From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 733C6C433EF for ; Fri, 4 Feb 2022 14:02:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1359205AbiBDOCG (ORCPT ); Fri, 4 Feb 2022 09:02:06 -0500 Received: from foss.arm.com ([217.140.110.172]:46498 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1359191AbiBDOCG (ORCPT ); Fri, 4 Feb 2022 09:02:06 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C563311D4; Fri, 4 Feb 2022 06:02:05 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0767A3F40C; Fri, 4 Feb 2022 06:02:02 -0800 (PST) Date: Fri, 4 Feb 2022 14:02:12 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 21/64] KVM: arm64: nv: Handle PSCI call via smc from the guest Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-22-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220128121912.509006-22-maz@kernel.org> Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org Hi Marc, The patch looks good to me. Checked kvm_hvc_call_handler(), it returns -1 only when kvm_psci_call() doesn't handle the function and PSCI_RET_NOT_SUPPORTED must be set by the caller (which is handle_smc). Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Jan 28, 2022 at 12:18:29PM +0000, Marc Zyngier wrote: > From: Jintack Lim > > VMs used to execute hvc #0 for the psci call if EL3 is not implemented. > However, when we come to provide the virtual EL2 mode to the VM, the > host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So, > it's hard to differentiate between them from the host hypervisor's point > of view. > > So, let the VM execute smc instruction for the psci call. On ARMv8.3, > even if EL3 is not implemented, a smc instruction executed at non-secure > EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than being treated as > UNDEFINED. So, the host hypervisor can handle this psci call without any > confusion. > > Signed-off-by: Jintack Lim > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/handle_exit.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index 2bbeed8c9786..0cedef6e0d80 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -62,6 +62,8 @@ static int handle_hvc(struct kvm_vcpu *vcpu) > > static int handle_smc(struct kvm_vcpu *vcpu) > { > + int ret; > + > /* > * "If an SMC instruction executed at Non-secure EL1 is > * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a > @@ -69,10 +71,28 @@ static int handle_smc(struct kvm_vcpu *vcpu) > * > * We need to advance the PC after the trap, as it would > * otherwise return to the same address... > + * > + * If imm is non-zero, it's not defined, so just skip it. > + */ > + if (kvm_vcpu_hvc_get_imm(vcpu)) { > + vcpu_set_reg(vcpu, 0, ~0UL); > + kvm_incr_pc(vcpu); > + return 1; > + } > + > + /* > + * If imm is zero, it's a psci call. > + * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed > + * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than > + * being treated as UNDEFINED. > */ > - vcpu_set_reg(vcpu, 0, ~0UL); > + ret = kvm_hvc_call_handler(vcpu); > + if (ret < 0) > + vcpu_set_reg(vcpu, 0, ~0UL); > + > kvm_incr_pc(vcpu); > - return 1; > + > + return ret; > } > > /* > -- > 2.30.2 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mm01.cs.columbia.edu (mm01.cs.columbia.edu [128.59.11.253]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8755DC433F5 for ; Fri, 4 Feb 2022 14:02:15 +0000 (UTC) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id E7F0141016; Fri, 4 Feb 2022 09:02:14 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Un2qlhVD7SR0; Fri, 4 Feb 2022 09:02:09 -0500 (EST) Received: from mm01.cs.columbia.edu (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 7804241003; Fri, 4 Feb 2022 09:02:09 -0500 (EST) Received: from localhost (localhost [127.0.0.1]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 58F6D41003 for ; Fri, 4 Feb 2022 09:02:08 -0500 (EST) X-Virus-Scanned: at lists.cs.columbia.edu Received: from mm01.cs.columbia.edu ([127.0.0.1]) by localhost (mm01.cs.columbia.edu [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id QBMr3bJoci8D for ; Fri, 4 Feb 2022 09:02:06 -0500 (EST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mm01.cs.columbia.edu (Postfix) with ESMTP id 908BC40066 for ; Fri, 4 Feb 2022 09:02:06 -0500 (EST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C563311D4; Fri, 4 Feb 2022 06:02:05 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0767A3F40C; Fri, 4 Feb 2022 06:02:02 -0800 (PST) Date: Fri, 4 Feb 2022 14:02:12 +0000 From: Alexandru Elisei To: Marc Zyngier Subject: Re: [PATCH v6 21/64] KVM: arm64: nv: Handle PSCI call via smc from the guest Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-22-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220128121912.509006-22-maz@kernel.org> Cc: kernel-team@android.com, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Chase Conklin , kvmarm@lists.cs.columbia.edu, mihai.carabas@oracle.com, Ganapatrao Kulkarni , "Russell King \(Oracle\)" , linux-arm-kernel@lists.infradead.org X-BeenThere: kvmarm@lists.cs.columbia.edu X-Mailman-Version: 2.1.14 Precedence: list List-Id: Where KVM/ARM decisions are made List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: kvmarm-bounces@lists.cs.columbia.edu Sender: kvmarm-bounces@lists.cs.columbia.edu Hi Marc, The patch looks good to me. Checked kvm_hvc_call_handler(), it returns -1 only when kvm_psci_call() doesn't handle the function and PSCI_RET_NOT_SUPPORTED must be set by the caller (which is handle_smc). Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Jan 28, 2022 at 12:18:29PM +0000, Marc Zyngier wrote: > From: Jintack Lim > > VMs used to execute hvc #0 for the psci call if EL3 is not implemented. > However, when we come to provide the virtual EL2 mode to the VM, the > host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So, > it's hard to differentiate between them from the host hypervisor's point > of view. > > So, let the VM execute smc instruction for the psci call. On ARMv8.3, > even if EL3 is not implemented, a smc instruction executed at non-secure > EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than being treated as > UNDEFINED. So, the host hypervisor can handle this psci call without any > confusion. > > Signed-off-by: Jintack Lim > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/handle_exit.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index 2bbeed8c9786..0cedef6e0d80 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -62,6 +62,8 @@ static int handle_hvc(struct kvm_vcpu *vcpu) > > static int handle_smc(struct kvm_vcpu *vcpu) > { > + int ret; > + > /* > * "If an SMC instruction executed at Non-secure EL1 is > * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a > @@ -69,10 +71,28 @@ static int handle_smc(struct kvm_vcpu *vcpu) > * > * We need to advance the PC after the trap, as it would > * otherwise return to the same address... > + * > + * If imm is non-zero, it's not defined, so just skip it. > + */ > + if (kvm_vcpu_hvc_get_imm(vcpu)) { > + vcpu_set_reg(vcpu, 0, ~0UL); > + kvm_incr_pc(vcpu); > + return 1; > + } > + > + /* > + * If imm is zero, it's a psci call. > + * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed > + * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than > + * being treated as UNDEFINED. > */ > - vcpu_set_reg(vcpu, 0, ~0UL); > + ret = kvm_hvc_call_handler(vcpu); > + if (ret < 0) > + vcpu_set_reg(vcpu, 0, ~0UL); > + > kvm_incr_pc(vcpu); > - return 1; > + > + return ret; > } > > /* > -- > 2.30.2 > _______________________________________________ kvmarm mailing list kvmarm@lists.cs.columbia.edu https://lists.cs.columbia.edu/mailman/listinfo/kvmarm From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id C7CD1C433EF for ; Fri, 4 Feb 2022 14:03:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=qTTcg0LUO0wcVmGac5KXCRQMb5Wvl/eLeYBRalc9WVU=; b=mqliNsiN52du/c OEnALbBaBwfg5uL8KnYJlp/dxwkptb7n/HMjARtOvqdUxYhrp7tJMnSv3UMDi1OQ9yczufAVHkTxs eWif1wH0u+nk7GNlBjFSg+87aTdUNj0yQKfb8gyH8sokWn6GXbxZLvy3nykW2nvGv+SZnRLC2BhO2 Ktt27hgviPqyc/x4MzqlDBgHfTA730gYolmmZ6jlI1ZtvM70WtHCk0EflwXMWrOFiws5ouUb+EUBX CynMrFW0eH7OI19hvZU54w2D7V/WwXlAytgqbV/mxcFnUbjHxiOvYyPw7aPjkAIvkcD/h7h1im5E7 SKqLZ0AMKsTHrByxvVlw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFzAA-004Ufj-Kb; Fri, 04 Feb 2022 14:02:10 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nFzA7-004Ues-NG for linux-arm-kernel@lists.infradead.org; Fri, 04 Feb 2022 14:02:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C563311D4; Fri, 4 Feb 2022 06:02:05 -0800 (PST) Received: from monolith.localdoman (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 0767A3F40C; Fri, 4 Feb 2022 06:02:02 -0800 (PST) Date: Fri, 4 Feb 2022 14:02:12 +0000 From: Alexandru Elisei To: Marc Zyngier Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org, Andre Przywara , Christoffer Dall , Jintack Lim , Haibo Xu , Ganapatrao Kulkarni , Chase Conklin , "Russell King (Oracle)" , James Morse , Suzuki K Poulose , karl.heubaum@oracle.com, mihai.carabas@oracle.com, miguel.luis@oracle.com, kernel-team@android.com Subject: Re: [PATCH v6 21/64] KVM: arm64: nv: Handle PSCI call via smc from the guest Message-ID: References: <20220128121912.509006-1-maz@kernel.org> <20220128121912.509006-22-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220128121912.509006-22-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220204_060207_818321_6E1C8ECA X-CRM114-Status: GOOD ( 27.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, The patch looks good to me. Checked kvm_hvc_call_handler(), it returns -1 only when kvm_psci_call() doesn't handle the function and PSCI_RET_NOT_SUPPORTED must be set by the caller (which is handle_smc). Reviewed-by: Alexandru Elisei Thanks, Alex On Fri, Jan 28, 2022 at 12:18:29PM +0000, Marc Zyngier wrote: > From: Jintack Lim > > VMs used to execute hvc #0 for the psci call if EL3 is not implemented. > However, when we come to provide the virtual EL2 mode to the VM, the > host OS inside the VM calls kvm_call_hyp() which is also hvc #0. So, > it's hard to differentiate between them from the host hypervisor's point > of view. > > So, let the VM execute smc instruction for the psci call. On ARMv8.3, > even if EL3 is not implemented, a smc instruction executed at non-secure > EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than being treated as > UNDEFINED. So, the host hypervisor can handle this psci call without any > confusion. > > Signed-off-by: Jintack Lim > Signed-off-by: Marc Zyngier > --- > arch/arm64/kvm/handle_exit.c | 24 ++++++++++++++++++++++-- > 1 file changed, 22 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index 2bbeed8c9786..0cedef6e0d80 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -62,6 +62,8 @@ static int handle_hvc(struct kvm_vcpu *vcpu) > > static int handle_smc(struct kvm_vcpu *vcpu) > { > + int ret; > + > /* > * "If an SMC instruction executed at Non-secure EL1 is > * trapped to EL2 because HCR_EL2.TSC is 1, the exception is a > @@ -69,10 +71,28 @@ static int handle_smc(struct kvm_vcpu *vcpu) > * > * We need to advance the PC after the trap, as it would > * otherwise return to the same address... > + * > + * If imm is non-zero, it's not defined, so just skip it. > + */ > + if (kvm_vcpu_hvc_get_imm(vcpu)) { > + vcpu_set_reg(vcpu, 0, ~0UL); > + kvm_incr_pc(vcpu); > + return 1; > + } > + > + /* > + * If imm is zero, it's a psci call. > + * Note that on ARMv8.3, even if EL3 is not implemented, SMC executed > + * at Non-secure EL1 is trapped to EL2 if HCR_EL2.TSC==1, rather than > + * being treated as UNDEFINED. > */ > - vcpu_set_reg(vcpu, 0, ~0UL); > + ret = kvm_hvc_call_handler(vcpu); > + if (ret < 0) > + vcpu_set_reg(vcpu, 0, ~0UL); > + > kvm_incr_pc(vcpu); > - return 1; > + > + return ret; > } > > /* > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel