From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-oi1-f177.google.com (mail-oi1-f177.google.com [209.85.167.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E734168 for ; Tue, 25 Jan 2022 19:04:47 +0000 (UTC) Received: by mail-oi1-f177.google.com with SMTP id bb37so32943958oib.1 for ; Tue, 25 Jan 2022 11:04:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vanguardiasur-com-ar.20210112.gappssmtp.com; s=20210112; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=xx6pPxDWusTyXDPmQQkkGMWNHJXpoVx/sQtpxlse54Q=; b=eL1XuwFOYuGbQjWefmXn6X59kcQdEJcCZ0aASe9nlq8PTeo3O0rnT1Qpn/1x7ivWkI 4ZhaWoAqzBJr/lYrFFq3xNGF4BFcQ8zYx7O0jheGHTbCPf14s6Z18suZMXkvpRlglKY3 lrfHLQSAHe4Zpg/wXlMH+melwJq2a6fGzyDvKR4QuygoxgypoukSjjY3xCXHtA8nyOKJ qMBZOZ9wR9cSVEkBdyyRJaddOaQqoix59xQlctEVoNA8U+kZLZ3VMwf1WUQrFJNo01Q8 agr1KSTZTMyd4gRVquSgfyVDjQrkZDrKTVlDvOOcbYYVQF5F2y0VG7XVMwJGbPx1tlSt tlog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=xx6pPxDWusTyXDPmQQkkGMWNHJXpoVx/sQtpxlse54Q=; b=L7QUaVkfpk9aFp58pPIbGEThAdwcsmyAH8DUP9bd2Wvyigz8hPcxeXINvpHKFPNwOQ qXaWFDCVhuco9ZHnU9bSajFBTCwU5D2oVbqOqSvtyXNFcAFgjnFPttV+Da2R4kt1Pxy7 bu+wewxCJqy/PxArSqflq6BauAraqBVaxTGT6hn9XyqoQ0NI6Oypu5ZzBxmdnSRYS/yo BMCMqAvj1yWTRvtZarh8aIKkt/ypWH12raocBluQxllYp/AkjSTbBufvp/WH9yL3GtM7 LDXDcctkpCDhVu0gUOQJKLi9CugUd6EwSHXPgHCXlpqSsUs8MaXY63JgFvZ8cgfZyWJT e4eg== X-Gm-Message-State: AOAM531XFrRt31R1sbCCql8KjE7dddXUGgH8PQolDl+afuyPMS3Fg3EM QQC3dRXBU/toRu533jvBCekkDQ== X-Google-Smtp-Source: ABdhPJxIP6+oD7gt9eH5+LFe++w9dIATHyaj+iBj28F054mPXWZGdYsjQk56Ug7nZcA1f6wMwrDeog== X-Received: by 2002:a05:6808:1b06:: with SMTP id bx6mr1656291oib.176.1643137486631; Tue, 25 Jan 2022 11:04:46 -0800 (PST) Received: from eze-laptop ([186.122.18.78]) by smtp.gmail.com with ESMTPSA id l18sm8138754otv.49.2022.01.25.11.04.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 25 Jan 2022 11:04:45 -0800 (PST) Date: Tue, 25 Jan 2022 16:04:38 -0300 From: Ezequiel Garcia To: Adam Ford Cc: linux-media@vger.kernel.org, aford@beaconembedded.com, cphealy@gmail.com, kernel test robot , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Message-ID: References: <20220125171129.472775-1-aford173@gmail.com> <20220125171129.472775-8-aford173@gmail.com> Precedence: bulk X-Mailing-List: linux-staging@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220125171129.472775-8-aford173@gmail.com> On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote: > With the Hantro G1 and G2 now setup to run independently, update > the device tree to allow both to operate. This requires the > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs > certain clock enabled to handle the gating of the G1 and G2 > fuses, the clock-parents and clock-rates for the various VPU's > to be moved into the pgc_vpu because they cannot get re-parented > once enabled, and the pgc_vpu is the highest in the chain. > > Signed-off-by: Adam Ford > Reported-by: kernel test robot It doesn't seem correct to have the Reported-by on this commit. Thanks, Ezequiel > Reviewed-by: Ezequiel Garcia > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 2df2510d0118..549b2440f55d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = ; > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, > + <600000000>, > + <800000000>, > + <0>; > }; > > pgc_disp: power-domain@7 { > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > - compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = , > - ; > - interrupt-names = "g1", "g2"; > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; > + }; > + > + vpu_blk_ctrl: blk-ctrl@38320000 { > + compatible = "fsl,imx8mq-vpu-blk-ctrl"; > + reg = <0x38320000 0x100>; > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; > + power-domain-names = "bus", "g1", "g2"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > - clock-names = "g1", "g2", "bus"; > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > - <&clk IMX8MQ_CLK_VPU_G2>, > - <&clk IMX8MQ_CLK_VPU_BUS>, > - <&clk IMX8MQ_VPU_PLL_BYPASS>; > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_SYS1_PLL_800M>, > - <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > - <800000000>, <0>; > - power-domains = <&pgc_vpu>; > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + clock-names = "g1", "g2"; > + #power-domain-cells = <1>; > }; > > pcie0: pcie@33800000 { > -- > 2.32.0 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 41929C433EF for ; Tue, 25 Jan 2022 19:05:03 +0000 (UTC) DKIM-Signature: v=1; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+linux-rockchip=archiver.kernel.org@lists.infradead.org On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote: > With the Hantro G1 and G2 now setup to run independently, update > the device tree to allow both to operate. This requires the > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs > certain clock enabled to handle the gating of the G1 and G2 > fuses, the clock-parents and clock-rates for the various VPU's > to be moved into the pgc_vpu because they cannot get re-parented > once enabled, and the pgc_vpu is the highest in the chain. > > Signed-off-by: Adam Ford > Reported-by: kernel test robot It doesn't seem correct to have the Reported-by on this commit. Thanks, Ezequiel > Reviewed-by: Ezequiel Garcia > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 2df2510d0118..549b2440f55d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = ; > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, > + <600000000>, > + <800000000>, > + <0>; > }; > > pgc_disp: power-domain@7 { > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > - compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = , > - ; > - interrupt-names = "g1", "g2"; > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; > + }; > + > + vpu_blk_ctrl: blk-ctrl@38320000 { > + compatible = "fsl,imx8mq-vpu-blk-ctrl"; > + reg = <0x38320000 0x100>; > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; > + power-domain-names = "bus", "g1", "g2"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > - clock-names = "g1", "g2", "bus"; > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > - <&clk IMX8MQ_CLK_VPU_G2>, > - <&clk IMX8MQ_CLK_VPU_BUS>, > - <&clk IMX8MQ_VPU_PLL_BYPASS>; > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_SYS1_PLL_800M>, > - <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > - <800000000>, <0>; > - power-domains = <&pgc_vpu>; > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + clock-names = "g1", "g2"; > + #power-domain-cells = <1>; > }; > > pcie0: pcie@33800000 { > -- > 2.32.0 > _______________________________________________ Linux-rockchip mailing list Linux-rockchip@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-rockchip From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 803CFC433EF for ; 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Tue, 25 Jan 2022 11:04:45 -0800 (PST) Date: Tue, 25 Jan 2022 16:04:38 -0300 From: Ezequiel Garcia To: Adam Ford Cc: linux-media@vger.kernel.org, aford@beaconembedded.com, cphealy@gmail.com, kernel test robot , Philipp Zabel , Mauro Carvalho Chehab , Rob Herring , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Greg Kroah-Hartman , Lucas Stach , linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-staging@lists.linux.dev Subject: Re: [PATCH V4 07/11] arm64: dts: imx8mq: Enable both G1 and G2 VPU's with vpu-blk-ctrl Message-ID: References: <20220125171129.472775-1-aford173@gmail.com> <20220125171129.472775-8-aford173@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220125171129.472775-8-aford173@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220125_110448_051942_FB26A7E7 X-CRM114-Status: GOOD ( 21.78 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jan 25, 2022 at 11:11:24AM -0600, Adam Ford wrote: > With the Hantro G1 and G2 now setup to run independently, update > the device tree to allow both to operate. This requires the > vpu-blk-ctrl node to be configured. Since vpu-blk-ctrl needs > certain clock enabled to handle the gating of the G1 and G2 > fuses, the clock-parents and clock-rates for the various VPU's > to be moved into the pgc_vpu because they cannot get re-parented > once enabled, and the pgc_vpu is the highest in the chain. > > Signed-off-by: Adam Ford > Reported-by: kernel test robot It doesn't seem correct to have the Reported-by on this commit. Thanks, Ezequiel > Reviewed-by: Ezequiel Garcia > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 2df2510d0118..549b2440f55d 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -737,7 +737,21 @@ pgc_gpu: power-domain@5 { > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = ; > - clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, > + <600000000>, > + <800000000>, > + <0>; > }; > > pgc_disp: power-domain@7 { > @@ -1457,30 +1471,31 @@ usb3_phy1: usb-phy@382f0040 { > status = "disabled"; > }; > > - vpu: video-codec@38300000 { > - compatible = "nxp,imx8mq-vpu"; > - reg = <0x38300000 0x10000>, > - <0x38310000 0x10000>, > - <0x38320000 0x10000>; > - reg-names = "g1", "g2", "ctrl"; > - interrupts = , > - ; > - interrupt-names = "g1", "g2"; > + vpu_g1: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu-g1"; > + reg = <0x38300000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G1>; > + }; > + > + vpu_g2: video-codec@38310000 { > + compatible = "nxp,imx8mq-vpu-g2"; > + reg = <0x38310000 0x10000>; > + interrupts = ; > + clocks = <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + power-domains = <&vpu_blk_ctrl IMX8MQ_VPUBLK_PD_G2>; > + }; > + > + vpu_blk_ctrl: blk-ctrl@38320000 { > + compatible = "fsl,imx8mq-vpu-blk-ctrl"; > + reg = <0x38320000 0x100>; > + power-domains = <&pgc_vpu>, <&pgc_vpu>, <&pgc_vpu>; > + power-domain-names = "bus", "g1", "g2"; > clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > - <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > - <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > - clock-names = "g1", "g2", "bus"; > - assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > - <&clk IMX8MQ_CLK_VPU_G2>, > - <&clk IMX8MQ_CLK_VPU_BUS>, > - <&clk IMX8MQ_VPU_PLL_BYPASS>; > - assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_VPU_PLL_OUT>, > - <&clk IMX8MQ_SYS1_PLL_800M>, > - <&clk IMX8MQ_VPU_PLL>; > - assigned-clock-rates = <600000000>, <600000000>, > - <800000000>, <0>; > - power-domains = <&pgc_vpu>; > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>; > + clock-names = "g1", "g2"; > + #power-domain-cells = <1>; > }; > > pcie0: pcie@33800000 { > -- > 2.32.0 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel