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[93.42.71.246]) by smtp.gmail.com with ESMTPSA id n2sm18074753wrw.63.2022.02.01.13.56.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Feb 2022 13:56:35 -0800 (PST) Date: Tue, 1 Feb 2022 22:56:23 +0100 From: Ansuel Smith To: Bjorn Andersson Cc: Andy Gross , Rob Herring , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 12/17] ARM: dts: qcom: add opp table for cpu and l2 for ipq8064 Message-ID: References: <20220118012051.21691-1-ansuelsmth@gmail.com> <20220118012051.21691-13-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Jan 31, 2022 at 04:49:07PM -0600, Bjorn Andersson wrote: > On Mon 17 Jan 19:20 CST 2022, Ansuel Smith wrote: > > > Add opp table for cpu and l2 cache. The l2 cache won't work as it would > > require a dedicated cpufreq driver to scale cache with core. > > > > Are you saying that the L2 cache frequency scaling doesn't work so you > put it there for completeness sake, or that it doesn't work without this > patch? > I put it here for completeness sake. A driver should use the opp table anyway, so I case I manage to make the cpufreq accepted upstream this is already present and can be used directly. > Could you please rewrite this to make it clear in the git history? > Hope it's not a problem, in theory should be correct to put it anyway as it does describe how the device works. > Thanks, > Bjorn > > > Opp-level is set based on the logic of > > 0: idle level > > 1: normal level > > 2: turbo level > > > > Signed-off-by: Ansuel Smith > > --- > > arch/arm/boot/dts/qcom-ipq8064.dtsi | 99 +++++++++++++++++++++++++++++ > > 1 file changed, 99 insertions(+) > > > > diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > index 6f9075489e58..1e6297d6f302 100644 > > --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi > > +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi > > @@ -48,6 +48,105 @@ L2: l2-cache { > > }; > > }; > > > > + opp_table_l2: opp_table_l2 { > > + compatible = "operating-points-v2"; > > + > > + opp-384000000 { > > + opp-hz = /bits/ 64 <384000000>; > > + opp-microvolt = <1100000>; > > + clock-latency-ns = <100000>; > > + opp-level = <0>; > > + }; > > + > > + opp-1000000000 { > > + opp-hz = /bits/ 64 <1000000000>; > > + opp-microvolt = <1100000>; > > + clock-latency-ns = <100000>; > > + opp-level = <1>; > > + }; > > + > > + opp-1200000000 { > > + opp-hz = /bits/ 64 <1200000000>; > > + opp-microvolt = <1150000>; > > + clock-latency-ns = <100000>; > > + opp-level = <2>; > > + }; > > + }; > > + > > + opp_table0: opp_table0 { > > + compatible = "operating-points-v2-kryo-cpu"; > > + nvmem-cells = <&speedbin_efuse>; > > + > > + /* > > + * Voltage thresholds are > > + */ > > + opp-384000000 { > > + opp-hz = /bits/ 64 <384000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1000000 950000 1050000>; > > + opp-microvolt-speed0-pvs1-v0 = <925000 878750 971250>; > > + opp-microvolt-speed0-pvs2-v0 = <875000 831250 918750>; > > + opp-microvolt-speed0-pvs3-v0 = <800000 760000 840000>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <0>; > > + }; > > + > > + opp-600000000 { > > + opp-hz = /bits/ 64 <600000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1050000 997500 1102500>; > > + opp-microvolt-speed0-pvs1-v0 = <975000 926250 1023750>; > > + opp-microvolt-speed0-pvs2-v0 = <925000 878750 971250>; > > + opp-microvolt-speed0-pvs3-v0 = <850000 807500 892500>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <1>; > > + }; > > + > > + opp-800000000 { > > + opp-hz = /bits/ 64 <800000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1100000 1045000 1155000>; > > + opp-microvolt-speed0-pvs1-v0 = <1025000 973750 1076250>; > > + opp-microvolt-speed0-pvs2-v0 = <995000 945250 1044750>; > > + opp-microvolt-speed0-pvs3-v0 = <900000 855000 945000>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <1>; > > + }; > > + > > + opp-1000000000 { > > + opp-hz = /bits/ 64 <1000000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1150000 1092500 1207500>; > > + opp-microvolt-speed0-pvs1-v0 = <1075000 1021250 1128750>; > > + opp-microvolt-speed0-pvs2-v0 = <1025000 973750 1076250>; > > + opp-microvolt-speed0-pvs3-v0 = <950000 902500 997500>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <1>; > > + }; > > + > > + opp-1200000000 { > > + opp-hz = /bits/ 64 <1200000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1200000 1140000 1260000>; > > + opp-microvolt-speed0-pvs1-v0 = <1125000 1068750 1181250>; > > + opp-microvolt-speed0-pvs2-v0 = <1075000 1021250 1128750>; > > + opp-microvolt-speed0-pvs3-v0 = <1000000 950000 1050000>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <2>; > > + }; > > + > > + opp-1400000000 { > > + opp-hz = /bits/ 64 <1400000000>; > > + opp-microvolt-speed0-pvs0-v0 = <1250000 1187500 1312500>; > > + opp-microvolt-speed0-pvs1-v0 = <1175000 1116250 1233750>; > > + opp-microvolt-speed0-pvs2-v0 = <1125000 1068750 1181250>; > > + opp-microvolt-speed0-pvs3-v0 = <1050000 997500 1102500>; > > + opp-supported-hw = <0x1>; > > + clock-latency-ns = <100000>; > > + opp-level = <2>; > > + }; > > + }; > > + > > thermal-zones { > > sensor0-thermal { > > polling-delay-passive = <0>; > > -- > > 2.33.1 > > -- Ansuel