* [REPOST PATCH v4 00/13] drm/msm: Add Display Stream Compression Support
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
support in encoder. We also add support in DSI and introduce required
topology changes.
In order for panel to set the DSC parameters we add dsc in drm_panel and set
it from the msm driver.
We still have dsc as a globabl entity. I think while doing DP + DSC we
should be able to update it, right now comprehending the requirements are
bit difficult.
Complete changes which enable this for Pixel3 along with panel driver (not
part of this series) and DT changes can be found at:
git.linaro.org/people/vinod.koul/kernel.git pixel/dsc_v4
Comments welcome!
Changes since v3:
- Merge changes from Dmitry to have dsc per encoder instance
- add warning for dsc and mode3d enabled together
- set dsc in dpu_encoder_phys_vid as well
- remove dsc hardcoded mask
- use devm_kzalloc for memory allocation for dsc
Changes since v2:
- Fix comments by Dimitry except the dsc being global.
- Move RM patch later for dependency on topology now
- Add patch for mode valid callback for dsi_mgr
- Add missing structure documentation patch
- Fix errors in mode_3d changes
- Rebase on v5.16-rc1 and test
Changes since v1:
- Fix various issues spotted by kbuildbot
- Rebase to v5.15-rc3
- Remove unused fields and duplicate defines
- Enable DSC blocks only when DSC is enabled
- remove sdm845 feature mask, use 0
- Check for DSC in hw_ctl
Changes since RFC:
- Drop the DT binding patch as we derive the configuration from panel
- Drop the drm api patch as we no longer need it (use pps drm api)
- Fix comments raised by Dimitry
- Add dsc parameters calculation from downstream
Vinod Koul (13):
drm/msm/dsi: add support for dsc data
drm/msm/dsi: Pass DSC params to drm_panel
drm/msm/disp/dpu1: Add support for DSC
drm/msm/disp/dpu1: Add support for DSC in pingpong block
drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
drm/msm/disp/dpu1: Add DSC support in hw_ctl
drm/msm/disp/dpu1: Add support for DSC in encoder
drm/msm/disp/dpu1: Don't use DSC with mode_3d
drm/msm: Add missing structure documentation
drm/msm/disp/dpu1: Add support for DSC in topology
drm/msm/disp/dpu1: Add DSC support in RM
drm/msm/dsi: add mode valid callback for dsi_mgr
drm/msm/dsi: Add support for DSC configuration
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 177 ++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 +++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.c | 5 +
drivers/gpu/drm/msm/dsi/dsi.h | 3 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 289 +++++++++++++++++-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 +
drivers/gpu/drm/msm/msm_drv.h | 26 ++
include/drm/drm_panel.h | 7 +
25 files changed, 1001 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
--
2.31.1
^ permalink raw reply [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 00/13] drm/msm: Add Display Stream Compression Support
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Display Stream Compression (DSC) compresses the display stream in host which
is later decoded by panel. This series enables this for Qualcomm msm driver.
This was tested on Google Pixel3 phone which use LGE SW43408 panel.
The changes include DSC data and hardware block enabling for DPU1 then
support in encoder. We also add support in DSI and introduce required
topology changes.
In order for panel to set the DSC parameters we add dsc in drm_panel and set
it from the msm driver.
We still have dsc as a globabl entity. I think while doing DP + DSC we
should be able to update it, right now comprehending the requirements are
bit difficult.
Complete changes which enable this for Pixel3 along with panel driver (not
part of this series) and DT changes can be found at:
git.linaro.org/people/vinod.koul/kernel.git pixel/dsc_v4
Comments welcome!
Changes since v3:
- Merge changes from Dmitry to have dsc per encoder instance
- add warning for dsc and mode3d enabled together
- set dsc in dpu_encoder_phys_vid as well
- remove dsc hardcoded mask
- use devm_kzalloc for memory allocation for dsc
Changes since v2:
- Fix comments by Dimitry except the dsc being global.
- Move RM patch later for dependency on topology now
- Add patch for mode valid callback for dsi_mgr
- Add missing structure documentation patch
- Fix errors in mode_3d changes
- Rebase on v5.16-rc1 and test
Changes since v1:
- Fix various issues spotted by kbuildbot
- Rebase to v5.15-rc3
- Remove unused fields and duplicate defines
- Enable DSC blocks only when DSC is enabled
- remove sdm845 feature mask, use 0
- Check for DSC in hw_ctl
Changes since RFC:
- Drop the DT binding patch as we derive the configuration from panel
- Drop the drm api patch as we no longer need it (use pps drm api)
- Fix comments raised by Dimitry
- Add dsc parameters calculation from downstream
Vinod Koul (13):
drm/msm/dsi: add support for dsc data
drm/msm/dsi: Pass DSC params to drm_panel
drm/msm/disp/dpu1: Add support for DSC
drm/msm/disp/dpu1: Add support for DSC in pingpong block
drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
drm/msm/disp/dpu1: Add DSC support in hw_ctl
drm/msm/disp/dpu1: Add support for DSC in encoder
drm/msm/disp/dpu1: Don't use DSC with mode_3d
drm/msm: Add missing structure documentation
drm/msm/disp/dpu1: Add support for DSC in topology
drm/msm/disp/dpu1: Add DSC support in RM
drm/msm/dsi: add mode valid callback for dsi_mgr
drm/msm/dsi: Add support for DSC configuration
drivers/gpu/drm/msm/Makefile | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 177 ++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 +
.../drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 18 +-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 +++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 ++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 +
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
drivers/gpu/drm/msm/dsi/dsi.c | 5 +
drivers/gpu/drm/msm/dsi/dsi.h | 3 +
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 289 +++++++++++++++++-
drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 +
drivers/gpu/drm/msm/msm_drv.h | 26 ++
include/drm/drm_panel.h | 7 +
25 files changed, 1001 insertions(+), 4 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
--
2.31.1
^ permalink raw reply [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 15 ++++
2 files changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 6b3ced4aaaf5..27553194f9fa 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,8 @@
#define DSI_RESET_TOGGLE_DELAY_MS 20
+static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
+
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
{
u32 ver;
@@ -157,6 +159,7 @@ struct msm_dsi_host {
struct regmap *sfpb;
struct drm_display_mode *mode;
+ struct msm_display_dsc_config *dsc;
/* connected device info */
struct device_node *device_node;
@@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
+static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
+ 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
+ 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
+};
+
+/* only 8bpc, 8bpp added */
+static char min_qp[DSC_NUM_BUF_RANGES] = {
+ 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
+};
+
+static char max_qp[DSC_NUM_BUF_RANGES] = {
+ 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
+};
+
+static char bpg_offset[DSC_NUM_BUF_RANGES] = {
+ 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
+};
+
+static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
+{
+ int mux_words_size;
+ int groups_per_line, groups_total;
+ int min_rate_buffer_size;
+ int hrd_delay;
+ int pre_num_extra_mux_bits, num_extra_mux_bits;
+ int slice_bits;
+ int target_bpp_x16;
+ int data;
+ int final_value, final_scale;
+ int i;
+
+ dsc->drm->rc_model_size = 8192;
+ dsc->drm->first_line_bpg_offset = 12;
+ dsc->drm->rc_edge_factor = 6;
+ dsc->drm->rc_tgt_offset_high = 3;
+ dsc->drm->rc_tgt_offset_low = 3;
+ dsc->drm->simple_422 = 0;
+ dsc->drm->convert_rgb = 1;
+ dsc->drm->vbr_enable = 0;
+
+ /* handle only bpp = bpc = 8 */
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
+ dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
+ dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
+ dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
+ }
+
+ dsc->drm->initial_offset = 6144; /* Not bpp 12 */
+ if (dsc->drm->bits_per_pixel != 8)
+ dsc->drm->initial_offset = 2048; /* bpp = 12 */
+
+ mux_words_size = 48; /* bpc == 8/10 */
+ if (dsc->drm->bits_per_component == 12)
+ mux_words_size = 64;
+
+ dsc->drm->initial_xmit_delay = 512;
+ dsc->drm->initial_scale_value = 32;
+ dsc->drm->first_line_bpg_offset = 12;
+ dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
+
+ /* bpc 8 */
+ dsc->drm->flatness_min_qp = 3;
+ dsc->drm->flatness_max_qp = 12;
+ dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
+ dsc->drm->rc_quant_incr_limit0 = 11;
+ dsc->drm->rc_quant_incr_limit1 = 11;
+ dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+
+ /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
+ * params are calculated
+ */
+ dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
+ groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
+ dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
+ if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
+ dsc->drm->slice_chunk_size++;
+
+ /* rbs-min */
+ min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
+ dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
+ groups_per_line * dsc->drm->first_line_bpg_offset;
+
+ hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
+
+ dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
+
+ dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
+ (dsc->drm->rc_model_size - dsc->drm->initial_offset);
+
+ slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
+
+ groups_total = groups_per_line * dsc->drm->slice_height;
+
+ data = dsc->drm->first_line_bpg_offset * 2048;
+
+ dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
+
+ pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
+
+ num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
+ ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
+
+ data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
+ dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
+
+ /* bpp * 16 + 0.5 */
+ data = dsc->drm->bits_per_pixel * 16;
+ data *= 2;
+ data++;
+ data /= 2;
+ target_bpp_x16 = data;
+
+ data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
+ final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
+ dsc->drm->final_offset = final_value;
+
+ final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
+
+ data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
+ dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
+
+ dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
+
+ return 0;
+}
+
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
{
struct device *dev = &msm_host->pdev->dev;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index d7574e6bd4e4..384f9bad4760 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -30,6 +30,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_fb_helper.h>
+#include <drm/drm_dsc.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>
@@ -134,6 +135,20 @@ struct msm_drm_thread {
struct kthread_worker *worker;
};
+/* DSC config */
+struct msm_display_dsc_config {
+ struct drm_dsc_config *drm;
+
+ u32 initial_lines;
+ u32 pkt_per_line;
+ u32 bytes_in_slice;
+ u32 bytes_per_pkt;
+ u32 eol_byte_num;
+ u32 pclk_per_line;
+ u32 slice_last_group_size;
+ u32 det_thresh_flatness;
+};
+
struct msm_drm_private {
struct drm_device *dev;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Display Stream Compression (DSC) parameters need to be calculated. Add
helpers and struct msm_display_dsc_config in msm_drv for this
msm_display_dsc_config uses drm_dsc_config for DSC parameters.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 15 ++++
2 files changed, 147 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 6b3ced4aaaf5..27553194f9fa 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -31,6 +31,8 @@
#define DSI_RESET_TOGGLE_DELAY_MS 20
+static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
+
static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
{
u32 ver;
@@ -157,6 +159,7 @@ struct msm_dsi_host {
struct regmap *sfpb;
struct drm_display_mode *mode;
+ struct msm_display_dsc_config *dsc;
/* connected device info */
struct device_node *device_node;
@@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
return -EINVAL;
}
+static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
+ 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
+ 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
+};
+
+/* only 8bpc, 8bpp added */
+static char min_qp[DSC_NUM_BUF_RANGES] = {
+ 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
+};
+
+static char max_qp[DSC_NUM_BUF_RANGES] = {
+ 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
+};
+
+static char bpg_offset[DSC_NUM_BUF_RANGES] = {
+ 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
+};
+
+static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
+{
+ int mux_words_size;
+ int groups_per_line, groups_total;
+ int min_rate_buffer_size;
+ int hrd_delay;
+ int pre_num_extra_mux_bits, num_extra_mux_bits;
+ int slice_bits;
+ int target_bpp_x16;
+ int data;
+ int final_value, final_scale;
+ int i;
+
+ dsc->drm->rc_model_size = 8192;
+ dsc->drm->first_line_bpg_offset = 12;
+ dsc->drm->rc_edge_factor = 6;
+ dsc->drm->rc_tgt_offset_high = 3;
+ dsc->drm->rc_tgt_offset_low = 3;
+ dsc->drm->simple_422 = 0;
+ dsc->drm->convert_rgb = 1;
+ dsc->drm->vbr_enable = 0;
+
+ /* handle only bpp = bpc = 8 */
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
+ dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
+
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
+ dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
+ dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
+ }
+
+ dsc->drm->initial_offset = 6144; /* Not bpp 12 */
+ if (dsc->drm->bits_per_pixel != 8)
+ dsc->drm->initial_offset = 2048; /* bpp = 12 */
+
+ mux_words_size = 48; /* bpc == 8/10 */
+ if (dsc->drm->bits_per_component == 12)
+ mux_words_size = 64;
+
+ dsc->drm->initial_xmit_delay = 512;
+ dsc->drm->initial_scale_value = 32;
+ dsc->drm->first_line_bpg_offset = 12;
+ dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
+
+ /* bpc 8 */
+ dsc->drm->flatness_min_qp = 3;
+ dsc->drm->flatness_max_qp = 12;
+ dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
+ dsc->drm->rc_quant_incr_limit0 = 11;
+ dsc->drm->rc_quant_incr_limit1 = 11;
+ dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
+
+ /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
+ * params are calculated
+ */
+ dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
+ groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
+ dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
+ if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
+ dsc->drm->slice_chunk_size++;
+
+ /* rbs-min */
+ min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
+ dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
+ groups_per_line * dsc->drm->first_line_bpg_offset;
+
+ hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
+
+ dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
+
+ dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
+ (dsc->drm->rc_model_size - dsc->drm->initial_offset);
+
+ slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
+
+ groups_total = groups_per_line * dsc->drm->slice_height;
+
+ data = dsc->drm->first_line_bpg_offset * 2048;
+
+ dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
+
+ pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
+
+ num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
+ ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
+
+ data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
+ dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
+
+ /* bpp * 16 + 0.5 */
+ data = dsc->drm->bits_per_pixel * 16;
+ data *= 2;
+ data++;
+ data /= 2;
+ target_bpp_x16 = data;
+
+ data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
+ final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
+ dsc->drm->final_offset = final_value;
+
+ final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
+
+ data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
+ dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
+
+ dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
+
+ return 0;
+}
+
static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
{
struct device *dev = &msm_host->pdev->dev;
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index d7574e6bd4e4..384f9bad4760 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -30,6 +30,7 @@
#include <drm/drm_plane_helper.h>
#include <drm/drm_probe_helper.h>
#include <drm/drm_fb_helper.h>
+#include <drm/drm_dsc.h>
#include <drm/msm_drm.h>
#include <drm/drm_gem.h>
@@ -134,6 +135,20 @@ struct msm_drm_thread {
struct kthread_worker *worker;
};
+/* DSC config */
+struct msm_display_dsc_config {
+ struct drm_dsc_config *drm;
+
+ u32 initial_lines;
+ u32 pkt_per_line;
+ u32 bytes_in_slice;
+ u32 bytes_per_pkt;
+ u32 eol_byte_num;
+ u32 pclk_per_line;
+ u32 slice_last_group_size;
+ u32 det_thresh_flatness;
+};
+
struct msm_drm_private {
struct drm_device *dev;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
which will enable and configure DSC hardware blocks accordingly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
include/drm/drm_panel.h | 7 +++++++
6 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 47fe11a84a77..ef6ddac22767 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
MSM_DISPLAY_CAP_CMD_MODE :
MSM_DISPLAY_CAP_VID_MODE;
+ info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
+
if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
if (rc) {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 052548883d27..3aeac15e7421 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
return !(host_flags & MIPI_DSI_MODE_VIDEO);
}
+struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+{
+ return msm_dsi_host_get_dsc_config(msm_dsi->host);
+}
+
static int dsi_get_phy(struct msm_dsi *msm_dsi)
{
struct platform_device *pdev = msm_dsi->pdev;
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index c8dedc95428c..16cd9b2fce86 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
+struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
/* dsi phy */
struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 27553194f9fa..7e9913eff724 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
+ struct drm_panel *panel;
int ret;
msm_host->dev = dev;
+ panel = msm_dsi_host_get_panel(&msm_host->base);
+
+ if (panel && panel->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+
+ if (!dsc) {
+ dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
+ if (!dsc)
+ return -ENOMEM;
+ dsc->drm = panel->dsc;
+ msm_host->dsc = dsc;
+ }
+ }
+
ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
if (ret) {
pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
@@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
}
+
+struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
+{
+ struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+ return msm_host->dsc;
+}
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 384f9bad4760..e7a312edfe67 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -119,6 +119,7 @@ struct msm_display_topology {
* based on num_of_h_tiles
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
+ * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
int intf_type;
@@ -126,6 +127,7 @@ struct msm_display_info {
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_te_using_watchdog_timer;
+ struct msm_display_dsc_config *dsc;
};
/* Commit/Event thread specific structure */
@@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
+struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
#else
static inline void __init msm_dsi_register(void)
{
@@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
{
return false;
}
+
+static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+{
+ return NULL;
+}
#endif
#ifdef CONFIG_DRM_MSM_DP
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 4602f833eb51..eb8ae9bf32ed 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -171,6 +171,13 @@ struct drm_panel {
* Panel entry in registry.
*/
struct list_head list;
+
+ /**
+ * @dsc:
+ *
+ * Panel DSC pps payload to be sent
+ */
+ struct drm_dsc_config *dsc;
};
void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
When DSC is enabled, we need to pass the DSC parameters to panel driver
as well, so add a dsc parameter in panel and set it when DSC is enabled
Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
which will enable and configure DSC hardware blocks accordingly.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
drivers/gpu/drm/msm/dsi/dsi.h | 1 +
drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
include/drm/drm_panel.h | 7 +++++++
6 files changed, 45 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 47fe11a84a77..ef6ddac22767 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
MSM_DISPLAY_CAP_CMD_MODE :
MSM_DISPLAY_CAP_VID_MODE;
+ info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
+
if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
if (rc) {
diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
index 052548883d27..3aeac15e7421 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.c
+++ b/drivers/gpu/drm/msm/dsi/dsi.c
@@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
return !(host_flags & MIPI_DSI_MODE_VIDEO);
}
+struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+{
+ return msm_dsi_host_get_dsc_config(msm_dsi->host);
+}
+
static int dsi_get_phy(struct msm_dsi *msm_dsi)
{
struct platform_device *pdev = msm_dsi->pdev;
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index c8dedc95428c..16cd9b2fce86 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
+struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
/* dsi phy */
struct msm_dsi_phy;
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 27553194f9fa..7e9913eff724 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
{
struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
+ struct drm_panel *panel;
int ret;
msm_host->dev = dev;
+ panel = msm_dsi_host_get_panel(&msm_host->base);
+
+ if (panel && panel->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+
+ if (!dsc) {
+ dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
+ if (!dsc)
+ return -ENOMEM;
+ dsc->drm = panel->dsc;
+ msm_host->dsc = dsc;
+ }
+ }
+
ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
if (ret) {
pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
@@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
}
+
+struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
+{
+ struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+
+ return msm_host->dsc;
+}
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 384f9bad4760..e7a312edfe67 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -119,6 +119,7 @@ struct msm_display_topology {
* based on num_of_h_tiles
* @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
* used instead of panel TE in cmd mode panels
+ * @dsc: DSC configuration data for DSC-enabled displays
*/
struct msm_display_info {
int intf_type;
@@ -126,6 +127,7 @@ struct msm_display_info {
uint32_t num_of_h_tiles;
uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
bool is_te_using_watchdog_timer;
+ struct msm_display_dsc_config *dsc;
};
/* Commit/Event thread specific structure */
@@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
+struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
#else
static inline void __init msm_dsi_register(void)
{
@@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
{
return false;
}
+
+static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
+{
+ return NULL;
+}
#endif
#ifdef CONFIG_DRM_MSM_DP
diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
index 4602f833eb51..eb8ae9bf32ed 100644
--- a/include/drm/drm_panel.h
+++ b/include/drm/drm_panel.h
@@ -171,6 +171,13 @@ struct drm_panel {
* Panel entry in registry.
*/
struct list_head list;
+
+ /**
+ * @dsc:
+ *
+ * Panel DSC pps payload to be sent
+ */
+ struct drm_dsc_config *dsc;
};
void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++
5 files changed, 314 insertions(+)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 03ab55c37beb..7ec3c70c77ce 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -56,6 +56,7 @@ msm-y := \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_ctl.o \
+ disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 31af04afda7d..5fc0888351c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -556,6 +556,16 @@ struct dpu_merge_3d_cfg {
const struct dpu_merge_3d_sub_blks *sblk;
};
+/**
+ * struct dpu_dsc_cfg - information of DSC blocks
+ * @id enum identifying this block
+ * @base register offset of this block
+ * @features bit mask identifying sub-blocks/features
+ */
+struct dpu_dsc_cfg {
+ DPU_HW_BLK_INFO;
+};
+
/**
* struct dpu_intf_cfg - information of timing engine blocks
* @id enum identifying this block
@@ -752,6 +762,9 @@ struct dpu_mdss_cfg {
u32 merge_3d_count;
const struct dpu_merge_3d_cfg *merge_3d;
+ u32 dsc_count;
+ struct dpu_dsc_cfg *dsc;
+
u32 intf_count;
const struct dpu_intf_cfg *intf;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
new file mode 100644
index 000000000000..449d6f1dad28
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021, Linaro Limited
+ */
+
+#include "dpu_kms.h"
+#include "dpu_hw_catalog.h"
+#include "dpu_hwio.h"
+#include "dpu_hw_mdss.h"
+#include "dpu_hw_dsc.h"
+
+#define DSC_COMMON_MODE 0x000
+#define DSC_ENC 0X004
+#define DSC_PICTURE 0x008
+#define DSC_SLICE 0x00C
+#define DSC_CHUNK_SIZE 0x010
+#define DSC_DELAY 0x014
+#define DSC_SCALE_INITIAL 0x018
+#define DSC_SCALE_DEC_INTERVAL 0x01C
+#define DSC_SCALE_INC_INTERVAL 0x020
+#define DSC_FIRST_LINE_BPG_OFFSET 0x024
+#define DSC_BPG_OFFSET 0x028
+#define DSC_DSC_OFFSET 0x02C
+#define DSC_FLATNESS 0x030
+#define DSC_RC_MODEL_SIZE 0x034
+#define DSC_RC 0x038
+#define DSC_RC_BUF_THRESH 0x03C
+#define DSC_RANGE_MIN_QP 0x074
+#define DSC_RANGE_MAX_QP 0x0B0
+#define DSC_RANGE_BPG_OFFSET 0x0EC
+
+static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
+{
+ struct dpu_hw_blk_reg_map *c = &dsc->hw;
+
+ DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
+}
+
+static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc, u32 mode)
+{
+ struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
+ u32 data, lsb, bpp;
+ u32 initial_lines = dsc->initial_lines;
+ bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
+
+ DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
+
+ if (is_cmd_mode)
+ initial_lines += 1;
+
+ data = (initial_lines << 20);
+ data |= ((dsc->slice_last_group_size - 1) << 18);
+ /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
+ data |= dsc->drm->bits_per_pixel << 12;
+ lsb = dsc->drm->bits_per_pixel % 4;
+ bpp = dsc->drm->bits_per_pixel / 4;
+ bpp *= 4;
+ bpp <<= 4;
+ bpp |= lsb;
+
+ data |= bpp << 8;
+ data |= (dsc->drm->block_pred_enable << 7);
+ data |= (dsc->drm->line_buf_depth << 3);
+ data |= (dsc->drm->simple_422 << 2);
+ data |= (dsc->drm->convert_rgb << 1);
+ data |= dsc->drm->bits_per_component;
+
+ DPU_REG_WRITE(c, DSC_ENC, data);
+
+ data = dsc->drm->pic_width << 16;
+ data |= dsc->drm->pic_height;
+ DPU_REG_WRITE(c, DSC_PICTURE, data);
+
+ data = dsc->drm->slice_width << 16;
+ data |= dsc->drm->slice_height;
+ DPU_REG_WRITE(c, DSC_SLICE, data);
+
+ data = dsc->drm->slice_chunk_size << 16;
+ DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
+
+ data = dsc->drm->initial_dec_delay << 16;
+ data |= dsc->drm->initial_xmit_delay;
+ DPU_REG_WRITE(c, DSC_DELAY, data);
+
+ data = dsc->drm->initial_scale_value;
+ DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
+
+ data = dsc->drm->scale_decrement_interval;
+ DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
+
+ data = dsc->drm->scale_increment_interval;
+ DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
+
+ data = dsc->drm->first_line_bpg_offset;
+ DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
+
+ data = dsc->drm->nfl_bpg_offset << 16;
+ data |= dsc->drm->slice_bpg_offset;
+ DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
+
+ data = dsc->drm->initial_offset << 16;
+ data |= dsc->drm->final_offset;
+ DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
+
+ data = dsc->det_thresh_flatness << 10;
+ data |= dsc->drm->flatness_max_qp << 5;
+ data |= dsc->drm->flatness_min_qp;
+ DPU_REG_WRITE(c, DSC_FLATNESS, data);
+
+ data = dsc->drm->rc_model_size;
+ DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
+
+ data = dsc->drm->rc_tgt_offset_low << 18;
+ data |= dsc->drm->rc_tgt_offset_high << 14;
+ data |= dsc->drm->rc_quant_incr_limit1 << 9;
+ data |= dsc->drm->rc_quant_incr_limit0 << 4;
+ data |= dsc->drm->rc_edge_factor;
+ DPU_REG_WRITE(c, DSC_RC, data);
+}
+
+static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc)
+{
+ struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
+ struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
+ u32 off;
+ int i;
+
+ off = DSC_RC_BUF_THRESH;
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
+ DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
+ off += 4;
+ }
+
+ off = DSC_RANGE_MIN_QP;
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_min_qp);
+ off += 4;
+ }
+
+ off = DSC_RANGE_MAX_QP;
+ for (i = 0; i < 15; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_max_qp);
+ off += 4;
+ }
+
+ off = DSC_RANGE_BPG_OFFSET;
+ for (i = 0; i < 15; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
+ off += 4;
+ }
+}
+
+static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
+ struct dpu_mdss_cfg *m,
+ void __iomem *addr,
+ struct dpu_hw_blk_reg_map *b)
+{
+ int i;
+
+ for (i = 0; i < m->dsc_count; i++) {
+ if (dsc == m->dsc[i].id) {
+ b->base_off = addr;
+ b->blk_off = m->dsc[i].base;
+ b->length = m->dsc[i].len;
+ b->hwversion = m->hwversion;
+ b->log_mask = DPU_DBG_MASK_DSC;
+ return &m->dsc[i];
+ }
+ }
+
+ return NULL;
+}
+
+static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
+ unsigned long cap)
+{
+ ops->dsc_disable = dpu_hw_dsc_disable;
+ ops->dsc_config = dpu_hw_dsc_config;
+ ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
+};
+
+struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
+ struct dpu_mdss_cfg *m)
+{
+ struct dpu_hw_dsc *c;
+ struct dpu_dsc_cfg *cfg;
+
+ c = kzalloc(sizeof(*c), GFP_KERNEL);
+ if (!c)
+ return ERR_PTR(-ENOMEM);
+
+ cfg = _dsc_offset(idx, m, addr, &c->hw);
+ if (IS_ERR_OR_NULL(cfg)) {
+ kfree(c);
+ return ERR_PTR(-EINVAL);
+ }
+
+ c->idx = idx;
+ c->caps = cfg;
+ _setup_dsc_ops(&c->ops, c->caps->features);
+
+ return c;
+}
+
+void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
+{
+ kfree(dsc);
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
new file mode 100644
index 000000000000..648c9e4d8749
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020-2021, Linaro Limited */
+
+#ifndef _DPU_HW_DSC_H
+#define _DPU_HW_DSC_H
+
+#include <drm/drm_dsc.h>
+
+#define DSC_MODE_SPLIT_PANEL BIT(0)
+#define DSC_MODE_MULTIPLEX BIT(1)
+#define DSC_MODE_VIDEO BIT(2)
+
+struct dpu_hw_dsc;
+
+/**
+ * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
+ * Assumption is these functions will be called after clocks are enabled
+ */
+struct dpu_hw_dsc_ops {
+ /**
+ * dsc_disable - disable dsc
+ * @hw_dsc: Pointer to dsc context
+ */
+ void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
+
+ /**
+ * dsc_config - configures dsc encoder
+ * @hw_dsc: Pointer to dsc context
+ * @dsc: panel dsc parameters
+ * @mode: dsc topology mode to be set
+ */
+ void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc, u32 mode);
+
+ /**
+ * dsc_config_thresh - programs panel thresholds
+ * @hw_dsc: Pointer to dsc context
+ * @dsc: panel dsc parameters
+ */
+ void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc);
+};
+
+struct dpu_hw_dsc {
+ struct dpu_hw_blk base;
+ struct dpu_hw_blk_reg_map hw;
+
+ /* dsc */
+ enum dpu_dsc idx;
+ const struct dpu_dsc_cfg *caps;
+
+ /* ops */
+ struct dpu_hw_dsc_ops ops;
+};
+
+/**
+ * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
+ * @idx: DSC index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * @m: Pointer to mdss catalog data
+ * Returns: Error code or allocated dpu_hw_dsc context
+ */
+struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
+ struct dpu_mdss_cfg *m);
+
+/**
+ * dpu_hw_dsc_destroy - destroys dsc driver context
+ * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
+ */
+void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
+
+static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
+{
+ return container_of(hw, struct dpu_hw_dsc, base);
+}
+
+#endif /* _DPU_HW_DSC_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index bb9ceadeb0bb..b0ce8cb97d22 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
DPU_HW_BLK_WB,
DPU_HW_BLK_DSPP,
DPU_HW_BLK_MERGE_3D,
+ DPU_HW_BLK_DSC,
DPU_HW_BLK_MAX,
};
@@ -176,6 +177,17 @@ enum dpu_ctl {
CTL_MAX
};
+enum dpu_dsc {
+ DSC_NONE = 0,
+ DSC_0,
+ DSC_1,
+ DSC_2,
+ DSC_3,
+ DSC_4,
+ DSC_5,
+ DSC_MAX
+};
+
enum dpu_pingpong {
PINGPONG_0 = 1,
PINGPONG_1,
@@ -437,5 +449,6 @@ struct dpu_mdss_color {
#define DPU_DBG_MASK_VBIF (1 << 8)
#define DPU_DBG_MASK_ROT (1 << 9)
#define DPU_DBG_MASK_DSPP (1 << 10)
+#define DPU_DBG_MASK_DSC (1 << 11)
#endif /* _DPU_HW_MDSS_H */
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
support by adding hw blocks for DSC
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/Makefile | 1 +
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++
5 files changed, 314 insertions(+)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
index 03ab55c37beb..7ec3c70c77ce 100644
--- a/drivers/gpu/drm/msm/Makefile
+++ b/drivers/gpu/drm/msm/Makefile
@@ -56,6 +56,7 @@ msm-y := \
disp/dpu1/dpu_formats.o \
disp/dpu1/dpu_hw_catalog.o \
disp/dpu1/dpu_hw_ctl.o \
+ disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
disp/dpu1/dpu_hw_lm.o \
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 31af04afda7d..5fc0888351c7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -556,6 +556,16 @@ struct dpu_merge_3d_cfg {
const struct dpu_merge_3d_sub_blks *sblk;
};
+/**
+ * struct dpu_dsc_cfg - information of DSC blocks
+ * @id enum identifying this block
+ * @base register offset of this block
+ * @features bit mask identifying sub-blocks/features
+ */
+struct dpu_dsc_cfg {
+ DPU_HW_BLK_INFO;
+};
+
/**
* struct dpu_intf_cfg - information of timing engine blocks
* @id enum identifying this block
@@ -752,6 +762,9 @@ struct dpu_mdss_cfg {
u32 merge_3d_count;
const struct dpu_merge_3d_cfg *merge_3d;
+ u32 dsc_count;
+ struct dpu_dsc_cfg *dsc;
+
u32 intf_count;
const struct dpu_intf_cfg *intf;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
new file mode 100644
index 000000000000..449d6f1dad28
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
@@ -0,0 +1,210 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (c) 2020-2021, Linaro Limited
+ */
+
+#include "dpu_kms.h"
+#include "dpu_hw_catalog.h"
+#include "dpu_hwio.h"
+#include "dpu_hw_mdss.h"
+#include "dpu_hw_dsc.h"
+
+#define DSC_COMMON_MODE 0x000
+#define DSC_ENC 0X004
+#define DSC_PICTURE 0x008
+#define DSC_SLICE 0x00C
+#define DSC_CHUNK_SIZE 0x010
+#define DSC_DELAY 0x014
+#define DSC_SCALE_INITIAL 0x018
+#define DSC_SCALE_DEC_INTERVAL 0x01C
+#define DSC_SCALE_INC_INTERVAL 0x020
+#define DSC_FIRST_LINE_BPG_OFFSET 0x024
+#define DSC_BPG_OFFSET 0x028
+#define DSC_DSC_OFFSET 0x02C
+#define DSC_FLATNESS 0x030
+#define DSC_RC_MODEL_SIZE 0x034
+#define DSC_RC 0x038
+#define DSC_RC_BUF_THRESH 0x03C
+#define DSC_RANGE_MIN_QP 0x074
+#define DSC_RANGE_MAX_QP 0x0B0
+#define DSC_RANGE_BPG_OFFSET 0x0EC
+
+static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
+{
+ struct dpu_hw_blk_reg_map *c = &dsc->hw;
+
+ DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
+}
+
+static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc, u32 mode)
+{
+ struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
+ u32 data, lsb, bpp;
+ u32 initial_lines = dsc->initial_lines;
+ bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
+
+ DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
+
+ if (is_cmd_mode)
+ initial_lines += 1;
+
+ data = (initial_lines << 20);
+ data |= ((dsc->slice_last_group_size - 1) << 18);
+ /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
+ data |= dsc->drm->bits_per_pixel << 12;
+ lsb = dsc->drm->bits_per_pixel % 4;
+ bpp = dsc->drm->bits_per_pixel / 4;
+ bpp *= 4;
+ bpp <<= 4;
+ bpp |= lsb;
+
+ data |= bpp << 8;
+ data |= (dsc->drm->block_pred_enable << 7);
+ data |= (dsc->drm->line_buf_depth << 3);
+ data |= (dsc->drm->simple_422 << 2);
+ data |= (dsc->drm->convert_rgb << 1);
+ data |= dsc->drm->bits_per_component;
+
+ DPU_REG_WRITE(c, DSC_ENC, data);
+
+ data = dsc->drm->pic_width << 16;
+ data |= dsc->drm->pic_height;
+ DPU_REG_WRITE(c, DSC_PICTURE, data);
+
+ data = dsc->drm->slice_width << 16;
+ data |= dsc->drm->slice_height;
+ DPU_REG_WRITE(c, DSC_SLICE, data);
+
+ data = dsc->drm->slice_chunk_size << 16;
+ DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
+
+ data = dsc->drm->initial_dec_delay << 16;
+ data |= dsc->drm->initial_xmit_delay;
+ DPU_REG_WRITE(c, DSC_DELAY, data);
+
+ data = dsc->drm->initial_scale_value;
+ DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
+
+ data = dsc->drm->scale_decrement_interval;
+ DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
+
+ data = dsc->drm->scale_increment_interval;
+ DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
+
+ data = dsc->drm->first_line_bpg_offset;
+ DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
+
+ data = dsc->drm->nfl_bpg_offset << 16;
+ data |= dsc->drm->slice_bpg_offset;
+ DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
+
+ data = dsc->drm->initial_offset << 16;
+ data |= dsc->drm->final_offset;
+ DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
+
+ data = dsc->det_thresh_flatness << 10;
+ data |= dsc->drm->flatness_max_qp << 5;
+ data |= dsc->drm->flatness_min_qp;
+ DPU_REG_WRITE(c, DSC_FLATNESS, data);
+
+ data = dsc->drm->rc_model_size;
+ DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
+
+ data = dsc->drm->rc_tgt_offset_low << 18;
+ data |= dsc->drm->rc_tgt_offset_high << 14;
+ data |= dsc->drm->rc_quant_incr_limit1 << 9;
+ data |= dsc->drm->rc_quant_incr_limit0 << 4;
+ data |= dsc->drm->rc_edge_factor;
+ DPU_REG_WRITE(c, DSC_RC, data);
+}
+
+static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc)
+{
+ struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
+ struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
+ u32 off;
+ int i;
+
+ off = DSC_RC_BUF_THRESH;
+ for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
+ DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
+ off += 4;
+ }
+
+ off = DSC_RANGE_MIN_QP;
+ for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_min_qp);
+ off += 4;
+ }
+
+ off = DSC_RANGE_MAX_QP;
+ for (i = 0; i < 15; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_max_qp);
+ off += 4;
+ }
+
+ off = DSC_RANGE_BPG_OFFSET;
+ for (i = 0; i < 15; i++) {
+ DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
+ off += 4;
+ }
+}
+
+static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
+ struct dpu_mdss_cfg *m,
+ void __iomem *addr,
+ struct dpu_hw_blk_reg_map *b)
+{
+ int i;
+
+ for (i = 0; i < m->dsc_count; i++) {
+ if (dsc == m->dsc[i].id) {
+ b->base_off = addr;
+ b->blk_off = m->dsc[i].base;
+ b->length = m->dsc[i].len;
+ b->hwversion = m->hwversion;
+ b->log_mask = DPU_DBG_MASK_DSC;
+ return &m->dsc[i];
+ }
+ }
+
+ return NULL;
+}
+
+static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
+ unsigned long cap)
+{
+ ops->dsc_disable = dpu_hw_dsc_disable;
+ ops->dsc_config = dpu_hw_dsc_config;
+ ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
+};
+
+struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
+ struct dpu_mdss_cfg *m)
+{
+ struct dpu_hw_dsc *c;
+ struct dpu_dsc_cfg *cfg;
+
+ c = kzalloc(sizeof(*c), GFP_KERNEL);
+ if (!c)
+ return ERR_PTR(-ENOMEM);
+
+ cfg = _dsc_offset(idx, m, addr, &c->hw);
+ if (IS_ERR_OR_NULL(cfg)) {
+ kfree(c);
+ return ERR_PTR(-EINVAL);
+ }
+
+ c->idx = idx;
+ c->caps = cfg;
+ _setup_dsc_ops(&c->ops, c->caps->features);
+
+ return c;
+}
+
+void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
+{
+ kfree(dsc);
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
new file mode 100644
index 000000000000..648c9e4d8749
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* Copyright (c) 2020-2021, Linaro Limited */
+
+#ifndef _DPU_HW_DSC_H
+#define _DPU_HW_DSC_H
+
+#include <drm/drm_dsc.h>
+
+#define DSC_MODE_SPLIT_PANEL BIT(0)
+#define DSC_MODE_MULTIPLEX BIT(1)
+#define DSC_MODE_VIDEO BIT(2)
+
+struct dpu_hw_dsc;
+
+/**
+ * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
+ * Assumption is these functions will be called after clocks are enabled
+ */
+struct dpu_hw_dsc_ops {
+ /**
+ * dsc_disable - disable dsc
+ * @hw_dsc: Pointer to dsc context
+ */
+ void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
+
+ /**
+ * dsc_config - configures dsc encoder
+ * @hw_dsc: Pointer to dsc context
+ * @dsc: panel dsc parameters
+ * @mode: dsc topology mode to be set
+ */
+ void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc, u32 mode);
+
+ /**
+ * dsc_config_thresh - programs panel thresholds
+ * @hw_dsc: Pointer to dsc context
+ * @dsc: panel dsc parameters
+ */
+ void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
+ struct msm_display_dsc_config *dsc);
+};
+
+struct dpu_hw_dsc {
+ struct dpu_hw_blk base;
+ struct dpu_hw_blk_reg_map hw;
+
+ /* dsc */
+ enum dpu_dsc idx;
+ const struct dpu_dsc_cfg *caps;
+
+ /* ops */
+ struct dpu_hw_dsc_ops ops;
+};
+
+/**
+ * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
+ * @idx: DSC index for which driver object is required
+ * @addr: Mapped register io address of MDP
+ * @m: Pointer to mdss catalog data
+ * Returns: Error code or allocated dpu_hw_dsc context
+ */
+struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
+ struct dpu_mdss_cfg *m);
+
+/**
+ * dpu_hw_dsc_destroy - destroys dsc driver context
+ * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
+ */
+void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
+
+static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
+{
+ return container_of(hw, struct dpu_hw_dsc, base);
+}
+
+#endif /* _DPU_HW_DSC_H */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
index bb9ceadeb0bb..b0ce8cb97d22 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
@@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
DPU_HW_BLK_WB,
DPU_HW_BLK_DSPP,
DPU_HW_BLK_MERGE_3D,
+ DPU_HW_BLK_DSC,
DPU_HW_BLK_MAX,
};
@@ -176,6 +177,17 @@ enum dpu_ctl {
CTL_MAX
};
+enum dpu_dsc {
+ DSC_NONE = 0,
+ DSC_0,
+ DSC_1,
+ DSC_2,
+ DSC_3,
+ DSC_4,
+ DSC_5,
+ DSC_MAX
+};
+
enum dpu_pingpong {
PINGPONG_0 = 1,
PINGPONG_1,
@@ -437,5 +449,6 @@ struct dpu_mdss_color {
#define DPU_DBG_MASK_VBIF (1 << 8)
#define DPU_DBG_MASK_ROT (1 << 9)
#define DPU_DBG_MASK_DSPP (1 << 10)
+#define DPU_DBG_MASK_DSC (1 << 11)
#endif /* _DPU_HW_MDSS_H */
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 55766c97c4c8..47c6ab6caf95 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -28,6 +28,9 @@
#define PP_FBC_MODE 0x034
#define PP_FBC_BUDGET_CTL 0x038
#define PP_FBC_LOSSY_MODE 0x03C
+#define PP_DSC_MODE 0x0a0
+#define PP_DCE_DATA_IN_SWAP 0x0ac
+#define PP_DCE_DATA_OUT_SWAP 0x0c8
#define PP_DITHER_EN 0x000
#define PP_DITHER_BITDEPTH 0x004
@@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
return line;
}
+static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *c = &pp->hw;
+
+ DPU_REG_WRITE(c, PP_DSC_MODE, 1);
+ return 0;
+}
+
+static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *c = &pp->hw;
+
+ DPU_REG_WRITE(c, PP_DSC_MODE, 0);
+}
+
+static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *pp_c = &pp->hw;
+ int data;
+
+ data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);
+ data |= BIT(18); /* endian flip */
+ DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);
+ return 0;
+}
+
static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
unsigned long features)
{
@@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
c->ops.get_line_count = dpu_hw_pp_get_line_count;
+ c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
+ c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
+ c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
if (test_bit(DPU_PINGPONG_DITHER, &features))
c->ops.setup_dither = dpu_hw_pp_setup_dither;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 89d08a715c16..12758468d9ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops {
*/
void (*setup_dither)(struct dpu_hw_pingpong *pp,
struct dpu_hw_dither_cfg *cfg);
+ /**
+ * Enable DSC
+ */
+ int (*enable_dsc)(struct dpu_hw_pingpong *pp);
+
+ /**
+ * Disable DSC
+ */
+ void (*disable_dsc)(struct dpu_hw_pingpong *pp);
+
+ /**
+ * Setup DSC
+ */
+ int (*setup_dsc)(struct dpu_hw_pingpong *pp);
};
struct dpu_hw_merge_3d;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
In SDM845, DSC can be enabled by writing to pingpong block registers, so
add support for DSC in hw_pp
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++
.../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++
2 files changed, 46 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
index 55766c97c4c8..47c6ab6caf95 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
@@ -28,6 +28,9 @@
#define PP_FBC_MODE 0x034
#define PP_FBC_BUDGET_CTL 0x038
#define PP_FBC_LOSSY_MODE 0x03C
+#define PP_DSC_MODE 0x0a0
+#define PP_DCE_DATA_IN_SWAP 0x0ac
+#define PP_DCE_DATA_OUT_SWAP 0x0c8
#define PP_DITHER_EN 0x000
#define PP_DITHER_BITDEPTH 0x004
@@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
return line;
}
+static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *c = &pp->hw;
+
+ DPU_REG_WRITE(c, PP_DSC_MODE, 1);
+ return 0;
+}
+
+static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *c = &pp->hw;
+
+ DPU_REG_WRITE(c, PP_DSC_MODE, 0);
+}
+
+static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
+{
+ struct dpu_hw_blk_reg_map *pp_c = &pp->hw;
+ int data;
+
+ data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);
+ data |= BIT(18); /* endian flip */
+ DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);
+ return 0;
+}
+
static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
unsigned long features)
{
@@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
c->ops.get_line_count = dpu_hw_pp_get_line_count;
+ c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
+ c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
+ c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
if (test_bit(DPU_PINGPONG_DITHER, &features))
c->ops.setup_dither = dpu_hw_pp_setup_dither;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
index 89d08a715c16..12758468d9ca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
@@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops {
*/
void (*setup_dither)(struct dpu_hw_pingpong *pp,
struct dpu_hw_dither_cfg *cfg);
+ /**
+ * Enable DSC
+ */
+ int (*enable_dsc)(struct dpu_hw_pingpong *pp);
+
+ /**
+ * Disable DSC
+ */
+ void (*disable_dsc)(struct dpu_hw_pingpong *pp);
+
+ /**
+ * Setup DSC
+ */
+ int (*setup_dsc)(struct dpu_hw_pingpong *pp);
};
struct dpu_hw_merge_3d;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991903a6..9c09cf318dfb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -821,6 +821,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
};
+
+/*************************************************************
+ * DSC sub blocks config
+ *************************************************************/
+#define DSC_BLK(_name, _id, _base) \
+ {\
+ .name = _name, .id = _id, \
+ .base = _base, .len = 0x140, \
+ .features = 0, \
+ }
+
+static struct dpu_dsc_cfg sdm845_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000),
+ DSC_BLK("dsc_1", DSC_1, 0x80400),
+ DSC_BLK("dsc_2", DSC_2, 0x80800),
+ DSC_BLK("dsc_3", DSC_3, 0x80c00),
+};
+
/*************************************************************
* INTF sub blocks config
*************************************************************/
@@ -1124,6 +1142,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.mixer = sdm845_lm,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
+ .dsc_count = ARRAY_SIZE(sdm845_dsc),
+ .dsc = sdm845_dsc,
.intf_count = ARRAY_SIZE(sdm845_intf),
.intf = sdm845_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
This adds SDM845 DSC blocks into hw_catalog
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
.../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index aa75991903a6..9c09cf318dfb 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -821,6 +821,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
};
+
+/*************************************************************
+ * DSC sub blocks config
+ *************************************************************/
+#define DSC_BLK(_name, _id, _base) \
+ {\
+ .name = _name, .id = _id, \
+ .base = _base, .len = 0x140, \
+ .features = 0, \
+ }
+
+static struct dpu_dsc_cfg sdm845_dsc[] = {
+ DSC_BLK("dsc_0", DSC_0, 0x80000),
+ DSC_BLK("dsc_1", DSC_1, 0x80400),
+ DSC_BLK("dsc_2", DSC_2, 0x80800),
+ DSC_BLK("dsc_3", DSC_3, 0x80c00),
+};
+
/*************************************************************
* INTF sub blocks config
*************************************************************/
@@ -1124,6 +1142,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.mixer = sdm845_lm,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
+ .dsc_count = ARRAY_SIZE(sdm845_dsc),
+ .dsc = sdm845_dsc,
.intf_count = ARRAY_SIZE(sdm845_intf),
.intf = sdm845_intf,
.vbif_count = ARRAY_SIZE(sdm845_vbif),
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 02da9ecf71f1..49659165cea8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
#define CTL_MERGE_3D_ACTIVE 0x0E4
#define CTL_INTF_ACTIVE 0x0F4
#define CTL_MERGE_3D_FLUSH 0x100
+#define CTL_DSC_ACTIVE 0x0E8
+#define CTL_DSC_FLUSH 0x104
#define CTL_INTF_FLUSH 0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000
#define MERGE_3D_IDX 23
+#define DSC_IDX 22
#define INTF_IDX 31
#define CTL_INVALID_BIT 0xffff
#define CTL_DEFAULT_GROUP_ID 0xf
@@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
{
-
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
ctx->pending_merge_3d_flush_mask);
@@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
mode_sel = CTL_DEFAULT_GROUP_ID << 28;
+ if (cfg->dsc)
+ DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
+
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
mode_sel |= BIT(17);
@@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
+ if (cfg->dsc) {
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
+ }
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 806c171e5df2..9847c9c46d6f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
* @merge_3d: 3d merge block used
* @intf_mode_sel: Interface mode, cmd / vid
* @stream_sel: Stream selection for multi-stream interfaces
+ * @dsc: DSC BIT masks
*/
struct dpu_hw_intf_cfg {
enum dpu_intf intf;
@@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
enum dpu_merge_3d merge_3d;
enum dpu_ctl_mode_sel intf_mode_sel;
int stream_sel;
+ unsigned int dsc;
};
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Later gens of hardware have DSC bits moved to hw_ctl, so configure these
bits so that DSC would work there as well
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 02da9ecf71f1..49659165cea8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -25,6 +25,8 @@
#define CTL_MERGE_3D_ACTIVE 0x0E4
#define CTL_INTF_ACTIVE 0x0F4
#define CTL_MERGE_3D_FLUSH 0x100
+#define CTL_DSC_ACTIVE 0x0E8
+#define CTL_DSC_FLUSH 0x104
#define CTL_INTF_FLUSH 0x110
#define CTL_INTF_MASTER 0x134
#define CTL_FETCH_PIPE_ACTIVE 0x0FC
@@ -34,6 +36,7 @@
#define DPU_REG_RESET_TIMEOUT_US 2000
#define MERGE_3D_IDX 23
+#define DSC_IDX 22
#define INTF_IDX 31
#define CTL_INVALID_BIT 0xffff
#define CTL_DEFAULT_GROUP_ID 0xf
@@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
{
-
if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
ctx->pending_merge_3d_flush_mask);
@@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
mode_sel = CTL_DEFAULT_GROUP_ID << 28;
+ if (cfg->dsc)
+ DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
+
if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
mode_sel |= BIT(17);
@@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
if (cfg->merge_3d)
DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
BIT(cfg->merge_3d - MERGE_3D_0));
+ if (cfg->dsc) {
+ DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
+ DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
+ }
}
static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
index 806c171e5df2..9847c9c46d6f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
@@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
* @merge_3d: 3d merge block used
* @intf_mode_sel: Interface mode, cmd / vid
* @stream_sel: Stream selection for multi-stream interfaces
+ * @dsc: DSC BIT masks
*/
struct dpu_hw_intf_cfg {
enum dpu_intf intf;
@@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
enum dpu_merge_3d merge_3d;
enum dpu_ctl_mode_sel intf_mode_sel;
int stream_sel;
+ unsigned int dsc;
};
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
2 files changed, 171 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1e648db439f9..95a7bf362e81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -21,6 +21,7 @@
#include "dpu_hw_intf.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_dspp.h"
+#include "dpu_hw_dsc.h"
#include "dpu_formats.h"
#include "dpu_encoder_phys.h"
#include "dpu_crtc.h"
@@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
* @cur_slave: As above but for the slave encoder.
* @hw_pp: Handle to the pingpong blocks used for the display. No.
* pingpong blocks can be different than num_phys_encs.
+ * @hw_dsc: Handle to the DSC blocks used for the display.
+ * @dsc_mask: The bitmask of used DSC blocks.
* @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
* for partial update right-only cases, such as pingpong
* split where virtual pingpong does not generate IRQs
@@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
* @dp: msm_dp pointer, for DP encoders
+ * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
*/
struct dpu_encoder_virt {
struct drm_encoder base;
@@ -182,6 +186,9 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *cur_master;
struct dpu_encoder_phys *cur_slave;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+ struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+
+ unsigned int dsc_mask;
bool intfs_swapped;
@@ -209,6 +216,9 @@ struct dpu_encoder_virt {
u32 idle_timeout;
struct msm_dp *dp;
+
+ /* DSC configuration */
+ struct msm_display_dsc_config *dsc;
};
#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
@@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
- int num_lm, num_ctl, num_pp;
+ struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
+ int num_lm, num_ctl, num_pp, num_dsc;
int i, j;
if (!drm_enc) {
@@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
: NULL;
+ dpu_enc->dsc_mask = 0;
+
+ if (dpu_enc->dsc) {
+ unsigned int dsc_mask = 0;
+
+ num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
+ drm_enc->base.id, DPU_HW_BLK_DSC,
+ hw_dsc, ARRAY_SIZE(hw_dsc));
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+ dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
+
+ for (i = 0; i < num_dsc; i++)
+ dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
+
+ dpu_enc->dsc_mask = dsc_mask;
+ }
+
cstate = to_dpu_crtc_state(drm_crtc->state);
for (i = 0; i < num_lm; i++) {
@@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
}
+static void
+dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
+{
+ int slice_count, slice_per_intf;
+ int bytes_in_slice, total_bytes_per_intf;
+
+ if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
+ DPU_ERROR("Invalid DSC/slices\n");
+ return;
+ }
+
+ slice_count = dsc->drm->slice_count;
+ slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
+
+ /*
+ * If slice_count is greater than slice_per_intf then default to 1.
+ * This can happen during partial update.
+ */
+ if (slice_count > slice_per_intf)
+ slice_count = 1;
+
+ bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
+ dsc->drm->bits_per_pixel, 8);
+ total_bytes_per_intf = bytes_in_slice * slice_per_intf;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
+ dsc->bytes_in_slice = bytes_in_slice;
+ dsc->bytes_per_pkt = bytes_in_slice * slice_count;
+ dsc->pkt_per_line = slice_per_intf / slice_count;
+}
+
+static void
+dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
+ u32 enc_ip_width)
+{
+ int ssm_delay, total_pixels, soft_slice_per_enc;
+
+ soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
+
+ /*
+ * minimum number of initial line pixels is a sum of:
+ * 1. sub-stream multiplexer delay (83 groups for 8bpc,
+ * 91 for 10 bpc) * 3
+ * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
+ * 3. the initial xmit delay
+ * 4. total pipeline delay through the "lock step" of encoder (47)
+ * 5. 6 additional pixels as the output of the rate buffer is
+ * 48 bits wide
+ */
+ ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
+ total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
+ if (soft_slice_per_enc > 1)
+ total_pixels += (ssm_delay * 3);
+ dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
+}
+
+static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
+ struct dpu_hw_pingpong *hw_pp,
+ struct msm_display_dsc_config *dsc,
+ u32 common_mode)
+{
+ if (hw_dsc->ops.dsc_config)
+ hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
+
+ if (hw_dsc->ops.dsc_config_thresh)
+ hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
+
+ if (hw_pp->ops.setup_dsc)
+ hw_pp->ops.setup_dsc(hw_pp);
+
+ if (hw_pp->ops.enable_dsc)
+ hw_pp->ops.enable_dsc(hw_pp);
+}
+
+static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
+ struct msm_display_dsc_config *dsc)
+{
+ /* coding only for 2LM, 2enc, 1 dsc config */
+ struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
+ struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+ struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+ int this_frame_slices;
+ int intf_ip_w, enc_ip_w;
+ int dsc_common_mode;
+ int pic_width;
+ int i;
+
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ hw_pp[i] = dpu_enc->hw_pp[i];
+ hw_dsc[i] = dpu_enc->hw_dsc[i];
+
+ if (!hw_pp[i] || !hw_dsc[i]) {
+ DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
+ return;
+ }
+ }
+
+ dsc_common_mode = 0;
+ pic_width = dsc->drm->pic_width;
+
+ dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
+ if (enc_master->intf_mode == INTF_MODE_VIDEO)
+ dsc_common_mode |= DSC_MODE_VIDEO;
+
+ this_frame_slices = pic_width / dsc->drm->slice_width;
+ intf_ip_w = this_frame_slices * dsc->drm->slice_width;
+
+ dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
+
+ /*
+ * dsc merge case: when using 2 encoders for the same stream,
+ * no. of slices need to be same on both the encoders.
+ */
+ enc_ip_w = intf_ip_w / 2;
+ dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
+
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+ dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
+}
+
void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc;
@@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
}
}
+
+ if (dpu_enc->dsc)
+ dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
}
void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
@@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
+ dpu_enc->dsc = disp_info->dsc;
+
mutex_lock(&dpu_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
@@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
return INTF_MODE_NONE;
}
+
+unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
+{
+ struct drm_encoder *encoder = phys_enc->parent;
+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
+
+ return dpu_enc->dsc_mask;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index e7270eb6b84b..7b90d644a41b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
return BLEND_3D_NONE;
}
+/**
+ * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
+ * This helper function is used by physical encoder to get DSC blocks mask
+ * used for this encoder.
+ * @phys_enc: Pointer to physical encoder structure
+ */
+unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+
/**
* dpu_encoder_helper_split_config - split display configuration helper function
* This helper function may be used by physical encoders to configure
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
We need to configure the encoder for DSC configuration and calculate DSC
parameters for the given timing so this patch adds that support by
adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
.../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
2 files changed, 171 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 1e648db439f9..95a7bf362e81 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -21,6 +21,7 @@
#include "dpu_hw_intf.h"
#include "dpu_hw_ctl.h"
#include "dpu_hw_dspp.h"
+#include "dpu_hw_dsc.h"
#include "dpu_formats.h"
#include "dpu_encoder_phys.h"
#include "dpu_crtc.h"
@@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
* @cur_slave: As above but for the slave encoder.
* @hw_pp: Handle to the pingpong blocks used for the display. No.
* pingpong blocks can be different than num_phys_encs.
+ * @hw_dsc: Handle to the DSC blocks used for the display.
+ * @dsc_mask: The bitmask of used DSC blocks.
* @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
* for partial update right-only cases, such as pingpong
* split where virtual pingpong does not generate IRQs
@@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
* @topology: topology of the display
* @idle_timeout: idle timeout duration in milliseconds
* @dp: msm_dp pointer, for DP encoders
+ * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
*/
struct dpu_encoder_virt {
struct drm_encoder base;
@@ -182,6 +186,9 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *cur_master;
struct dpu_encoder_phys *cur_slave;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+ struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+
+ unsigned int dsc_mask;
bool intfs_swapped;
@@ -209,6 +216,9 @@ struct dpu_encoder_virt {
u32 idle_timeout;
struct msm_dp *dp;
+
+ /* DSC configuration */
+ struct msm_display_dsc_config *dsc;
};
#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
@@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
- int num_lm, num_ctl, num_pp;
+ struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
+ int num_lm, num_ctl, num_pp, num_dsc;
int i, j;
if (!drm_enc) {
@@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
: NULL;
+ dpu_enc->dsc_mask = 0;
+
+ if (dpu_enc->dsc) {
+ unsigned int dsc_mask = 0;
+
+ num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
+ drm_enc->base.id, DPU_HW_BLK_DSC,
+ hw_dsc, ARRAY_SIZE(hw_dsc));
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+ dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
+
+ for (i = 0; i < num_dsc; i++)
+ dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
+
+ dpu_enc->dsc_mask = dsc_mask;
+ }
+
cstate = to_dpu_crtc_state(drm_crtc->state);
for (i = 0; i < num_lm; i++) {
@@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
}
+static void
+dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
+{
+ int slice_count, slice_per_intf;
+ int bytes_in_slice, total_bytes_per_intf;
+
+ if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
+ DPU_ERROR("Invalid DSC/slices\n");
+ return;
+ }
+
+ slice_count = dsc->drm->slice_count;
+ slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
+
+ /*
+ * If slice_count is greater than slice_per_intf then default to 1.
+ * This can happen during partial update.
+ */
+ if (slice_count > slice_per_intf)
+ slice_count = 1;
+
+ bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
+ dsc->drm->bits_per_pixel, 8);
+ total_bytes_per_intf = bytes_in_slice * slice_per_intf;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
+ dsc->bytes_in_slice = bytes_in_slice;
+ dsc->bytes_per_pkt = bytes_in_slice * slice_count;
+ dsc->pkt_per_line = slice_per_intf / slice_count;
+}
+
+static void
+dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
+ u32 enc_ip_width)
+{
+ int ssm_delay, total_pixels, soft_slice_per_enc;
+
+ soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
+
+ /*
+ * minimum number of initial line pixels is a sum of:
+ * 1. sub-stream multiplexer delay (83 groups for 8bpc,
+ * 91 for 10 bpc) * 3
+ * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
+ * 3. the initial xmit delay
+ * 4. total pipeline delay through the "lock step" of encoder (47)
+ * 5. 6 additional pixels as the output of the rate buffer is
+ * 48 bits wide
+ */
+ ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
+ total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
+ if (soft_slice_per_enc > 1)
+ total_pixels += (ssm_delay * 3);
+ dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
+}
+
+static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
+ struct dpu_hw_pingpong *hw_pp,
+ struct msm_display_dsc_config *dsc,
+ u32 common_mode)
+{
+ if (hw_dsc->ops.dsc_config)
+ hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
+
+ if (hw_dsc->ops.dsc_config_thresh)
+ hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
+
+ if (hw_pp->ops.setup_dsc)
+ hw_pp->ops.setup_dsc(hw_pp);
+
+ if (hw_pp->ops.enable_dsc)
+ hw_pp->ops.enable_dsc(hw_pp);
+}
+
+static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
+ struct msm_display_dsc_config *dsc)
+{
+ /* coding only for 2LM, 2enc, 1 dsc config */
+ struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
+ struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
+ struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
+ int this_frame_slices;
+ int intf_ip_w, enc_ip_w;
+ int dsc_common_mode;
+ int pic_width;
+ int i;
+
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
+ hw_pp[i] = dpu_enc->hw_pp[i];
+ hw_dsc[i] = dpu_enc->hw_dsc[i];
+
+ if (!hw_pp[i] || !hw_dsc[i]) {
+ DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
+ return;
+ }
+ }
+
+ dsc_common_mode = 0;
+ pic_width = dsc->drm->pic_width;
+
+ dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
+ if (enc_master->intf_mode == INTF_MODE_VIDEO)
+ dsc_common_mode |= DSC_MODE_VIDEO;
+
+ this_frame_slices = pic_width / dsc->drm->slice_width;
+ intf_ip_w = this_frame_slices * dsc->drm->slice_width;
+
+ dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
+
+ /*
+ * dsc merge case: when using 2 encoders for the same stream,
+ * no. of slices need to be same on both the encoders.
+ */
+ enc_ip_w = intf_ip_w / 2;
+ dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
+
+ for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
+ dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
+}
+
void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc;
@@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
}
}
+
+ if (dpu_enc->dsc)
+ dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
}
void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
@@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
dpu_enc->idle_pc_supported =
dpu_kms->catalog->caps->has_idle_pc;
+ dpu_enc->dsc = disp_info->dsc;
+
mutex_lock(&dpu_enc->enc_lock);
for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
/*
@@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
return INTF_MODE_NONE;
}
+
+unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
+{
+ struct drm_encoder *encoder = phys_enc->parent;
+ struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
+
+ return dpu_enc->dsc_mask;
+}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index e7270eb6b84b..7b90d644a41b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
return BLEND_3D_NONE;
}
+/**
+ * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
+ * This helper function is used by physical encoder to get DSC blocks mask
+ * used for this encoder.
+ * @phys_enc: Pointer to physical encoder structure
+ */
+unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
+
/**
* dpu_encoder_helper_split_config - split display configuration helper function
* This helper function may be used by physical encoders to configure
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 34a6940d12c5..ed37a4c21596 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
intf_cfg.stream_sel = cmd_enc->stream_sel;
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+ intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
+ if (intf_cfg.dsc)
+ intf_cfg.mode_3d = 0;
+
ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89cd456..218009855fca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+ intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
+ if (intf_cfg.dsc)
+ intf_cfg.mode_3d = 0;
+
if (phys_enc->hw_pp->merge_3d)
intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 49659165cea8..6d5268b7da90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
intf_cfg |= (cfg->intf & 0xF) << 4;
- if (cfg->mode_3d) {
+ /* In DSC we can't set merge, so check for dsc and complain */
+ if (cfg->mode_3d && cfg->dsc)
+ pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
+
+ /* set merge only when dsc is not set */
+ if (cfg->mode_3d && !cfg->dsc) {
intf_cfg |= BIT(19);
intf_cfg |= (cfg->mode_3d - 0x1) << 20;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
We cannot enable mode_3d when we are using the DSC. So pass
configuration to detect DSC is enabled and not enable mode_3d
when we are using DSC
We add a helper dpu_encoder_helper_get_dsc() to detect dsc
enabled and pass this to .setup_intf_cfg()
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 34a6940d12c5..ed37a4c21596 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
intf_cfg.stream_sel = cmd_enc->stream_sel;
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+ intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
+ if (intf_cfg.dsc)
+ intf_cfg.mode_3d = 0;
+
ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
}
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index ddd9d89cd456..218009855fca 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
intf_cfg.stream_sel = 0; /* Don't care value for video mode */
intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
+ intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
+ if (intf_cfg.dsc)
+ intf_cfg.mode_3d = 0;
+
if (phys_enc->hw_pp->merge_3d)
intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
index 49659165cea8..6d5268b7da90 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
@@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
intf_cfg |= (cfg->intf & 0xF) << 4;
- if (cfg->mode_3d) {
+ /* In DSC we can't set merge, so check for dsc and complain */
+ if (cfg->mode_3d && cfg->dsc)
+ pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
+
+ /* set merge only when dsc is not set */
+ if (cfg->mode_3d && !cfg->dsc) {
intf_cfg |= BIT(19);
intf_cfg |= (cfg->mode_3d - 0x1) << 20;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Somehow documentation for dspp was missed, so add that
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index e7a312edfe67..6425a42e997c 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -102,6 +102,7 @@ enum msm_event_wait {
* @num_lm: number of layer mixers used
* @num_enc: number of compression encoder blocks used
* @num_intf: number of interfaces the panel is mounted on
+ * @num_dspp: number of dspp blocks used
*/
struct msm_display_topology {
u32 num_lm;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Somehow documentation for dspp was missed, so add that
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/msm_drv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index e7a312edfe67..6425a42e997c 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -102,6 +102,7 @@ enum msm_event_wait {
* @num_lm: number of layer mixers used
* @num_enc: number of compression encoder blocks used
* @num_intf: number of interfaces the panel is mounted on
+ * @num_dspp: number of dspp blocks used
*/
struct msm_display_topology {
u32 num_lm;
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
The panel has been tested only with 2,2,1 configuration, so for
now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 95a7bf362e81..13ccb7b3cce5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
topology.num_enc = 0;
topology.num_intf = intf_count;
+ if (dpu_enc->dsc) {
+ /* In case of Display Stream Compression DSC, we would use
+ * 2 encoders, 2 line mixers and 1 interface
+ * this is power optimal and can drive up to (including) 4k
+ * screens
+ */
+ topology.num_enc = 2;
+ topology.num_dsc = 2;
+ topology.num_intf = 1;
+ topology.num_lm = 2;
+ }
+
return topology;
}
+
static int dpu_encoder_virt_atomic_check(
struct drm_encoder *drm_enc,
struct drm_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 6425a42e997c..994d895d1a47 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -103,12 +103,14 @@ enum msm_event_wait {
* @num_enc: number of compression encoder blocks used
* @num_intf: number of interfaces the panel is mounted on
* @num_dspp: number of dspp blocks used
+ * @num_dsc: number of Display Stream Compression (DSC) blocks used
*/
struct msm_display_topology {
u32 num_lm;
u32 num_enc;
u32 num_intf;
u32 num_dspp;
+ u32 num_dsc;
};
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
For DSC to work we typically need a 2,2,1 configuration. This should
suffice for resolutions up to 4k. For more resolutions like 8k this won't
work.
Also, it is better to use 2 LMs and DSC instances as half width results
in lesser power consumption as compared to single LM, DSC at full width.
The panel has been tested only with 2,2,1 configuration, so for
now we blindly create 2,2,1 topology when DSC is enabled
Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
drivers/gpu/drm/msm/msm_drv.h | 2 ++
2 files changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 95a7bf362e81..13ccb7b3cce5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
topology.num_enc = 0;
topology.num_intf = intf_count;
+ if (dpu_enc->dsc) {
+ /* In case of Display Stream Compression DSC, we would use
+ * 2 encoders, 2 line mixers and 1 interface
+ * this is power optimal and can drive up to (including) 4k
+ * screens
+ */
+ topology.num_enc = 2;
+ topology.num_dsc = 2;
+ topology.num_intf = 1;
+ topology.num_lm = 2;
+ }
+
return topology;
}
+
static int dpu_encoder_virt_atomic_check(
struct drm_encoder *drm_enc,
struct drm_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 6425a42e997c..994d895d1a47 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -103,12 +103,14 @@ enum msm_event_wait {
* @num_enc: number of compression encoder blocks used
* @num_intf: number of interfaces the panel is mounted on
* @num_dspp: number of dspp blocks used
+ * @num_dsc: number of Display Stream Compression (DSC) blocks used
*/
struct msm_display_topology {
u32 num_lm;
u32 num_enc;
u32 num_intf;
u32 num_dspp;
+ u32 num_dsc;
};
/**
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 2d385b4b7f5e..8f2fb667b05c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -146,6 +146,7 @@ struct dpu_global_state {
uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
+ uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
};
struct dpu_global_state
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f9c83d6e427a..fbb24bb2b998 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -11,6 +11,7 @@
#include "dpu_hw_intf.h"
#include "dpu_hw_dspp.h"
#include "dpu_hw_merge3d.h"
+#include "dpu_hw_dsc.h"
#include "dpu_encoder.h"
#include "dpu_trace.h"
@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
dpu_hw_intf_destroy(hw);
}
}
+ for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
+ struct dpu_hw_dsc *hw;
+
+ if (rm->dsc_blks[i]) {
+ hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
+ dpu_hw_dsc_destroy(hw);
+ }
+ }
return 0;
}
@@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
}
+ for (i = 0; i < cat->dsc_count; i++) {
+ struct dpu_hw_dsc *hw;
+ const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
+
+ hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
+ if (IS_ERR_OR_NULL(hw)) {
+ rc = PTR_ERR(hw);
+ DPU_ERROR("failed dsc object creation: err %d\n", rc);
+ goto fail;
+ }
+ rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
+ }
+
return 0;
fail:
@@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
}
global_state->intf_to_enc_id[idx] = enc_id;
+
return 0;
}
@@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
return ret;
}
+static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
+ struct dpu_global_state *global_state,
+ struct drm_encoder *enc,
+ const struct msm_display_topology *top)
+{
+ int num_dsc = top->num_dsc;
+ int i;
+
+ /* check if DSC required are allocated or not */
+ for (i = 0; i < num_dsc; i++) {
+ if (global_state->dsc_to_enc_id[i]) {
+ DPU_ERROR("DSC %d is already allocated\n", i);
+ return -EIO;
+ }
+ }
+
+ for (i = 0; i < num_dsc; i++)
+ global_state->dsc_to_enc_id[i] = enc->base.id;
+
+ return 0;
+}
+
static int _dpu_rm_make_reservation(
struct dpu_rm *rm,
struct dpu_global_state *global_state,
@@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
if (ret)
return ret;
+ ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
+ if (ret)
+ return ret;
+
return ret;
}
@@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
_dpu_rm_clear_mapping(global_state->intf_to_enc_id,
ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
+ _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
+ ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
}
int dpu_rm_reserve(
@@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
hw_to_enc_id = global_state->dspp_to_enc_id;
max_blks = ARRAY_SIZE(rm->dspp_blks);
break;
+ case DPU_HW_BLK_DSC:
+ hw_blks = rm->dsc_blks;
+ hw_to_enc_id = global_state->dsc_to_enc_id;
+ max_blks = ARRAY_SIZE(rm->dsc_blks);
+ break;
default:
DPU_ERROR("blk type %d not managed by rm\n", type);
return 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 1f12c8d5b8aa..278d2a510b80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -30,6 +30,7 @@ struct dpu_rm {
struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
+ struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
uint32_t lm_max_width;
};
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
This add the bits in RM to enable the DSC blocks
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
3 files changed, 58 insertions(+)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
index 2d385b4b7f5e..8f2fb667b05c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
@@ -146,6 +146,7 @@ struct dpu_global_state {
uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
+ uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
};
struct dpu_global_state
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index f9c83d6e427a..fbb24bb2b998 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -11,6 +11,7 @@
#include "dpu_hw_intf.h"
#include "dpu_hw_dspp.h"
#include "dpu_hw_merge3d.h"
+#include "dpu_hw_dsc.h"
#include "dpu_encoder.h"
#include "dpu_trace.h"
@@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
dpu_hw_intf_destroy(hw);
}
}
+ for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
+ struct dpu_hw_dsc *hw;
+
+ if (rm->dsc_blks[i]) {
+ hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
+ dpu_hw_dsc_destroy(hw);
+ }
+ }
return 0;
}
@@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
}
+ for (i = 0; i < cat->dsc_count; i++) {
+ struct dpu_hw_dsc *hw;
+ const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
+
+ hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
+ if (IS_ERR_OR_NULL(hw)) {
+ rc = PTR_ERR(hw);
+ DPU_ERROR("failed dsc object creation: err %d\n", rc);
+ goto fail;
+ }
+ rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
+ }
+
return 0;
fail:
@@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
}
global_state->intf_to_enc_id[idx] = enc_id;
+
return 0;
}
@@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
return ret;
}
+static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
+ struct dpu_global_state *global_state,
+ struct drm_encoder *enc,
+ const struct msm_display_topology *top)
+{
+ int num_dsc = top->num_dsc;
+ int i;
+
+ /* check if DSC required are allocated or not */
+ for (i = 0; i < num_dsc; i++) {
+ if (global_state->dsc_to_enc_id[i]) {
+ DPU_ERROR("DSC %d is already allocated\n", i);
+ return -EIO;
+ }
+ }
+
+ for (i = 0; i < num_dsc; i++)
+ global_state->dsc_to_enc_id[i] = enc->base.id;
+
+ return 0;
+}
+
static int _dpu_rm_make_reservation(
struct dpu_rm *rm,
struct dpu_global_state *global_state,
@@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
if (ret)
return ret;
+ ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
+ if (ret)
+ return ret;
+
return ret;
}
@@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
_dpu_rm_clear_mapping(global_state->intf_to_enc_id,
ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
+ _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
+ ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
}
int dpu_rm_reserve(
@@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
hw_to_enc_id = global_state->dspp_to_enc_id;
max_blks = ARRAY_SIZE(rm->dspp_blks);
break;
+ case DPU_HW_BLK_DSC:
+ hw_blks = rm->dsc_blks;
+ hw_to_enc_id = global_state->dsc_to_enc_id;
+ max_blks = ARRAY_SIZE(rm->dsc_blks);
+ break;
default:
DPU_ERROR("blk type %d not managed by rm\n", type);
return 0;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 1f12c8d5b8aa..278d2a510b80 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -30,6 +30,7 @@ struct dpu_rm {
struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
+ struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
uint32_t lm_max_width;
};
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
drivers/gpu/drm/msm/dsi/dsi_host.c | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ++++++++++++
3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 16cd9b2fce86..580a1e6358bf 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -114,6 +114,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
const struct drm_display_mode *mode);
+enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
+ const struct drm_display_mode *mode);
struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host);
unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host);
struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 7e9913eff724..438c80750682 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2552,6 +2552,32 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
return 0;
}
+enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
+ const struct drm_display_mode *mode)
+{
+ struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ int pic_width = mode->hdisplay;
+ int pic_height = mode->vdisplay;
+
+ if (!msm_host->dsc)
+ return MODE_OK;
+
+ if (pic_width % dsc->drm->slice_width) {
+ pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
+ pic_width, dsc->drm->slice_width);
+ return MODE_H_ILLEGAL;
+ }
+
+ if (pic_height % dsc->drm->slice_height) {
+ pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
+ pic_height, dsc->drm->slice_height);
+ return MODE_V_ILLEGAL;
+ }
+
+ return MODE_OK;
+}
+
struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
{
return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index f19bae475c96..e7f6cc88f7a4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -575,6 +575,17 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
}
+static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ int id = dsi_mgr_bridge_get_id(bridge);
+ struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+ struct mipi_dsi_host *host = msm_dsi->host;
+
+ return msm_dsi_host_check_dsc(host, mode);
+}
+
static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
.detect = dsi_mgr_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -596,6 +607,7 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
.disable = dsi_mgr_bridge_disable,
.post_disable = dsi_mgr_bridge_post_disable,
.mode_set = dsi_mgr_bridge_mode_set,
+ .mode_valid = dsi_mgr_bridge_mode_valid,
};
/* initialize connector when we're connected to a drm_panel */
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
Add a mode valid callback for dsi_mgr for checking mode being valid in
case of DSC. For DSC the height and width needs to be multiple of slice,
so we check that here
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
drivers/gpu/drm/msm/dsi/dsi_host.c | 26 ++++++++++++++++++++++++++
drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ++++++++++++
3 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
index 16cd9b2fce86..580a1e6358bf 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.h
@@ -114,6 +114,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
int msm_dsi_host_power_off(struct mipi_dsi_host *host);
int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
const struct drm_display_mode *mode);
+enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
+ const struct drm_display_mode *mode);
struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host);
unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host);
struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 7e9913eff724..438c80750682 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -2552,6 +2552,32 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
return 0;
}
+enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
+ const struct drm_display_mode *mode)
+{
+ struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ int pic_width = mode->hdisplay;
+ int pic_height = mode->vdisplay;
+
+ if (!msm_host->dsc)
+ return MODE_OK;
+
+ if (pic_width % dsc->drm->slice_width) {
+ pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
+ pic_width, dsc->drm->slice_width);
+ return MODE_H_ILLEGAL;
+ }
+
+ if (pic_height % dsc->drm->slice_height) {
+ pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
+ pic_height, dsc->drm->slice_height);
+ return MODE_V_ILLEGAL;
+ }
+
+ return MODE_OK;
+}
+
struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
{
return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
index f19bae475c96..e7f6cc88f7a4 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
@@ -575,6 +575,17 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
}
+static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
+ const struct drm_display_info *info,
+ const struct drm_display_mode *mode)
+{
+ int id = dsi_mgr_bridge_get_id(bridge);
+ struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
+ struct mipi_dsi_host *host = msm_dsi->host;
+
+ return msm_dsi_host_check_dsc(host, mode);
+}
+
static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
.detect = dsi_mgr_connector_detect,
.fill_modes = drm_helper_probe_single_connector_modes,
@@ -596,6 +607,7 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
.disable = dsi_mgr_bridge_disable,
.post_disable = dsi_mgr_bridge_post_disable,
.mode_set = dsi_mgr_bridge_mode_set,
+ .mode_valid = dsi_mgr_bridge_mode_valid,
};
/* initialize connector when we're connected to a drm_panel */
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:34 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 49b551ad1bff..c1c85df58c4b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
+
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
+
#endif /* DSI_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 438c80750682..3d8d5a1daaa3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
}
+static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
+ int pic_width, int pic_height)
+{
+ if (!dsc || !pic_width || !pic_height) {
+ pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
+ return -EINVAL;
+ }
+
+ dsc->drm->pic_width = pic_width;
+ dsc->drm->pic_height = pic_height;
+
+ return 0;
+}
+
static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
@@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
hdisplay /= 2;
}
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+
+ /* update dsc params with timing params */
+ dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
+ DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
+
+ /* we do the calculations for dsc parameters here so that
+ * panel can use these parameters
+ */
+ dsi_populate_dsc_params(dsc);
+
+ /* Divide the display by 3 but keep back/font porch and
+ * pulse width same
+ */
+ h_total -= hdisplay;
+ hdisplay /= 3;
+ h_total += hdisplay;
+ ha_end = ha_start + hdisplay;
+ }
+
if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ u32 reg, intf_width, slice_per_intf;
+ u32 total_bytes_per_intf;
+
+ /* first calculate dsc parameters and then program
+ * compress mode registers
+ */
+ intf_width = hdisplay;
+ slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
+
+ dsc->drm->slice_count = 1;
+ dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
+ total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
+ dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
+ dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
+
+ reg = dsc->bytes_per_pkt << 16;
+ reg |= (0x0b << 8); /* dtype of compressed image */
+
+ /* pkt_per_line:
+ * 0 == 1 pkt
+ * 1 == 2 pkt
+ * 2 == 4 pkt
+ * 3 pkt is not supported
+ * above translates to ffs() - 1
+ */
+ reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ reg |= dsc->eol_byte_num << 4;
+ reg |= 1;
+
+ dsi_write(msm_host,
+ REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
+ }
+
dsi_write(msm_host, REG_DSI_ACTIVE_H,
DSI_ACTIVE_H_START(ha_start) |
DSI_ACTIVE_H_END(ha_end));
@@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
} else { /* command mode */
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ u32 reg, reg_ctrl, reg_ctrl2;
+ u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
+
+ reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
+ reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
+
+ slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
+ bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
+ dsc->drm->bits_per_pixel, 8);
+ dsc->drm->slice_chunk_size = bytes_in_slice;
+ total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
+ dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
+
+ reg = 0x39 << 8;
+ reg |= ffs(dsc->pkt_per_line) << 6;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ reg |= dsc->eol_byte_num << 4;
+ reg |= 1;
+
+ reg_ctrl |= reg;
+ reg_ctrl2 |= bytes_in_slice;
+
+ dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
+ dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
+ }
+
/* image data and 1 byte write_memory_start cmd */
- wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ if (!msm_host->dsc)
+ wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ else
+ wc = mode->hdisplay / 2 + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-10 10:34 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-10 10:34 UTC (permalink / raw)
To: Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Vinod Koul, dri-devel,
Dmitry Baryshkov, freedreno
When DSC is enabled, we need to configure DSI registers accordingly and
configure the respective stream compression registers.
Add support to calculate the register setting based on DSC params and
timing information and configure these registers.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
2 files changed, 118 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
index 49b551ad1bff..c1c85df58c4b 100644
--- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
+++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
@@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
#define REG_DSI_CPHY_MODE_CTRL 0x000002d4
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
+
+#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
+
+#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
+
#endif /* DSI_XML */
diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index 438c80750682..3d8d5a1daaa3 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
}
+static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
+ int pic_width, int pic_height)
+{
+ if (!dsc || !pic_width || !pic_height) {
+ pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
+ return -EINVAL;
+ }
+
+ dsc->drm->pic_width = pic_width;
+ dsc->drm->pic_height = pic_height;
+
+ return 0;
+}
+
static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
{
struct drm_display_mode *mode = msm_host->mode;
@@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
hdisplay /= 2;
}
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+
+ /* update dsc params with timing params */
+ dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
+ DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
+
+ /* we do the calculations for dsc parameters here so that
+ * panel can use these parameters
+ */
+ dsi_populate_dsc_params(dsc);
+
+ /* Divide the display by 3 but keep back/font porch and
+ * pulse width same
+ */
+ h_total -= hdisplay;
+ hdisplay /= 3;
+ h_total += hdisplay;
+ ha_end = ha_start + hdisplay;
+ }
+
if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ u32 reg, intf_width, slice_per_intf;
+ u32 total_bytes_per_intf;
+
+ /* first calculate dsc parameters and then program
+ * compress mode registers
+ */
+ intf_width = hdisplay;
+ slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
+
+ dsc->drm->slice_count = 1;
+ dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
+ total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
+ dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
+ dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
+
+ reg = dsc->bytes_per_pkt << 16;
+ reg |= (0x0b << 8); /* dtype of compressed image */
+
+ /* pkt_per_line:
+ * 0 == 1 pkt
+ * 1 == 2 pkt
+ * 2 == 4 pkt
+ * 3 pkt is not supported
+ * above translates to ffs() - 1
+ */
+ reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ reg |= dsc->eol_byte_num << 4;
+ reg |= 1;
+
+ dsi_write(msm_host,
+ REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
+ }
+
dsi_write(msm_host, REG_DSI_ACTIVE_H,
DSI_ACTIVE_H_START(ha_start) |
DSI_ACTIVE_H_END(ha_end));
@@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
} else { /* command mode */
+ if (msm_host->dsc) {
+ struct msm_display_dsc_config *dsc = msm_host->dsc;
+ u32 reg, reg_ctrl, reg_ctrl2;
+ u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
+
+ reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
+ reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
+
+ slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
+ bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
+ dsc->drm->bits_per_pixel, 8);
+ dsc->drm->slice_chunk_size = bytes_in_slice;
+ total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
+ dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
+
+ reg = 0x39 << 8;
+ reg |= ffs(dsc->pkt_per_line) << 6;
+
+ dsc->eol_byte_num = total_bytes_per_intf % 3;
+ reg |= dsc->eol_byte_num << 4;
+ reg |= 1;
+
+ reg_ctrl |= reg;
+ reg_ctrl2 |= bytes_in_slice;
+
+ dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
+ dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
+ }
+
/* image data and 1 byte write_memory_start cmd */
- wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ if (!msm_host->dsc)
+ wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
+ else
+ wc = mode->hdisplay / 2 + 1;
dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
2.31.1
^ permalink raw reply related [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:39 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:39 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
@ 2022-02-10 10:39 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:39 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:43 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:43 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
The patch description is incorrect. We do not pass DSC parameters to the
panel driver. Instead we fetch them from the panel. Could you please
correct it?
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
@ 2022-02-10 10:43 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:43 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
The patch description is incorrect. We do not pass DSC parameters to the
panel driver. Instead we fetch them from the panel. Could you please
correct it?
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:47 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:47 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
> + * 2 encoders, 2 line mixers and 1 interface
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-02-10 10:47 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:47 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
> + * 2 encoders, 2 line mixers and 1 interface
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 10:55 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:55 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We cannot enable mode_3d when we are using the DSC. So pass
> configuration to detect DSC is enabled and not enable mode_3d
> when we are using DSC
>
> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> enabled and pass this to .setup_intf_cfg()
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
You seem to insist on this.
Ok, lets agree that you did not test any other topologies and let
anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle this.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 34a6940d12c5..ed37a4c21596 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
> intf_cfg.stream_sel = cmd_enc->stream_sel;
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ddd9d89cd456..218009855fca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
> intf_cfg.stream_sel = 0; /* Don't care value for video mode */
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> if (phys_enc->hw_pp->merge_3d)
> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 49659165cea8..6d5268b7da90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
>
> intf_cfg |= (cfg->intf & 0xF) << 4;
>
> - if (cfg->mode_3d) {
> + /* In DSC we can't set merge, so check for dsc and complain */
> + if (cfg->mode_3d && cfg->dsc)
> + pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
> +
> + /* set merge only when dsc is not set */
> + if (cfg->mode_3d && !cfg->dsc) {
> intf_cfg |= BIT(19);
> intf_cfg |= (cfg->mode_3d - 0x1) << 20;
> }
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-10 10:55 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 10:55 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We cannot enable mode_3d when we are using the DSC. So pass
> configuration to detect DSC is enabled and not enable mode_3d
> when we are using DSC
>
> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> enabled and pass this to .setup_intf_cfg()
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
You seem to insist on this.
Ok, lets agree that you did not test any other topologies and let
anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle this.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 34a6940d12c5..ed37a4c21596 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
> intf_cfg.stream_sel = cmd_enc->stream_sel;
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ddd9d89cd456..218009855fca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
> intf_cfg.stream_sel = 0; /* Don't care value for video mode */
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> if (phys_enc->hw_pp->merge_3d)
> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 49659165cea8..6d5268b7da90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
>
> intf_cfg |= (cfg->intf & 0xF) << 4;
>
> - if (cfg->mode_3d) {
> + /* In DSC we can't set merge, so check for dsc and complain */
> + if (cfg->mode_3d && cfg->dsc)
> + pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
> +
> + /* set merge only when dsc is not set */
> + if (cfg->mode_3d && !cfg->dsc) {
> intf_cfg |= BIT(19);
> intf_cfg |= (cfg->mode_3d - 0x1) << 20;
> }
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 11:07 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 11:07 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
@ 2022-02-10 11:07 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 11:07 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-10 11:13 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 11:13 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-10 11:13 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-10 11:13 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-16 18:57 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 18:57 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
> support by adding hw blocks for DSC
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Somehow second patch of this series is not showing up on patchwork in
your REPOST.
It jumps from 1 to 3.
That being said, please fix the copyright to 2022 in all your files.
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++
> 5 files changed, 314 insertions(+)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 03ab55c37beb..7ec3c70c77ce 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -56,6 +56,7 @@ msm-y := \
> disp/dpu1/dpu_formats.o \
> disp/dpu1/dpu_hw_catalog.o \
> disp/dpu1/dpu_hw_ctl.o \
> + disp/dpu1/dpu_hw_dsc.o \
> disp/dpu1/dpu_hw_interrupts.o \
> disp/dpu1/dpu_hw_intf.o \
> disp/dpu1/dpu_hw_lm.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 31af04afda7d..5fc0888351c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -556,6 +556,16 @@ struct dpu_merge_3d_cfg {
> const struct dpu_merge_3d_sub_blks *sblk;
> };
>
> +/**
> + * struct dpu_dsc_cfg - information of DSC blocks
> + * @id enum identifying this block
> + * @base register offset of this block
> + * @features bit mask identifying sub-blocks/features
> + */
> +struct dpu_dsc_cfg {
> + DPU_HW_BLK_INFO;
> +};
> +
> /**
> * struct dpu_intf_cfg - information of timing engine blocks
> * @id enum identifying this block
> @@ -752,6 +762,9 @@ struct dpu_mdss_cfg {
> u32 merge_3d_count;
> const struct dpu_merge_3d_cfg *merge_3d;
>
> + u32 dsc_count;
> + struct dpu_dsc_cfg *dsc;
> +
> u32 intf_count;
> const struct dpu_intf_cfg *intf;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> new file mode 100644
> index 000000000000..449d6f1dad28
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -0,0 +1,210 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, Linaro Limited
> + */
> +
> +#include "dpu_kms.h"
> +#include "dpu_hw_catalog.h"
> +#include "dpu_hwio.h"
> +#include "dpu_hw_mdss.h"
> +#include "dpu_hw_dsc.h"
> +
> +#define DSC_COMMON_MODE 0x000
> +#define DSC_ENC 0X004
> +#define DSC_PICTURE 0x008
> +#define DSC_SLICE 0x00C
> +#define DSC_CHUNK_SIZE 0x010
> +#define DSC_DELAY 0x014
> +#define DSC_SCALE_INITIAL 0x018
> +#define DSC_SCALE_DEC_INTERVAL 0x01C
> +#define DSC_SCALE_INC_INTERVAL 0x020
> +#define DSC_FIRST_LINE_BPG_OFFSET 0x024
> +#define DSC_BPG_OFFSET 0x028
> +#define DSC_DSC_OFFSET 0x02C
> +#define DSC_FLATNESS 0x030
> +#define DSC_RC_MODEL_SIZE 0x034
> +#define DSC_RC 0x038
> +#define DSC_RC_BUF_THRESH 0x03C
> +#define DSC_RANGE_MIN_QP 0x074
> +#define DSC_RANGE_MAX_QP 0x0B0
> +#define DSC_RANGE_BPG_OFFSET 0x0EC
> +
> +static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
> +{
> + struct dpu_hw_blk_reg_map *c = &dsc->hw;
> +
> + DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
> +}
> +
> +static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc, u32 mode)
> +{
> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> + u32 data, lsb, bpp;
> + u32 initial_lines = dsc->initial_lines;
> + bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
> +
> + DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
> +
> + if (is_cmd_mode)
> + initial_lines += 1;
> +
> + data = (initial_lines << 20);
> + data |= ((dsc->slice_last_group_size - 1) << 18);
> + /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
> + data |= dsc->drm->bits_per_pixel << 12;
> + lsb = dsc->drm->bits_per_pixel % 4;
> + bpp = dsc->drm->bits_per_pixel / 4;
> + bpp *= 4;
> + bpp <<= 4;
> + bpp |= lsb;
> +
> + data |= bpp << 8;
> + data |= (dsc->drm->block_pred_enable << 7);
> + data |= (dsc->drm->line_buf_depth << 3);
> + data |= (dsc->drm->simple_422 << 2);
> + data |= (dsc->drm->convert_rgb << 1);
> + data |= dsc->drm->bits_per_component;
> +
> + DPU_REG_WRITE(c, DSC_ENC, data);
> +
> + data = dsc->drm->pic_width << 16;
> + data |= dsc->drm->pic_height;
> + DPU_REG_WRITE(c, DSC_PICTURE, data);
> +
> + data = dsc->drm->slice_width << 16;
> + data |= dsc->drm->slice_height;
> + DPU_REG_WRITE(c, DSC_SLICE, data);
> +
> + data = dsc->drm->slice_chunk_size << 16;
> + DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
> +
> + data = dsc->drm->initial_dec_delay << 16;
> + data |= dsc->drm->initial_xmit_delay;
> + DPU_REG_WRITE(c, DSC_DELAY, data);
> +
> + data = dsc->drm->initial_scale_value;
> + DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
> +
> + data = dsc->drm->scale_decrement_interval;
> + DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
> +
> + data = dsc->drm->scale_increment_interval;
> + DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
> +
> + data = dsc->drm->first_line_bpg_offset;
> + DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
> +
> + data = dsc->drm->nfl_bpg_offset << 16;
> + data |= dsc->drm->slice_bpg_offset;
> + DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
> +
> + data = dsc->drm->initial_offset << 16;
> + data |= dsc->drm->final_offset;
> + DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
> +
> + data = dsc->det_thresh_flatness << 10;
> + data |= dsc->drm->flatness_max_qp << 5;
> + data |= dsc->drm->flatness_min_qp;
> + DPU_REG_WRITE(c, DSC_FLATNESS, data);
> +
> + data = dsc->drm->rc_model_size;
> + DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
> +
> + data = dsc->drm->rc_tgt_offset_low << 18;
> + data |= dsc->drm->rc_tgt_offset_high << 14;
> + data |= dsc->drm->rc_quant_incr_limit1 << 9;
> + data |= dsc->drm->rc_quant_incr_limit0 << 4;
> + data |= dsc->drm->rc_edge_factor;
> + DPU_REG_WRITE(c, DSC_RC, data);
> +}
> +
> +static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc)
> +{
> + struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> + u32 off;
> + int i;
> +
> + off = DSC_RC_BUF_THRESH;
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
> + DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_MIN_QP;
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_min_qp);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_MAX_QP;
> + for (i = 0; i < 15; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_max_qp);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_BPG_OFFSET;
> + for (i = 0; i < 15; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
> + off += 4;
> + }
> +}
> +
> +static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
> + struct dpu_mdss_cfg *m,
> + void __iomem *addr,
> + struct dpu_hw_blk_reg_map *b)
> +{
> + int i;
> +
> + for (i = 0; i < m->dsc_count; i++) {
> + if (dsc == m->dsc[i].id) {
> + b->base_off = addr;
> + b->blk_off = m->dsc[i].base;
> + b->length = m->dsc[i].len;
> + b->hwversion = m->hwversion;
> + b->log_mask = DPU_DBG_MASK_DSC;
> + return &m->dsc[i];
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
> + unsigned long cap)
> +{
> + ops->dsc_disable = dpu_hw_dsc_disable;
> + ops->dsc_config = dpu_hw_dsc_config;
> + ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
> +};
> +
> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
> + struct dpu_mdss_cfg *m)
> +{
> + struct dpu_hw_dsc *c;
> + struct dpu_dsc_cfg *cfg;
> +
> + c = kzalloc(sizeof(*c), GFP_KERNEL);
> + if (!c)
> + return ERR_PTR(-ENOMEM);
> +
> + cfg = _dsc_offset(idx, m, addr, &c->hw);
> + if (IS_ERR_OR_NULL(cfg)) {
> + kfree(c);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + c->idx = idx;
> + c->caps = cfg;
> + _setup_dsc_ops(&c->ops, c->caps->features);
> +
> + return c;
> +}
> +
> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
> +{
> + kfree(dsc);
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> new file mode 100644
> index 000000000000..648c9e4d8749
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright (c) 2020-2021, Linaro Limited */
> +
> +#ifndef _DPU_HW_DSC_H
> +#define _DPU_HW_DSC_H
> +
> +#include <drm/drm_dsc.h>
> +
> +#define DSC_MODE_SPLIT_PANEL BIT(0)
> +#define DSC_MODE_MULTIPLEX BIT(1)
> +#define DSC_MODE_VIDEO BIT(2)
> +
> +struct dpu_hw_dsc;
> +
> +/**
> + * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
> + * Assumption is these functions will be called after clocks are enabled
> + */
> +struct dpu_hw_dsc_ops {
> + /**
> + * dsc_disable - disable dsc
> + * @hw_dsc: Pointer to dsc context
> + */
> + void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
> +
> + /**
> + * dsc_config - configures dsc encoder
> + * @hw_dsc: Pointer to dsc context
> + * @dsc: panel dsc parameters
> + * @mode: dsc topology mode to be set
> + */
> + void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc, u32 mode);
> +
> + /**
> + * dsc_config_thresh - programs panel thresholds
> + * @hw_dsc: Pointer to dsc context
> + * @dsc: panel dsc parameters
> + */
> + void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc);
> +};
> +
> +struct dpu_hw_dsc {
> + struct dpu_hw_blk base;
> + struct dpu_hw_blk_reg_map hw;
> +
> + /* dsc */
> + enum dpu_dsc idx;
> + const struct dpu_dsc_cfg *caps;
> +
> + /* ops */
> + struct dpu_hw_dsc_ops ops;
> +};
> +
> +/**
> + * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
> + * @idx: DSC index for which driver object is required
> + * @addr: Mapped register io address of MDP
> + * @m: Pointer to mdss catalog data
> + * Returns: Error code or allocated dpu_hw_dsc context
> + */
> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
> + struct dpu_mdss_cfg *m);
> +
> +/**
> + * dpu_hw_dsc_destroy - destroys dsc driver context
> + * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
> + */
> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
> +
> +static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
> +{
> + return container_of(hw, struct dpu_hw_dsc, base);
> +}
> +
> +#endif /* _DPU_HW_DSC_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index bb9ceadeb0bb..b0ce8cb97d22 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
> DPU_HW_BLK_WB,
> DPU_HW_BLK_DSPP,
> DPU_HW_BLK_MERGE_3D,
> + DPU_HW_BLK_DSC,
> DPU_HW_BLK_MAX,
> };
>
> @@ -176,6 +177,17 @@ enum dpu_ctl {
> CTL_MAX
> };
>
> +enum dpu_dsc {
> + DSC_NONE = 0,
> + DSC_0,
> + DSC_1,
> + DSC_2,
> + DSC_3,
> + DSC_4,
> + DSC_5,
> + DSC_MAX
> +};
> +
> enum dpu_pingpong {
> PINGPONG_0 = 1,
> PINGPONG_1,
> @@ -437,5 +449,6 @@ struct dpu_mdss_color {
> #define DPU_DBG_MASK_VBIF (1 << 8)
> #define DPU_DBG_MASK_ROT (1 << 9)
> #define DPU_DBG_MASK_DSPP (1 << 10)
> +#define DPU_DBG_MASK_DSC (1 << 11)
>
> #endif /* _DPU_HW_MDSS_H */
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
@ 2022-02-16 18:57 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 18:57 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
> support by adding hw blocks for DSC
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Somehow second patch of this series is not showing up on patchwork in
your REPOST.
It jumps from 1 to 3.
That being said, please fix the copyright to 2022 in all your files.
> ---
> drivers/gpu/drm/msm/Makefile | 1 +
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++
> 5 files changed, 314 insertions(+)
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>
> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
> index 03ab55c37beb..7ec3c70c77ce 100644
> --- a/drivers/gpu/drm/msm/Makefile
> +++ b/drivers/gpu/drm/msm/Makefile
> @@ -56,6 +56,7 @@ msm-y := \
> disp/dpu1/dpu_formats.o \
> disp/dpu1/dpu_hw_catalog.o \
> disp/dpu1/dpu_hw_ctl.o \
> + disp/dpu1/dpu_hw_dsc.o \
> disp/dpu1/dpu_hw_interrupts.o \
> disp/dpu1/dpu_hw_intf.o \
> disp/dpu1/dpu_hw_lm.o \
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 31af04afda7d..5fc0888351c7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -556,6 +556,16 @@ struct dpu_merge_3d_cfg {
> const struct dpu_merge_3d_sub_blks *sblk;
> };
>
> +/**
> + * struct dpu_dsc_cfg - information of DSC blocks
> + * @id enum identifying this block
> + * @base register offset of this block
> + * @features bit mask identifying sub-blocks/features
> + */
> +struct dpu_dsc_cfg {
> + DPU_HW_BLK_INFO;
> +};
> +
> /**
> * struct dpu_intf_cfg - information of timing engine blocks
> * @id enum identifying this block
> @@ -752,6 +762,9 @@ struct dpu_mdss_cfg {
> u32 merge_3d_count;
> const struct dpu_merge_3d_cfg *merge_3d;
>
> + u32 dsc_count;
> + struct dpu_dsc_cfg *dsc;
> +
> u32 intf_count;
> const struct dpu_intf_cfg *intf;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> new file mode 100644
> index 000000000000..449d6f1dad28
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
> @@ -0,0 +1,210 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2020-2021, Linaro Limited
> + */
> +
> +#include "dpu_kms.h"
> +#include "dpu_hw_catalog.h"
> +#include "dpu_hwio.h"
> +#include "dpu_hw_mdss.h"
> +#include "dpu_hw_dsc.h"
> +
> +#define DSC_COMMON_MODE 0x000
> +#define DSC_ENC 0X004
> +#define DSC_PICTURE 0x008
> +#define DSC_SLICE 0x00C
> +#define DSC_CHUNK_SIZE 0x010
> +#define DSC_DELAY 0x014
> +#define DSC_SCALE_INITIAL 0x018
> +#define DSC_SCALE_DEC_INTERVAL 0x01C
> +#define DSC_SCALE_INC_INTERVAL 0x020
> +#define DSC_FIRST_LINE_BPG_OFFSET 0x024
> +#define DSC_BPG_OFFSET 0x028
> +#define DSC_DSC_OFFSET 0x02C
> +#define DSC_FLATNESS 0x030
> +#define DSC_RC_MODEL_SIZE 0x034
> +#define DSC_RC 0x038
> +#define DSC_RC_BUF_THRESH 0x03C
> +#define DSC_RANGE_MIN_QP 0x074
> +#define DSC_RANGE_MAX_QP 0x0B0
> +#define DSC_RANGE_BPG_OFFSET 0x0EC
> +
> +static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
> +{
> + struct dpu_hw_blk_reg_map *c = &dsc->hw;
> +
> + DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
> +}
> +
> +static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc, u32 mode)
> +{
> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> + u32 data, lsb, bpp;
> + u32 initial_lines = dsc->initial_lines;
> + bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
> +
> + DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
> +
> + if (is_cmd_mode)
> + initial_lines += 1;
> +
> + data = (initial_lines << 20);
> + data |= ((dsc->slice_last_group_size - 1) << 18);
> + /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
> + data |= dsc->drm->bits_per_pixel << 12;
> + lsb = dsc->drm->bits_per_pixel % 4;
> + bpp = dsc->drm->bits_per_pixel / 4;
> + bpp *= 4;
> + bpp <<= 4;
> + bpp |= lsb;
> +
> + data |= bpp << 8;
> + data |= (dsc->drm->block_pred_enable << 7);
> + data |= (dsc->drm->line_buf_depth << 3);
> + data |= (dsc->drm->simple_422 << 2);
> + data |= (dsc->drm->convert_rgb << 1);
> + data |= dsc->drm->bits_per_component;
> +
> + DPU_REG_WRITE(c, DSC_ENC, data);
> +
> + data = dsc->drm->pic_width << 16;
> + data |= dsc->drm->pic_height;
> + DPU_REG_WRITE(c, DSC_PICTURE, data);
> +
> + data = dsc->drm->slice_width << 16;
> + data |= dsc->drm->slice_height;
> + DPU_REG_WRITE(c, DSC_SLICE, data);
> +
> + data = dsc->drm->slice_chunk_size << 16;
> + DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
> +
> + data = dsc->drm->initial_dec_delay << 16;
> + data |= dsc->drm->initial_xmit_delay;
> + DPU_REG_WRITE(c, DSC_DELAY, data);
> +
> + data = dsc->drm->initial_scale_value;
> + DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
> +
> + data = dsc->drm->scale_decrement_interval;
> + DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
> +
> + data = dsc->drm->scale_increment_interval;
> + DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
> +
> + data = dsc->drm->first_line_bpg_offset;
> + DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
> +
> + data = dsc->drm->nfl_bpg_offset << 16;
> + data |= dsc->drm->slice_bpg_offset;
> + DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
> +
> + data = dsc->drm->initial_offset << 16;
> + data |= dsc->drm->final_offset;
> + DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
> +
> + data = dsc->det_thresh_flatness << 10;
> + data |= dsc->drm->flatness_max_qp << 5;
> + data |= dsc->drm->flatness_min_qp;
> + DPU_REG_WRITE(c, DSC_FLATNESS, data);
> +
> + data = dsc->drm->rc_model_size;
> + DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
> +
> + data = dsc->drm->rc_tgt_offset_low << 18;
> + data |= dsc->drm->rc_tgt_offset_high << 14;
> + data |= dsc->drm->rc_quant_incr_limit1 << 9;
> + data |= dsc->drm->rc_quant_incr_limit0 << 4;
> + data |= dsc->drm->rc_edge_factor;
> + DPU_REG_WRITE(c, DSC_RC, data);
> +}
> +
> +static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc)
> +{
> + struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
> + u32 off;
> + int i;
> +
> + off = DSC_RC_BUF_THRESH;
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
> + DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_MIN_QP;
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_min_qp);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_MAX_QP;
> + for (i = 0; i < 15; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_max_qp);
> + off += 4;
> + }
> +
> + off = DSC_RANGE_BPG_OFFSET;
> + for (i = 0; i < 15; i++) {
> + DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
> + off += 4;
> + }
> +}
> +
> +static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
> + struct dpu_mdss_cfg *m,
> + void __iomem *addr,
> + struct dpu_hw_blk_reg_map *b)
> +{
> + int i;
> +
> + for (i = 0; i < m->dsc_count; i++) {
> + if (dsc == m->dsc[i].id) {
> + b->base_off = addr;
> + b->blk_off = m->dsc[i].base;
> + b->length = m->dsc[i].len;
> + b->hwversion = m->hwversion;
> + b->log_mask = DPU_DBG_MASK_DSC;
> + return &m->dsc[i];
> + }
> + }
> +
> + return NULL;
> +}
> +
> +static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
> + unsigned long cap)
> +{
> + ops->dsc_disable = dpu_hw_dsc_disable;
> + ops->dsc_config = dpu_hw_dsc_config;
> + ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
> +};
> +
> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
> + struct dpu_mdss_cfg *m)
> +{
> + struct dpu_hw_dsc *c;
> + struct dpu_dsc_cfg *cfg;
> +
> + c = kzalloc(sizeof(*c), GFP_KERNEL);
> + if (!c)
> + return ERR_PTR(-ENOMEM);
> +
> + cfg = _dsc_offset(idx, m, addr, &c->hw);
> + if (IS_ERR_OR_NULL(cfg)) {
> + kfree(c);
> + return ERR_PTR(-EINVAL);
> + }
> +
> + c->idx = idx;
> + c->caps = cfg;
> + _setup_dsc_ops(&c->ops, c->caps->features);
> +
> + return c;
> +}
> +
> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
> +{
> + kfree(dsc);
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> new file mode 100644
> index 000000000000..648c9e4d8749
> --- /dev/null
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
> @@ -0,0 +1,77 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/* Copyright (c) 2020-2021, Linaro Limited */
> +
> +#ifndef _DPU_HW_DSC_H
> +#define _DPU_HW_DSC_H
> +
> +#include <drm/drm_dsc.h>
> +
> +#define DSC_MODE_SPLIT_PANEL BIT(0)
> +#define DSC_MODE_MULTIPLEX BIT(1)
> +#define DSC_MODE_VIDEO BIT(2)
> +
> +struct dpu_hw_dsc;
> +
> +/**
> + * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
> + * Assumption is these functions will be called after clocks are enabled
> + */
> +struct dpu_hw_dsc_ops {
> + /**
> + * dsc_disable - disable dsc
> + * @hw_dsc: Pointer to dsc context
> + */
> + void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
> +
> + /**
> + * dsc_config - configures dsc encoder
> + * @hw_dsc: Pointer to dsc context
> + * @dsc: panel dsc parameters
> + * @mode: dsc topology mode to be set
> + */
> + void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc, u32 mode);
> +
> + /**
> + * dsc_config_thresh - programs panel thresholds
> + * @hw_dsc: Pointer to dsc context
> + * @dsc: panel dsc parameters
> + */
> + void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
> + struct msm_display_dsc_config *dsc);
> +};
> +
> +struct dpu_hw_dsc {
> + struct dpu_hw_blk base;
> + struct dpu_hw_blk_reg_map hw;
> +
> + /* dsc */
> + enum dpu_dsc idx;
> + const struct dpu_dsc_cfg *caps;
> +
> + /* ops */
> + struct dpu_hw_dsc_ops ops;
> +};
> +
> +/**
> + * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
> + * @idx: DSC index for which driver object is required
> + * @addr: Mapped register io address of MDP
> + * @m: Pointer to mdss catalog data
> + * Returns: Error code or allocated dpu_hw_dsc context
> + */
> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
> + struct dpu_mdss_cfg *m);
> +
> +/**
> + * dpu_hw_dsc_destroy - destroys dsc driver context
> + * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
> + */
> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
> +
> +static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
> +{
> + return container_of(hw, struct dpu_hw_dsc, base);
> +}
> +
> +#endif /* _DPU_HW_DSC_H */
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> index bb9ceadeb0bb..b0ce8cb97d22 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
> @@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
> DPU_HW_BLK_WB,
> DPU_HW_BLK_DSPP,
> DPU_HW_BLK_MERGE_3D,
> + DPU_HW_BLK_DSC,
> DPU_HW_BLK_MAX,
> };
>
> @@ -176,6 +177,17 @@ enum dpu_ctl {
> CTL_MAX
> };
>
> +enum dpu_dsc {
> + DSC_NONE = 0,
> + DSC_0,
> + DSC_1,
> + DSC_2,
> + DSC_3,
> + DSC_4,
> + DSC_5,
> + DSC_MAX
> +};
> +
> enum dpu_pingpong {
> PINGPONG_0 = 1,
> PINGPONG_1,
> @@ -437,5 +449,6 @@ struct dpu_mdss_color {
> #define DPU_DBG_MASK_VBIF (1 << 8)
> #define DPU_DBG_MASK_ROT (1 << 9)
> #define DPU_DBG_MASK_DSPP (1 << 10)
> +#define DPU_DBG_MASK_DSC (1 << 11)
>
> #endif /* _DPU_HW_MDSS_H */
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-16 19:42 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:42 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Daniel Vetter,
Dmitry Baryshkov, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This adds SDM845 DSC blocks into hw_catalog
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index aa75991903a6..9c09cf318dfb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -821,6 +821,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
> PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
> };
> +
> +/*************************************************************
> + * DSC sub blocks config
> + *************************************************************/
> +#define DSC_BLK(_name, _id, _base) \
> + {\
> + .name = _name, .id = _id, \
> + .base = _base, .len = 0x140, \
> + .features = 0, \
> + }
> +
> +static struct dpu_dsc_cfg sdm845_dsc[] = {
> + DSC_BLK("dsc_0", DSC_0, 0x80000),
> + DSC_BLK("dsc_1", DSC_1, 0x80400),
> + DSC_BLK("dsc_2", DSC_2, 0x80800),
> + DSC_BLK("dsc_3", DSC_3, 0x80c00),
> +};
> +
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> @@ -1124,6 +1142,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
> .mixer = sdm845_lm,
> .pingpong_count = ARRAY_SIZE(sdm845_pp),
> .pingpong = sdm845_pp,
> + .dsc_count = ARRAY_SIZE(sdm845_dsc),
> + .dsc = sdm845_dsc,
> .intf_count = ARRAY_SIZE(sdm845_intf),
> .intf = sdm845_intf,
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog
@ 2022-02-16 19:42 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:42 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This adds SDM845 DSC blocks into hw_catalog
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 +++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index aa75991903a6..9c09cf318dfb 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -821,6 +821,24 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = {
> PP_BLK("pingpong_2", PINGPONG_2, 0x6b000, 0, sc7280_pp_sblk, -1, -1),
> PP_BLK("pingpong_3", PINGPONG_3, 0x6c000, 0, sc7280_pp_sblk, -1, -1),
> };
> +
> +/*************************************************************
> + * DSC sub blocks config
> + *************************************************************/
> +#define DSC_BLK(_name, _id, _base) \
> + {\
> + .name = _name, .id = _id, \
> + .base = _base, .len = 0x140, \
> + .features = 0, \
> + }
> +
> +static struct dpu_dsc_cfg sdm845_dsc[] = {
> + DSC_BLK("dsc_0", DSC_0, 0x80000),
> + DSC_BLK("dsc_1", DSC_1, 0x80400),
> + DSC_BLK("dsc_2", DSC_2, 0x80800),
> + DSC_BLK("dsc_3", DSC_3, 0x80c00),
> +};
> +
> /*************************************************************
> * INTF sub blocks config
> *************************************************************/
> @@ -1124,6 +1142,8 @@ static void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
> .mixer = sdm845_lm,
> .pingpong_count = ARRAY_SIZE(sdm845_pp),
> .pingpong = sdm845_pp,
> + .dsc_count = ARRAY_SIZE(sdm845_dsc),
> + .dsc = sdm845_dsc,
> .intf_count = ARRAY_SIZE(sdm845_intf),
> .intf = sdm845_intf,
> .vbif_count = ARRAY_SIZE(sdm845_vbif),
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
2022-02-16 18:57 ` Abhinav Kumar
(?)
@ 2022-02-16 19:46 ` Dmitry Baryshkov
2022-02-17 4:20 ` Vinod Koul
-1 siblings, 1 reply; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-16 19:46 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 16/02/2022 21:57, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>> Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
>> support by adding hw blocks for DSC
>>
>> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> Somehow second patch of this series is not showing up on patchwork in
> your REPOST.
>
> It jumps from 1 to 3.
patch 2: https://patchwork.freedesktop.org/patch/473356/?series=99959&rev=1
>
> That being said, please fix the copyright to 2022 in all your files.
>
>> ---
>> drivers/gpu/drm/msm/Makefile | 1 +
>> .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 13 ++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 210 ++++++++++++++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 77 +++++++
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 13 ++
>> 5 files changed, 314 insertions(+)
>> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
>> create mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>>
>> diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile
>> index 03ab55c37beb..7ec3c70c77ce 100644
>> --- a/drivers/gpu/drm/msm/Makefile
>> +++ b/drivers/gpu/drm/msm/Makefile
>> @@ -56,6 +56,7 @@ msm-y := \
>> disp/dpu1/dpu_formats.o \
>> disp/dpu1/dpu_hw_catalog.o \
>> disp/dpu1/dpu_hw_ctl.o \
>> + disp/dpu1/dpu_hw_dsc.o \
>> disp/dpu1/dpu_hw_interrupts.o \
>> disp/dpu1/dpu_hw_intf.o \
>> disp/dpu1/dpu_hw_lm.o \
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> index 31af04afda7d..5fc0888351c7 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>> @@ -556,6 +556,16 @@ struct dpu_merge_3d_cfg {
>> const struct dpu_merge_3d_sub_blks *sblk;
>> };
>> +/**
>> + * struct dpu_dsc_cfg - information of DSC blocks
>> + * @id enum identifying this block
>> + * @base register offset of this block
>> + * @features bit mask identifying sub-blocks/features
>> + */
>> +struct dpu_dsc_cfg {
>> + DPU_HW_BLK_INFO;
>> +};
>> +
>> /**
>> * struct dpu_intf_cfg - information of timing engine blocks
>> * @id enum identifying this block
>> @@ -752,6 +762,9 @@ struct dpu_mdss_cfg {
>> u32 merge_3d_count;
>> const struct dpu_merge_3d_cfg *merge_3d;
>> + u32 dsc_count;
>> + struct dpu_dsc_cfg *dsc;
>> +
>> u32 intf_count;
>> const struct dpu_intf_cfg *intf;
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
>> new file mode 100644
>> index 000000000000..449d6f1dad28
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c
>> @@ -0,0 +1,210 @@
>> +// SPDX-License-Identifier: GPL-2.0-only
>> +/*
>> + * Copyright (c) 2020-2021, Linaro Limited
>> + */
>> +
>> +#include "dpu_kms.h"
>> +#include "dpu_hw_catalog.h"
>> +#include "dpu_hwio.h"
>> +#include "dpu_hw_mdss.h"
>> +#include "dpu_hw_dsc.h"
>> +
>> +#define DSC_COMMON_MODE 0x000
>> +#define DSC_ENC 0X004
>> +#define DSC_PICTURE 0x008
>> +#define DSC_SLICE 0x00C
>> +#define DSC_CHUNK_SIZE 0x010
>> +#define DSC_DELAY 0x014
>> +#define DSC_SCALE_INITIAL 0x018
>> +#define DSC_SCALE_DEC_INTERVAL 0x01C
>> +#define DSC_SCALE_INC_INTERVAL 0x020
>> +#define DSC_FIRST_LINE_BPG_OFFSET 0x024
>> +#define DSC_BPG_OFFSET 0x028
>> +#define DSC_DSC_OFFSET 0x02C
>> +#define DSC_FLATNESS 0x030
>> +#define DSC_RC_MODEL_SIZE 0x034
>> +#define DSC_RC 0x038
>> +#define DSC_RC_BUF_THRESH 0x03C
>> +#define DSC_RANGE_MIN_QP 0x074
>> +#define DSC_RANGE_MAX_QP 0x0B0
>> +#define DSC_RANGE_BPG_OFFSET 0x0EC
>> +
>> +static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
>> +{
>> + struct dpu_hw_blk_reg_map *c = &dsc->hw;
>> +
>> + DPU_REG_WRITE(c, DSC_COMMON_MODE, 0);
>> +}
>> +
>> +static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
>> + struct msm_display_dsc_config *dsc, u32 mode)
>> +{
>> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
>> + u32 data, lsb, bpp;
>> + u32 initial_lines = dsc->initial_lines;
>> + bool is_cmd_mode = !(mode & DSC_MODE_VIDEO);
>> +
>> + DPU_REG_WRITE(c, DSC_COMMON_MODE, mode);
>> +
>> + if (is_cmd_mode)
>> + initial_lines += 1;
>> +
>> + data = (initial_lines << 20);
>> + data |= ((dsc->slice_last_group_size - 1) << 18);
>> + /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
>> + data |= dsc->drm->bits_per_pixel << 12;
>> + lsb = dsc->drm->bits_per_pixel % 4;
>> + bpp = dsc->drm->bits_per_pixel / 4;
>> + bpp *= 4;
>> + bpp <<= 4;
>> + bpp |= lsb;
>> +
>> + data |= bpp << 8;
>> + data |= (dsc->drm->block_pred_enable << 7);
>> + data |= (dsc->drm->line_buf_depth << 3);
>> + data |= (dsc->drm->simple_422 << 2);
>> + data |= (dsc->drm->convert_rgb << 1);
>> + data |= dsc->drm->bits_per_component;
>> +
>> + DPU_REG_WRITE(c, DSC_ENC, data);
>> +
>> + data = dsc->drm->pic_width << 16;
>> + data |= dsc->drm->pic_height;
>> + DPU_REG_WRITE(c, DSC_PICTURE, data);
>> +
>> + data = dsc->drm->slice_width << 16;
>> + data |= dsc->drm->slice_height;
>> + DPU_REG_WRITE(c, DSC_SLICE, data);
>> +
>> + data = dsc->drm->slice_chunk_size << 16;
>> + DPU_REG_WRITE(c, DSC_CHUNK_SIZE, data);
>> +
>> + data = dsc->drm->initial_dec_delay << 16;
>> + data |= dsc->drm->initial_xmit_delay;
>> + DPU_REG_WRITE(c, DSC_DELAY, data);
>> +
>> + data = dsc->drm->initial_scale_value;
>> + DPU_REG_WRITE(c, DSC_SCALE_INITIAL, data);
>> +
>> + data = dsc->drm->scale_decrement_interval;
>> + DPU_REG_WRITE(c, DSC_SCALE_DEC_INTERVAL, data);
>> +
>> + data = dsc->drm->scale_increment_interval;
>> + DPU_REG_WRITE(c, DSC_SCALE_INC_INTERVAL, data);
>> +
>> + data = dsc->drm->first_line_bpg_offset;
>> + DPU_REG_WRITE(c, DSC_FIRST_LINE_BPG_OFFSET, data);
>> +
>> + data = dsc->drm->nfl_bpg_offset << 16;
>> + data |= dsc->drm->slice_bpg_offset;
>> + DPU_REG_WRITE(c, DSC_BPG_OFFSET, data);
>> +
>> + data = dsc->drm->initial_offset << 16;
>> + data |= dsc->drm->final_offset;
>> + DPU_REG_WRITE(c, DSC_DSC_OFFSET, data);
>> +
>> + data = dsc->det_thresh_flatness << 10;
>> + data |= dsc->drm->flatness_max_qp << 5;
>> + data |= dsc->drm->flatness_min_qp;
>> + DPU_REG_WRITE(c, DSC_FLATNESS, data);
>> +
>> + data = dsc->drm->rc_model_size;
>> + DPU_REG_WRITE(c, DSC_RC_MODEL_SIZE, data);
>> +
>> + data = dsc->drm->rc_tgt_offset_low << 18;
>> + data |= dsc->drm->rc_tgt_offset_high << 14;
>> + data |= dsc->drm->rc_quant_incr_limit1 << 9;
>> + data |= dsc->drm->rc_quant_incr_limit0 << 4;
>> + data |= dsc->drm->rc_edge_factor;
>> + DPU_REG_WRITE(c, DSC_RC, data);
>> +}
>> +
>> +static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
>> + struct msm_display_dsc_config *dsc)
>> +{
>> + struct drm_dsc_rc_range_parameters *rc = dsc->drm->rc_range_params;
>> + struct dpu_hw_blk_reg_map *c = &hw_dsc->hw;
>> + u32 off;
>> + int i;
>> +
>> + off = DSC_RC_BUF_THRESH;
>> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) {
>> + DPU_REG_WRITE(c, off, dsc->drm->rc_buf_thresh[i]);
>> + off += 4;
>> + }
>> +
>> + off = DSC_RANGE_MIN_QP;
>> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
>> + DPU_REG_WRITE(c, off, rc[i].range_min_qp);
>> + off += 4;
>> + }
>> +
>> + off = DSC_RANGE_MAX_QP;
>> + for (i = 0; i < 15; i++) {
>> + DPU_REG_WRITE(c, off, rc[i].range_max_qp);
>> + off += 4;
>> + }
>> +
>> + off = DSC_RANGE_BPG_OFFSET;
>> + for (i = 0; i < 15; i++) {
>> + DPU_REG_WRITE(c, off, rc[i].range_bpg_offset);
>> + off += 4;
>> + }
>> +}
>> +
>> +static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
>> + struct dpu_mdss_cfg *m,
>> + void __iomem *addr,
>> + struct dpu_hw_blk_reg_map *b)
>> +{
>> + int i;
>> +
>> + for (i = 0; i < m->dsc_count; i++) {
>> + if (dsc == m->dsc[i].id) {
>> + b->base_off = addr;
>> + b->blk_off = m->dsc[i].base;
>> + b->length = m->dsc[i].len;
>> + b->hwversion = m->hwversion;
>> + b->log_mask = DPU_DBG_MASK_DSC;
>> + return &m->dsc[i];
>> + }
>> + }
>> +
>> + return NULL;
>> +}
>> +
>> +static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
>> + unsigned long cap)
>> +{
>> + ops->dsc_disable = dpu_hw_dsc_disable;
>> + ops->dsc_config = dpu_hw_dsc_config;
>> + ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
>> +};
>> +
>> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
>> + struct dpu_mdss_cfg *m)
>> +{
>> + struct dpu_hw_dsc *c;
>> + struct dpu_dsc_cfg *cfg;
>> +
>> + c = kzalloc(sizeof(*c), GFP_KERNEL);
>> + if (!c)
>> + return ERR_PTR(-ENOMEM);
>> +
>> + cfg = _dsc_offset(idx, m, addr, &c->hw);
>> + if (IS_ERR_OR_NULL(cfg)) {
>> + kfree(c);
>> + return ERR_PTR(-EINVAL);
>> + }
>> +
>> + c->idx = idx;
>> + c->caps = cfg;
>> + _setup_dsc_ops(&c->ops, c->caps->features);
>> +
>> + return c;
>> +}
>> +
>> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
>> +{
>> + kfree(dsc);
>> +}
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>> new file mode 100644
>> index 000000000000..648c9e4d8749
>> --- /dev/null
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h
>> @@ -0,0 +1,77 @@
>> +/* SPDX-License-Identifier: GPL-2.0-only */
>> +/* Copyright (c) 2020-2021, Linaro Limited */
>> +
>> +#ifndef _DPU_HW_DSC_H
>> +#define _DPU_HW_DSC_H
>> +
>> +#include <drm/drm_dsc.h>
>> +
>> +#define DSC_MODE_SPLIT_PANEL BIT(0)
>> +#define DSC_MODE_MULTIPLEX BIT(1)
>> +#define DSC_MODE_VIDEO BIT(2)
>> +
>> +struct dpu_hw_dsc;
>> +
>> +/**
>> + * struct dpu_hw_dsc_ops - interface to the dsc hardware driver
>> functions
>> + * Assumption is these functions will be called after clocks are enabled
>> + */
>> +struct dpu_hw_dsc_ops {
>> + /**
>> + * dsc_disable - disable dsc
>> + * @hw_dsc: Pointer to dsc context
>> + */
>> + void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
>> +
>> + /**
>> + * dsc_config - configures dsc encoder
>> + * @hw_dsc: Pointer to dsc context
>> + * @dsc: panel dsc parameters
>> + * @mode: dsc topology mode to be set
>> + */
>> + void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
>> + struct msm_display_dsc_config *dsc, u32 mode);
>> +
>> + /**
>> + * dsc_config_thresh - programs panel thresholds
>> + * @hw_dsc: Pointer to dsc context
>> + * @dsc: panel dsc parameters
>> + */
>> + void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
>> + struct msm_display_dsc_config *dsc);
>> +};
>> +
>> +struct dpu_hw_dsc {
>> + struct dpu_hw_blk base;
>> + struct dpu_hw_blk_reg_map hw;
>> +
>> + /* dsc */
>> + enum dpu_dsc idx;
>> + const struct dpu_dsc_cfg *caps;
>> +
>> + /* ops */
>> + struct dpu_hw_dsc_ops ops;
>> +};
>> +
>> +/**
>> + * dpu_hw_dsc_init - initializes the dsc block for the passed dsc idx.
>> + * @idx: DSC index for which driver object is required
>> + * @addr: Mapped register io address of MDP
>> + * @m: Pointer to mdss catalog data
>> + * Returns: Error code or allocated dpu_hw_dsc context
>> + */
>> +struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx, void __iomem *addr,
>> + struct dpu_mdss_cfg *m);
>> +
>> +/**
>> + * dpu_hw_dsc_destroy - destroys dsc driver context
>> + * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
>> + */
>> +void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
>> +
>> +static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
>> +{
>> + return container_of(hw, struct dpu_hw_dsc, base);
>> +}
>> +
>> +#endif /* _DPU_HW_DSC_H */
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> index bb9ceadeb0bb..b0ce8cb97d22 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h
>> @@ -97,6 +97,7 @@ enum dpu_hw_blk_type {
>> DPU_HW_BLK_WB,
>> DPU_HW_BLK_DSPP,
>> DPU_HW_BLK_MERGE_3D,
>> + DPU_HW_BLK_DSC,
>> DPU_HW_BLK_MAX,
>> };
>> @@ -176,6 +177,17 @@ enum dpu_ctl {
>> CTL_MAX
>> };
>> +enum dpu_dsc {
>> + DSC_NONE = 0,
>> + DSC_0,
>> + DSC_1,
>> + DSC_2,
>> + DSC_3,
>> + DSC_4,
>> + DSC_5,
>> + DSC_MAX
>> +};
>> +
>> enum dpu_pingpong {
>> PINGPONG_0 = 1,
>> PINGPONG_1,
>> @@ -437,5 +449,6 @@ struct dpu_mdss_color {
>> #define DPU_DBG_MASK_VBIF (1 << 8)
>> #define DPU_DBG_MASK_ROT (1 << 9)
>> #define DPU_DBG_MASK_DSPP (1 << 10)
>> +#define DPU_DBG_MASK_DSC (1 << 11)
>> #endif /* _DPU_HW_MDSS_H */
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-16 19:49 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:49 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> In SDM845, DSC can be enabled by writing to pingpong block registers, so
> add support for DSC in hw_pp
>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
For the sake of uniformity, please use
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> index 55766c97c4c8..47c6ab6caf95 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> @@ -28,6 +28,9 @@
> #define PP_FBC_MODE 0x034
> #define PP_FBC_BUDGET_CTL 0x038
> #define PP_FBC_LOSSY_MODE 0x03C
> +#define PP_DSC_MODE 0x0a0
> +#define PP_DCE_DATA_IN_SWAP 0x0ac
> +#define PP_DCE_DATA_OUT_SWAP 0x0c8
>
> #define PP_DITHER_EN 0x000
> #define PP_DITHER_BITDEPTH 0x004
> @@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
> return line;
> }
>
> +static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *c = &pp->hw;
> +
> + DPU_REG_WRITE(c, PP_DSC_MODE, 1);
> + return 0;
> +}
> +
> +static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *c = &pp->hw;
> +
> + DPU_REG_WRITE(c, PP_DSC_MODE, 0);
> +}
> +
> +static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *pp_c = &pp->hw;
> + int data;
> +
> + data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);
> + data |= BIT(18); /* endian flip */
> + DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);
> + return 0;
> +}
> +
> static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> unsigned long features)
> {
> @@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
> c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
> c->ops.get_line_count = dpu_hw_pp_get_line_count;
> + c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
> + c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
> + c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
>
> if (test_bit(DPU_PINGPONG_DITHER, &features))
> c->ops.setup_dither = dpu_hw_pp_setup_dither;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> index 89d08a715c16..12758468d9ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> @@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops {
> */
> void (*setup_dither)(struct dpu_hw_pingpong *pp,
> struct dpu_hw_dither_cfg *cfg);
> + /**
> + * Enable DSC
> + */
> + int (*enable_dsc)(struct dpu_hw_pingpong *pp);
> +
> + /**
> + * Disable DSC
> + */
> + void (*disable_dsc)(struct dpu_hw_pingpong *pp);
> +
> + /**
> + * Setup DSC
> + */
> + int (*setup_dsc)(struct dpu_hw_pingpong *pp);
> };
>
> struct dpu_hw_merge_3d;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
@ 2022-02-16 19:49 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:49 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> In SDM845, DSC can be enabled by writing to pingpong block registers, so
> add support for DSC in hw_pp
>
> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
For the sake of uniformity, please use
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 32 +++++++++++++++++++
> .../gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 14 ++++++++
> 2 files changed, 46 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> index 55766c97c4c8..47c6ab6caf95 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c
> @@ -28,6 +28,9 @@
> #define PP_FBC_MODE 0x034
> #define PP_FBC_BUDGET_CTL 0x038
> #define PP_FBC_LOSSY_MODE 0x03C
> +#define PP_DSC_MODE 0x0a0
> +#define PP_DCE_DATA_IN_SWAP 0x0ac
> +#define PP_DCE_DATA_OUT_SWAP 0x0c8
>
> #define PP_DITHER_EN 0x000
> #define PP_DITHER_BITDEPTH 0x004
> @@ -245,6 +248,32 @@ static u32 dpu_hw_pp_get_line_count(struct dpu_hw_pingpong *pp)
> return line;
> }
>
> +static int dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *c = &pp->hw;
> +
> + DPU_REG_WRITE(c, PP_DSC_MODE, 1);
> + return 0;
> +}
> +
> +static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *c = &pp->hw;
> +
> + DPU_REG_WRITE(c, PP_DSC_MODE, 0);
> +}
> +
> +static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
> +{
> + struct dpu_hw_blk_reg_map *pp_c = &pp->hw;
> + int data;
> +
> + data = DPU_REG_READ(pp_c, PP_DCE_DATA_OUT_SWAP);
> + data |= BIT(18); /* endian flip */
> + DPU_REG_WRITE(pp_c, PP_DCE_DATA_OUT_SWAP, data);
> + return 0;
> +}
> +
> static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> unsigned long features)
> {
> @@ -256,6 +285,9 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong *c,
> c->ops.get_autorefresh = dpu_hw_pp_get_autorefresh_config;
> c->ops.poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
> c->ops.get_line_count = dpu_hw_pp_get_line_count;
> + c->ops.setup_dsc = dpu_hw_pp_setup_dsc;
> + c->ops.enable_dsc = dpu_hw_pp_dsc_enable;
> + c->ops.disable_dsc = dpu_hw_pp_dsc_disable;
>
> if (test_bit(DPU_PINGPONG_DITHER, &features))
> c->ops.setup_dither = dpu_hw_pp_setup_dither;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> index 89d08a715c16..12758468d9ca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h
> @@ -124,6 +124,20 @@ struct dpu_hw_pingpong_ops {
> */
> void (*setup_dither)(struct dpu_hw_pingpong *pp,
> struct dpu_hw_dither_cfg *cfg);
> + /**
> + * Enable DSC
> + */
> + int (*enable_dsc)(struct dpu_hw_pingpong *pp);
> +
> + /**
> + * Disable DSC
> + */
> + void (*disable_dsc)(struct dpu_hw_pingpong *pp);
> +
> + /**
> + * Setup DSC
> + */
> + int (*setup_dsc)(struct dpu_hw_pingpong *pp);
> };
>
> struct dpu_hw_merge_3d;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-16 19:52 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:52 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Daniel Vetter,
Dmitry Baryshkov, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> bits so that DSC would work there as well
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 02da9ecf71f1..49659165cea8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
> #define CTL_DEFAULT_GROUP_ID 0xf
> @@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> -
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> ctx->pending_merge_3d_flush_mask);
> @@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> + if (cfg->dsc)
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> +
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> mode_sel |= BIT(17);
>
> @@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + if (cfg->dsc) {
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> + }
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 806c171e5df2..9847c9c46d6f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> * @merge_3d: 3d merge block used
> * @intf_mode_sel: Interface mode, cmd / vid
> * @stream_sel: Stream selection for multi-stream interfaces
> + * @dsc: DSC BIT masks
> */
> struct dpu_hw_intf_cfg {
> enum dpu_intf intf;
> @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
> enum dpu_merge_3d merge_3d;
> enum dpu_ctl_mode_sel intf_mode_sel;
> int stream_sel;
> + unsigned int dsc;
> };
>
> /**
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
@ 2022-02-16 19:52 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:52 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> bits so that DSC would work there as well
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 02da9ecf71f1..49659165cea8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
> #define CTL_DEFAULT_GROUP_ID 0xf
> @@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> -
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> ctx->pending_merge_3d_flush_mask);
> @@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> + if (cfg->dsc)
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> +
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> mode_sel |= BIT(17);
>
> @@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + if (cfg->dsc) {
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> + }
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 806c171e5df2..9847c9c46d6f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> * @merge_3d: 3d merge block used
> * @intf_mode_sel: Interface mode, cmd / vid
> * @stream_sel: Stream selection for multi-stream interfaces
> + * @dsc: DSC BIT masks
> */
> struct dpu_hw_intf_cfg {
> enum dpu_intf intf;
> @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
> enum dpu_merge_3d merge_3d;
> enum dpu_ctl_mode_sel intf_mode_sel;
> int stream_sel;
> + unsigned int dsc;
> };
>
> /**
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-16 19:54 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:54 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Daniel Vetter,
Dmitry Baryshkov, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Minor nit below, with that
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
This looks slightly misaligned to me or not sure if its my mail client.
Please check it once.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-16 19:54 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-16 19:54 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Minor nit below, with that
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
This looks slightly misaligned to me or not sure if its my mail client.
Please check it once.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 0:27 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 0:27 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
@ 2022-02-17 0:27 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 0:27 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:11 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:11 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> We cannot enable mode_3d when we are using the DSC. So pass
> configuration to detect DSC is enabled and not enable mode_3d
> when we are using DSC
>
> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> enabled and pass this to .setup_intf_cfg()
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
We should not use 3D mux only when we use DSC merge topology.
I agree that today we use only 2-2-1 topology for DSC which means its
using DSC merge.
But generalizing that 3D mux should not be used for DSC is not right.
You can detect DSC merge by checking if there are two encoders and one
interface in the topology and if so, you can disable 3D mux.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 34a6940d12c5..ed37a4c21596 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
> intf_cfg.stream_sel = cmd_enc->stream_sel;
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ddd9d89cd456..218009855fca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
> intf_cfg.stream_sel = 0; /* Don't care value for video mode */
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> if (phys_enc->hw_pp->merge_3d)
> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 49659165cea8..6d5268b7da90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
>
> intf_cfg |= (cfg->intf & 0xF) << 4;
>
> - if (cfg->mode_3d) {
> + /* In DSC we can't set merge, so check for dsc and complain */
> + if (cfg->mode_3d && cfg->dsc)
> + pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
> +
> + /* set merge only when dsc is not set */
> + if (cfg->mode_3d && !cfg->dsc) {
> intf_cfg |= BIT(19);
> intf_cfg |= (cfg->mode_3d - 0x1) << 20;
> }
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-17 3:11 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:11 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> We cannot enable mode_3d when we are using the DSC. So pass
> configuration to detect DSC is enabled and not enable mode_3d
> when we are using DSC
>
> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> enabled and pass this to .setup_intf_cfg()
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
We should not use 3D mux only when we use DSC merge topology.
I agree that today we use only 2-2-1 topology for DSC which means its
using DSC merge.
But generalizing that 3D mux should not be used for DSC is not right.
You can detect DSC merge by checking if there are two encoders and one
interface in the topology and if so, you can disable 3D mux.
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 4 ++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 7 ++++++-
> 3 files changed, 14 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> index 34a6940d12c5..ed37a4c21596 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
> @@ -70,6 +70,10 @@ static void _dpu_encoder_phys_cmd_update_intf_cfg(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_CMD;
> intf_cfg.stream_sel = cmd_enc->stream_sel;
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> ctl->ops.setup_intf_cfg(ctl, &intf_cfg);
> }
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> index ddd9d89cd456..218009855fca 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
> @@ -284,6 +284,10 @@ static void dpu_encoder_phys_vid_setup_timing_engine(
> intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID;
> intf_cfg.stream_sel = 0; /* Don't care value for video mode */
> intf_cfg.mode_3d = dpu_encoder_helper_get_3d_blend_mode(phys_enc);
> + intf_cfg.dsc = dpu_encoder_helper_get_dsc(phys_enc);
> + if (intf_cfg.dsc)
> + intf_cfg.mode_3d = 0;
> +
> if (phys_enc->hw_pp->merge_3d)
> intf_cfg.merge_3d = phys_enc->hw_pp->merge_3d->idx;
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 49659165cea8..6d5268b7da90 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -536,7 +536,12 @@ static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
>
> intf_cfg |= (cfg->intf & 0xF) << 4;
>
> - if (cfg->mode_3d) {
> + /* In DSC we can't set merge, so check for dsc and complain */
> + if (cfg->mode_3d && cfg->dsc)
> + pr_err("DPU1: DSC and Merge 3D both are set!! it may not work\n");
> +
> + /* set merge only when dsc is not set */
> + if (cfg->mode_3d && !cfg->dsc) {
> intf_cfg |= BIT(19);
> intf_cfg |= (cfg->mode_3d - 0x1) << 20;
> }
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:12 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:12 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
@ 2022-02-17 3:12 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:12 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:14 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:14 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This add the bits in RM to enable the DSC blocks
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> --Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 2d385b4b7f5e..8f2fb667b05c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -146,6 +146,7 @@ struct dpu_global_state {
> uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
> uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
> uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
> + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
> };
>
> struct dpu_global_state
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index f9c83d6e427a..fbb24bb2b998 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -11,6 +11,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_dspp.h"
> #include "dpu_hw_merge3d.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_encoder.h"
> #include "dpu_trace.h"
>
> @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> dpu_hw_intf_destroy(hw);
> }
> }
> + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
> + struct dpu_hw_dsc *hw;
> +
> + if (rm->dsc_blks[i]) {
> + hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
> + dpu_hw_dsc_destroy(hw);
> + }
> + }
>
> return 0;
> }
> @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->dsc_count; i++) {
> + struct dpu_hw_dsc *hw;
> + const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
> +
> + hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
> + if (IS_ERR_OR_NULL(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed dsc object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> + }
> +
> return 0;
>
> fail:
> @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
> }
>
> global_state->intf_to_enc_id[idx] = enc_id;
> +
> return 0;
> }
>
> @@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
> return ret;
> }
>
> +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
> + struct dpu_global_state *global_state,
> + struct drm_encoder *enc,
> + const struct msm_display_topology *top)
> +{
> + int num_dsc = top->num_dsc;
> + int i;
> +
> + /* check if DSC required are allocated or not */
> + for (i = 0; i < num_dsc; i++) {
> + if (global_state->dsc_to_enc_id[i]) {
> + DPU_ERROR("DSC %d is already allocated\n", i);
> + return -EIO;
> + }
> + }
> +
> + for (i = 0; i < num_dsc; i++)
> + global_state->dsc_to_enc_id[i] = enc->base.id;
> +
> + return 0;
> +}
> +
> static int _dpu_rm_make_reservation(
> struct dpu_rm *rm,
> struct dpu_global_state *global_state,
> @@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
> if (ret)
> return ret;
>
> + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
> + if (ret)
> + return ret;
> +
> return ret;
> }
>
> @@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
> ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
> _dpu_rm_clear_mapping(global_state->intf_to_enc_id,
> ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
> + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
> + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
> }
>
> int dpu_rm_reserve(
> @@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
> hw_to_enc_id = global_state->dspp_to_enc_id;
> max_blks = ARRAY_SIZE(rm->dspp_blks);
> break;
> + case DPU_HW_BLK_DSC:
> + hw_blks = rm->dsc_blks;
> + hw_to_enc_id = global_state->dsc_to_enc_id;
> + max_blks = ARRAY_SIZE(rm->dsc_blks);
> + break;
> default:
> DPU_ERROR("blk type %d not managed by rm\n", type);
> return 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 1f12c8d5b8aa..278d2a510b80 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -30,6 +30,7 @@ struct dpu_rm {
> struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>
> uint32_t lm_max_width;
> };
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
@ 2022-02-17 3:14 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:14 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This add the bits in RM to enable the DSC blocks
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> --Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 2d385b4b7f5e..8f2fb667b05c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -146,6 +146,7 @@ struct dpu_global_state {
> uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
> uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
> uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
> + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
> };
>
> struct dpu_global_state
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index f9c83d6e427a..fbb24bb2b998 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -11,6 +11,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_dspp.h"
> #include "dpu_hw_merge3d.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_encoder.h"
> #include "dpu_trace.h"
>
> @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> dpu_hw_intf_destroy(hw);
> }
> }
> + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
> + struct dpu_hw_dsc *hw;
> +
> + if (rm->dsc_blks[i]) {
> + hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
> + dpu_hw_dsc_destroy(hw);
> + }
> + }
>
> return 0;
> }
> @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->dsc_count; i++) {
> + struct dpu_hw_dsc *hw;
> + const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
> +
> + hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
> + if (IS_ERR_OR_NULL(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed dsc object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> + }
> +
> return 0;
>
> fail:
> @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
> }
>
> global_state->intf_to_enc_id[idx] = enc_id;
> +
> return 0;
> }
>
> @@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
> return ret;
> }
>
> +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
> + struct dpu_global_state *global_state,
> + struct drm_encoder *enc,
> + const struct msm_display_topology *top)
> +{
> + int num_dsc = top->num_dsc;
> + int i;
> +
> + /* check if DSC required are allocated or not */
> + for (i = 0; i < num_dsc; i++) {
> + if (global_state->dsc_to_enc_id[i]) {
> + DPU_ERROR("DSC %d is already allocated\n", i);
> + return -EIO;
> + }
> + }
> +
> + for (i = 0; i < num_dsc; i++)
> + global_state->dsc_to_enc_id[i] = enc->base.id;
> +
> + return 0;
> +}
> +
> static int _dpu_rm_make_reservation(
> struct dpu_rm *rm,
> struct dpu_global_state *global_state,
> @@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
> if (ret)
> return ret;
>
> + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
> + if (ret)
> + return ret;
> +
> return ret;
> }
>
> @@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
> ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
> _dpu_rm_clear_mapping(global_state->intf_to_enc_id,
> ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
> + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
> + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
> }
>
> int dpu_rm_reserve(
> @@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
> hw_to_enc_id = global_state->dspp_to_enc_id;
> max_blks = ARRAY_SIZE(rm->dspp_blks);
> break;
> + case DPU_HW_BLK_DSC:
> + hw_blks = rm->dsc_blks;
> + hw_to_enc_id = global_state->dsc_to_enc_id;
> + max_blks = ARRAY_SIZE(rm->dsc_blks);
> + break;
> default:
> DPU_ERROR("blk type %d not managed by rm\n", type);
> return 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 1f12c8d5b8aa..278d2a510b80 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -30,6 +30,7 @@ struct dpu_rm {
> struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>
> uint32_t lm_max_width;
> };
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:17 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:17 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Add a mode valid callback for dsi_mgr for checking mode being valid in
> case of DSC. For DSC the height and width needs to be multiple of slice,
> so we check that here
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 26 ++++++++++++++++++++++++++
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ++++++++++++
> 3 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 16cd9b2fce86..580a1e6358bf 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -114,6 +114,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
> int msm_dsi_host_power_off(struct mipi_dsi_host *host);
> int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
> const struct drm_display_mode *mode);
> +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> + const struct drm_display_mode *mode);
> struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host);
> unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host);
> struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7e9913eff724..438c80750682 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2552,6 +2552,32 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
> return 0;
> }
>
> +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> + const struct drm_display_mode *mode)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + int pic_width = mode->hdisplay;
> + int pic_height = mode->vdisplay;
> +
> + if (!msm_host->dsc)
> + return MODE_OK;
> +
> + if (pic_width % dsc->drm->slice_width) {
> + pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
> + pic_width, dsc->drm->slice_width);
> + return MODE_H_ILLEGAL;
> + }
> +
> + if (pic_height % dsc->drm->slice_height) {
> + pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
> + pic_height, dsc->drm->slice_height);
> + return MODE_V_ILLEGAL;
> + }
> +
> + return MODE_OK;
> +}
> +
> struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
> {
> return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index f19bae475c96..e7f6cc88f7a4 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -575,6 +575,17 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
> msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
> }
>
> +static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_info *info,
> + const struct drm_display_mode *mode)
> +{
> + int id = dsi_mgr_bridge_get_id(bridge);
> + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
> + struct mipi_dsi_host *host = msm_dsi->host;
> +
> + return msm_dsi_host_check_dsc(host, mode);
> +}
> +
> static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
> .detect = dsi_mgr_connector_detect,
> .fill_modes = drm_helper_probe_single_connector_modes,
> @@ -596,6 +607,7 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
> .disable = dsi_mgr_bridge_disable,
> .post_disable = dsi_mgr_bridge_post_disable,
> .mode_set = dsi_mgr_bridge_mode_set,
> + .mode_valid = dsi_mgr_bridge_mode_valid,
> };
>
> /* initialize connector when we're connected to a drm_panel */
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr
@ 2022-02-17 3:17 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:17 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Add a mode valid callback for dsi_mgr for checking mode being valid in
> case of DSC. For DSC the height and width needs to be multiple of slice,
> so we check that here
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi.h | 2 ++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 26 ++++++++++++++++++++++++++
> drivers/gpu/drm/msm/dsi/dsi_manager.c | 12 ++++++++++++
> 3 files changed, 40 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index 16cd9b2fce86..580a1e6358bf 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -114,6 +114,8 @@ int msm_dsi_host_power_on(struct mipi_dsi_host *host,
> int msm_dsi_host_power_off(struct mipi_dsi_host *host);
> int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
> const struct drm_display_mode *mode);
> +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> + const struct drm_display_mode *mode);
> struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host);
> unsigned long msm_dsi_host_get_mode_flags(struct mipi_dsi_host *host);
> struct drm_bridge *msm_dsi_host_get_bridge(struct mipi_dsi_host *host);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 7e9913eff724..438c80750682 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2552,6 +2552,32 @@ int msm_dsi_host_set_display_mode(struct mipi_dsi_host *host,
> return 0;
> }
>
> +enum drm_mode_status msm_dsi_host_check_dsc(struct mipi_dsi_host *host,
> + const struct drm_display_mode *mode)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + int pic_width = mode->hdisplay;
> + int pic_height = mode->vdisplay;
> +
> + if (!msm_host->dsc)
> + return MODE_OK;
> +
> + if (pic_width % dsc->drm->slice_width) {
> + pr_err("DSI: pic_width %d has to be multiple of slice %d\n",
> + pic_width, dsc->drm->slice_width);
> + return MODE_H_ILLEGAL;
> + }
> +
> + if (pic_height % dsc->drm->slice_height) {
> + pr_err("DSI: pic_height %d has to be multiple of slice %d\n",
> + pic_height, dsc->drm->slice_height);
> + return MODE_V_ILLEGAL;
> + }
> +
> + return MODE_OK;
> +}
> +
> struct drm_panel *msm_dsi_host_get_panel(struct mipi_dsi_host *host)
> {
> return of_drm_find_panel(to_msm_dsi_host(host)->device_node);
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> index f19bae475c96..e7f6cc88f7a4 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c
> @@ -575,6 +575,17 @@ static void dsi_mgr_bridge_mode_set(struct drm_bridge *bridge,
> msm_dsi_host_set_display_mode(other_dsi->host, adjusted_mode);
> }
>
> +static enum drm_mode_status dsi_mgr_bridge_mode_valid(struct drm_bridge *bridge,
> + const struct drm_display_info *info,
> + const struct drm_display_mode *mode)
> +{
> + int id = dsi_mgr_bridge_get_id(bridge);
> + struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id);
> + struct mipi_dsi_host *host = msm_dsi->host;
> +
> + return msm_dsi_host_check_dsc(host, mode);
> +}
> +
> static const struct drm_connector_funcs dsi_mgr_connector_funcs = {
> .detect = dsi_mgr_connector_detect,
> .fill_modes = drm_helper_probe_single_connector_modes,
> @@ -596,6 +607,7 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = {
> .disable = dsi_mgr_bridge_disable,
> .post_disable = dsi_mgr_bridge_post_disable,
> .mode_set = dsi_mgr_bridge_mode_set,
> + .mode_valid = dsi_mgr_bridge_mode_valid,
> };
>
> /* initialize connector when we're connected to a drm_panel */
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:21 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:21 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This add the bits in RM to enable the DSC blocks
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 2d385b4b7f5e..8f2fb667b05c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -146,6 +146,7 @@ struct dpu_global_state {
> uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
> uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
> uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
> + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
> };
>
> struct dpu_global_state
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index f9c83d6e427a..fbb24bb2b998 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -11,6 +11,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_dspp.h"
> #include "dpu_hw_merge3d.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_encoder.h"
> #include "dpu_trace.h"
>
> @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> dpu_hw_intf_destroy(hw);
> }
> }
> + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
> + struct dpu_hw_dsc *hw;
> +
> + if (rm->dsc_blks[i]) {
> + hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
> + dpu_hw_dsc_destroy(hw);
> + }
> + }
>
> return 0;
> }
> @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->dsc_count; i++) {
> + struct dpu_hw_dsc *hw;
> + const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
> +
> + hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
> + if (IS_ERR_OR_NULL(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed dsc object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> + }
> +
> return 0;
>
> fail:
> @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
> }
>
> global_state->intf_to_enc_id[idx] = enc_id;
> +
> return 0;
> }
>
> @@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
> return ret;
> }
>
> +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
> + struct dpu_global_state *global_state,
> + struct drm_encoder *enc,
> + const struct msm_display_topology *top)
> +{
> + int num_dsc = top->num_dsc;
> + int i;
> +
> + /* check if DSC required are allocated or not */
> + for (i = 0; i < num_dsc; i++) {
> + if (global_state->dsc_to_enc_id[i]) {
> + DPU_ERROR("DSC %d is already allocated\n", i);
> + return -EIO;
> + }
> + }
> +
> + for (i = 0; i < num_dsc; i++)
> + global_state->dsc_to_enc_id[i] = enc->base.id;
> +
> + return 0;
> +}
> +
> static int _dpu_rm_make_reservation(
> struct dpu_rm *rm,
> struct dpu_global_state *global_state,
> @@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
> if (ret)
> return ret;
>
> + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
> + if (ret)
> + return ret;
> +
> return ret;
> }
>
> @@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
> ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
> _dpu_rm_clear_mapping(global_state->intf_to_enc_id,
> ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
> + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
> + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
> }
>
> int dpu_rm_reserve(
> @@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
> hw_to_enc_id = global_state->dspp_to_enc_id;
> max_blks = ARRAY_SIZE(rm->dspp_blks);
> break;
> + case DPU_HW_BLK_DSC:
> + hw_blks = rm->dsc_blks;
> + hw_to_enc_id = global_state->dsc_to_enc_id;
> + max_blks = ARRAY_SIZE(rm->dsc_blks);
> + break;
> default:
> DPU_ERROR("blk type %d not managed by rm\n", type);
> return 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 1f12c8d5b8aa..278d2a510b80 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -30,6 +30,7 @@ struct dpu_rm {
> struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>
> uint32_t lm_max_width;
> };
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM
@ 2022-02-17 3:21 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:21 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> This add the bits in RM to enable the DSC blocks
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h | 1 +
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 56 +++++++++++++++++++++++++
> drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 1 +
> 3 files changed, 58 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> index 2d385b4b7f5e..8f2fb667b05c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h
> @@ -146,6 +146,7 @@ struct dpu_global_state {
> uint32_t ctl_to_enc_id[CTL_MAX - CTL_0];
> uint32_t intf_to_enc_id[INTF_MAX - INTF_0];
> uint32_t dspp_to_enc_id[DSPP_MAX - DSPP_0];
> + uint32_t dsc_to_enc_id[DSC_MAX - DSC_0];
> };
>
> struct dpu_global_state
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> index f9c83d6e427a..fbb24bb2b998 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
> @@ -11,6 +11,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_dspp.h"
> #include "dpu_hw_merge3d.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_encoder.h"
> #include "dpu_trace.h"
>
> @@ -75,6 +76,14 @@ int dpu_rm_destroy(struct dpu_rm *rm)
> dpu_hw_intf_destroy(hw);
> }
> }
> + for (i = 0; i < ARRAY_SIZE(rm->dsc_blks); i++) {
> + struct dpu_hw_dsc *hw;
> +
> + if (rm->dsc_blks[i]) {
> + hw = to_dpu_hw_dsc(rm->dsc_blks[i]);
> + dpu_hw_dsc_destroy(hw);
> + }
> + }
>
> return 0;
> }
> @@ -221,6 +230,19 @@ int dpu_rm_init(struct dpu_rm *rm,
> rm->dspp_blks[dspp->id - DSPP_0] = &hw->base;
> }
>
> + for (i = 0; i < cat->dsc_count; i++) {
> + struct dpu_hw_dsc *hw;
> + const struct dpu_dsc_cfg *dsc = &cat->dsc[i];
> +
> + hw = dpu_hw_dsc_init(dsc->id, mmio, cat);
> + if (IS_ERR_OR_NULL(hw)) {
> + rc = PTR_ERR(hw);
> + DPU_ERROR("failed dsc object creation: err %d\n", rc);
> + goto fail;
> + }
> + rm->dsc_blks[dsc->id - DSC_0] = &hw->base;
> + }
> +
> return 0;
>
> fail:
> @@ -476,6 +498,7 @@ static int _dpu_rm_reserve_intf(
> }
>
> global_state->intf_to_enc_id[idx] = enc_id;
> +
> return 0;
> }
>
> @@ -500,6 +523,28 @@ static int _dpu_rm_reserve_intf_related_hw(
> return ret;
> }
>
> +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm,
> + struct dpu_global_state *global_state,
> + struct drm_encoder *enc,
> + const struct msm_display_topology *top)
> +{
> + int num_dsc = top->num_dsc;
> + int i;
> +
> + /* check if DSC required are allocated or not */
> + for (i = 0; i < num_dsc; i++) {
> + if (global_state->dsc_to_enc_id[i]) {
> + DPU_ERROR("DSC %d is already allocated\n", i);
> + return -EIO;
> + }
> + }
> +
> + for (i = 0; i < num_dsc; i++)
> + global_state->dsc_to_enc_id[i] = enc->base.id;
> +
> + return 0;
> +}
> +
> static int _dpu_rm_make_reservation(
> struct dpu_rm *rm,
> struct dpu_global_state *global_state,
> @@ -526,6 +571,10 @@ static int _dpu_rm_make_reservation(
> if (ret)
> return ret;
>
> + ret = _dpu_rm_reserve_dsc(rm, global_state, enc, &reqs->topology);
> + if (ret)
> + return ret;
> +
> return ret;
> }
>
> @@ -567,6 +616,8 @@ void dpu_rm_release(struct dpu_global_state *global_state,
> ARRAY_SIZE(global_state->ctl_to_enc_id), enc->base.id);
> _dpu_rm_clear_mapping(global_state->intf_to_enc_id,
> ARRAY_SIZE(global_state->intf_to_enc_id), enc->base.id);
> + _dpu_rm_clear_mapping(global_state->dsc_to_enc_id,
> + ARRAY_SIZE(global_state->dsc_to_enc_id), enc->base.id);
> }
>
> int dpu_rm_reserve(
> @@ -640,6 +691,11 @@ int dpu_rm_get_assigned_resources(struct dpu_rm *rm,
> hw_to_enc_id = global_state->dspp_to_enc_id;
> max_blks = ARRAY_SIZE(rm->dspp_blks);
> break;
> + case DPU_HW_BLK_DSC:
> + hw_blks = rm->dsc_blks;
> + hw_to_enc_id = global_state->dsc_to_enc_id;
> + max_blks = ARRAY_SIZE(rm->dsc_blks);
> + break;
> default:
> DPU_ERROR("blk type %d not managed by rm\n", type);
> return 0;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> index 1f12c8d5b8aa..278d2a510b80 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
> @@ -30,6 +30,7 @@ struct dpu_rm {
> struct dpu_hw_blk *intf_blks[INTF_MAX - INTF_0];
> struct dpu_hw_blk *dspp_blks[DSPP_MAX - DSPP_0];
> struct dpu_hw_blk *merge_3d_blks[MERGE_3D_MAX - MERGE_3D_0];
> + struct dpu_hw_blk *dsc_blks[DSC_MAX - DSC_0];
>
> uint32_t lm_max_width;
> };
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 3:44 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:44 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Daniel Vetter,
Dmitry Baryshkov, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
This file should not be edited manually. The updates have to be
generated using the headergen tool.
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
Why is this hard-coded to 1 here? Am i missing something?
I think I need another day to look into these calculations.
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-17 3:44 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 3:44 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
This file should not be edited manually. The updates have to be
generated using the headergen tool.
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
Why is this hard-coded to 1 here? Am i missing something?
I think I need another day to look into these calculations.
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
2022-02-16 19:46 ` Dmitry Baryshkov
@ 2022-02-17 4:20 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 4:20 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Abhinav Kumar, Rob Clark, Jonathan Marek, David Airlie,
linux-arm-msm, linux-kernel, Abhinav Kumar, Bjorn Andersson,
dri-devel, freedreno
On 16-02-22, 22:46, Dmitry Baryshkov wrote:
> On 16/02/2022 21:57, Abhinav Kumar wrote:
> >
> >
> > On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > > Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
> > > support by adding hw blocks for DSC
> > >
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> >
> > Somehow second patch of this series is not showing up on patchwork in
> > your REPOST.
> >
> > It jumps from 1 to 3.
>
> patch 2: https://patchwork.freedesktop.org/patch/473356/?series=99959&rev=1
yeah it seems to be there.. As well os arm-msm and dri-devel on k.org
pw....Problem with QC delivery...?
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC
@ 2022-02-17 4:20 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 4:20 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Jonathan Marek, David Airlie, linux-arm-msm, Abhinav Kumar,
Abhinav Kumar, linux-kernel, dri-devel, Bjorn Andersson,
freedreno
On 16-02-22, 22:46, Dmitry Baryshkov wrote:
> On 16/02/2022 21:57, Abhinav Kumar wrote:
> >
> >
> > On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > > Display Stream Compression (DSC) is one of the hw blocks in dpu, so add
> > > support by adding hw blocks for DSC
> > >
> > > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> >
> > Somehow second patch of this series is not showing up on patchwork in
> > your REPOST.
> >
> > It jumps from 1 to 3.
>
> patch 2: https://patchwork.freedesktop.org/patch/473356/?series=99959&rev=1
yeah it seems to be there.. As well os arm-msm and dri-devel on k.org
pw....Problem with QC delivery...?
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
2022-02-16 19:49 ` Abhinav Kumar
@ 2022-02-17 4:21 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 4:21 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 16-02-22, 11:49, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > In SDM845, DSC can be enabled by writing to pingpong block registers, so
> > add support for DSC in hw_pp
> >
> > Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>
> For the sake of uniformity, please use
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
This one has been carry fwd from few versions back :) will update
everywhere...
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block
@ 2022-02-17 4:21 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 4:21 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 16-02-22, 11:49, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > In SDM845, DSC can be enabled by writing to pingpong block registers, so
> > add support for DSC in hw_pp
> >
> > Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
>
> For the sake of uniformity, please use
>
> Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
This one has been carry fwd from few versions back :) will update
everywhere...
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-16 19:54 ` Abhinav Kumar
@ 2022-02-17 6:08 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:08 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Jonathan Marek, David Airlie, linux-arm-msm,
linux-kernel, Abhinav Kumar, Bjorn Andersson, dri-devel,
Daniel Vetter, Dmitry Baryshkov, freedreno
On 16-02-22, 11:54, Abhinav Kumar wrote:
> > +/**
> > + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> > + * This helper function is used by physical encoder to get DSC blocks mask
> > + * used for this encoder.
>
> This looks slightly misaligned to me or not sure if its my mail client.
> Please check it once.
This looks fine in code as well as in mutt for me.. Maybe client issue
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-17 6:08 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:08 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 16-02-22, 11:54, Abhinav Kumar wrote:
> > +/**
> > + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> > + * This helper function is used by physical encoder to get DSC blocks mask
> > + * used for this encoder.
>
> This looks slightly misaligned to me or not sure if its my mail client.
> Please check it once.
This looks fine in code as well as in mutt for me.. Maybe client issue
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-17 3:11 ` Abhinav Kumar
@ 2022-02-17 6:10 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:10 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 16-02-22, 19:11, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > We cannot enable mode_3d when we are using the DSC. So pass
> > configuration to detect DSC is enabled and not enable mode_3d
> > when we are using DSC
> >
> > We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> > enabled and pass this to .setup_intf_cfg()
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> We should not use 3D mux only when we use DSC merge topology.
> I agree that today we use only 2-2-1 topology for DSC which means its using
> DSC merge.
>
> But generalizing that 3D mux should not be used for DSC is not right.
>
> You can detect DSC merge by checking if there are two encoders and one
> interface in the topology and if so, you can disable 3D mux.
Right now with DSC we disable that as suggested by Dmitry last time.
Whenever we introduce merge we should revisit this, for now this should
suffice
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-17 6:10 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:10 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 16-02-22, 19:11, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > We cannot enable mode_3d when we are using the DSC. So pass
> > configuration to detect DSC is enabled and not enable mode_3d
> > when we are using DSC
> >
> > We add a helper dpu_encoder_helper_get_dsc() to detect dsc
> > enabled and pass this to .setup_intf_cfg()
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> We should not use 3D mux only when we use DSC merge topology.
> I agree that today we use only 2-2-1 topology for DSC which means its using
> DSC merge.
>
> But generalizing that 3D mux should not be used for DSC is not right.
>
> You can detect DSC merge by checking if there are two encoders and one
> interface in the topology and if so, you can disable 3D mux.
Right now with DSC we disable that as suggested by Dmitry last time.
Whenever we introduce merge we should revisit this, for now this should
suffice
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-17 3:44 ` Abhinav Kumar
@ 2022-02-17 6:19 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:19 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Rob Clark, Jonathan Marek, David Airlie, linux-arm-msm,
linux-kernel, Abhinav Kumar, Bjorn Andersson, dri-devel,
Daniel Vetter, Dmitry Baryshkov, freedreno
On 16-02-22, 19:44, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> > 2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > index 49b551ad1bff..c1c85df58c4b 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> > +
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> > +
>
> This file should not be edited manually. The updates have to be generated
> using the headergen tool.
I have already send mesa patch for that. https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14967#note_1253974
You should chime in there as well :)
I will split these and get these generated one as a separate patch..
>
> > #endif /* DSI_XML */
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index 438c80750682..3d8d5a1daaa3 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> > }
> > +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> > + int pic_width, int pic_height)
> > +{
> > + if (!dsc || !pic_width || !pic_height) {
> > + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> > + return -EINVAL;
> > + }
> > +
> > + dsc->drm->pic_width = pic_width;
> > + dsc->drm->pic_height = pic_height;
> > +
> > + return 0;
> > +}
> > +
> > static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > {
> > struct drm_display_mode *mode = msm_host->mode;
> > @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > hdisplay /= 2;
> > }
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > +
> > + /* update dsc params with timing params */
> > + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> > + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> > +
> > + /* we do the calculations for dsc parameters here so that
> > + * panel can use these parameters
> > + */
> > + dsi_populate_dsc_params(dsc);
> > +
> > + /* Divide the display by 3 but keep back/font porch and
> > + * pulse width same
> > + */
> > + h_total -= hdisplay;
> > + hdisplay /= 3;
> > + h_total += hdisplay;
> > + ha_end = ha_start + hdisplay;
> > + }
> > +
> > if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, intf_width, slice_per_intf;
> > + u32 total_bytes_per_intf;
> > +
> > + /* first calculate dsc parameters and then program
> > + * compress mode registers
> > + */
> > + intf_width = hdisplay;
> > + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> > +
> > + dsc->drm->slice_count = 1;
>
> Why is this hard-coded to 1 here? Am i missing something?
> I think I need another day to look into these calculations.
Thanks for spotting this, it should be:
dsc->drm->slice_count = DIV_ROUND_UP(intf_width, dsc->drm->slice_widths);
which is slice_per_intf so I will update this
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-17 6:19 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 6:19 UTC (permalink / raw)
To: Abhinav Kumar
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 16-02-22, 19:44, Abhinav Kumar wrote:
>
>
> On 2/10/2022 2:34 AM, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> > 2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > index 49b551ad1bff..c1c85df58c4b 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> > +
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> > +
>
> This file should not be edited manually. The updates have to be generated
> using the headergen tool.
I have already send mesa patch for that. https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14967#note_1253974
You should chime in there as well :)
I will split these and get these generated one as a separate patch..
>
> > #endif /* DSI_XML */
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index 438c80750682..3d8d5a1daaa3 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> > }
> > +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> > + int pic_width, int pic_height)
> > +{
> > + if (!dsc || !pic_width || !pic_height) {
> > + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> > + return -EINVAL;
> > + }
> > +
> > + dsc->drm->pic_width = pic_width;
> > + dsc->drm->pic_height = pic_height;
> > +
> > + return 0;
> > +}
> > +
> > static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > {
> > struct drm_display_mode *mode = msm_host->mode;
> > @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > hdisplay /= 2;
> > }
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > +
> > + /* update dsc params with timing params */
> > + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> > + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> > +
> > + /* we do the calculations for dsc parameters here so that
> > + * panel can use these parameters
> > + */
> > + dsi_populate_dsc_params(dsc);
> > +
> > + /* Divide the display by 3 but keep back/font porch and
> > + * pulse width same
> > + */
> > + h_total -= hdisplay;
> > + hdisplay /= 3;
> > + h_total += hdisplay;
> > + ha_end = ha_start + hdisplay;
> > + }
> > +
> > if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, intf_width, slice_per_intf;
> > + u32 total_bytes_per_intf;
> > +
> > + /* first calculate dsc parameters and then program
> > + * compress mode registers
> > + */
> > + intf_width = hdisplay;
> > + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> > +
> > + dsc->drm->slice_count = 1;
>
> Why is this hard-coded to 1 here? Am i missing something?
> I think I need another day to look into these calculations.
Thanks for spotting this, it should be:
dsc->drm->slice_count = DIV_ROUND_UP(intf_width, dsc->drm->slice_widths);
which is slice_per_intf so I will update this
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-17 6:10 ` Vinod Koul
@ 2022-02-17 6:33 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 6:33 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 2/16/2022 10:10 PM, Vinod Koul wrote:
> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>
>>
>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>> We cannot enable mode_3d when we are using the DSC. So pass
>>> configuration to detect DSC is enabled and not enable mode_3d
>>> when we are using DSC
>>>
>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>> enabled and pass this to .setup_intf_cfg()
>>>
>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>
>> We should not use 3D mux only when we use DSC merge topology.
>> I agree that today we use only 2-2-1 topology for DSC which means its using
>> DSC merge.
>>
>> But generalizing that 3D mux should not be used for DSC is not right.
>>
>> You can detect DSC merge by checking if there are two encoders and one
>> interface in the topology and if so, you can disable 3D mux.
>
> Right now with DSC we disable that as suggested by Dmitry last time.
> Whenever we introduce merge we should revisit this, for now this should
> suffice
>
Sorry I didnt follow.
The topology which you are supporting today IS DSC merge 2-2-1. I didnt
get what you mean by "whenever we introduce".
I didnt follow Dmitry's comment either.
"anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle
this."
3D mux shouldnt be used when DSC merge is used.
The topology Dmitry is referring to will not use DSC merge but you are
using it here and thats why you had to make this patch in the first
place. So I am not sure why would someone who uses 3D merge topology
worry about DSC merge. Your patch is the one which deals with the
topology in question.
What I am suggesting is a small but necessary improvement to this patch.
All that you have to do is in query whether DSC merge is used from the
topology. You can do it in multiple ways:
1) Either query this from the encoder
2) Store a bool "dsc_merge" in the intf_cfg
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-17 6:33 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 6:33 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/16/2022 10:10 PM, Vinod Koul wrote:
> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>
>>
>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>> We cannot enable mode_3d when we are using the DSC. So pass
>>> configuration to detect DSC is enabled and not enable mode_3d
>>> when we are using DSC
>>>
>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>> enabled and pass this to .setup_intf_cfg()
>>>
>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>
>> We should not use 3D mux only when we use DSC merge topology.
>> I agree that today we use only 2-2-1 topology for DSC which means its using
>> DSC merge.
>>
>> But generalizing that 3D mux should not be used for DSC is not right.
>>
>> You can detect DSC merge by checking if there are two encoders and one
>> interface in the topology and if so, you can disable 3D mux.
>
> Right now with DSC we disable that as suggested by Dmitry last time.
> Whenever we introduce merge we should revisit this, for now this should
> suffice
>
Sorry I didnt follow.
The topology which you are supporting today IS DSC merge 2-2-1. I didnt
get what you mean by "whenever we introduce".
I didnt follow Dmitry's comment either.
"anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle
this."
3D mux shouldnt be used when DSC merge is used.
The topology Dmitry is referring to will not use DSC merge but you are
using it here and thats why you had to make this patch in the first
place. So I am not sure why would someone who uses 3D merge topology
worry about DSC merge. Your patch is the one which deals with the
topology in question.
What I am suggesting is a small but necessary improvement to this patch.
All that you have to do is in query whether DSC merge is used from the
topology. You can do it in multiple ways:
1) Either query this from the encoder
2) Store a bool "dsc_merge" in the intf_cfg
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-17 6:33 ` Abhinav Kumar
@ 2022-02-17 7:12 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-17 7:12 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 17/02/2022 09:33, Abhinav Kumar wrote:
>
>
> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>> when we are using DSC
>>>>
>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>> enabled and pass this to .setup_intf_cfg()
>>>>
>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>
>>> We should not use 3D mux only when we use DSC merge topology.
>>> I agree that today we use only 2-2-1 topology for DSC which means its
>>> using
>>> DSC merge.
>>>
>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>
>>> You can detect DSC merge by checking if there are two encoders and one
>>> interface in the topology and if so, you can disable 3D mux.
>>
>> Right now with DSC we disable that as suggested by Dmitry last time.
>> Whenever we introduce merge we should revisit this, for now this should
>> suffice
>>
>
> Sorry I didnt follow.
>
> The topology which you are supporting today IS DSC merge 2-2-1. I didnt
> get what you mean by "whenever we introduce".
>
> I didnt follow Dmitry's comment either.
>
> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle
> this."
>
> 3D mux shouldnt be used when DSC merge is used.
>
> The topology Dmitry is referring to will not use DSC merge but you are
> using it here and thats why you had to make this patch in the first
> place. So I am not sure why would someone who uses 3D merge topology
> worry about DSC merge. Your patch is the one which deals with the
> topology in question.
>
> What I am suggesting is a small but necessary improvement to this patch.
It seems that we can replace this patch by changing
dpu_encoder_helper_get_3d_blend_mode() to contain the following
condition (instead of the one present there). Does the following seem
correct to you:
static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
struct dpu_encoder_phys *phys_enc)
{
struct dpu_crtc_state *dpu_cstate;
if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
return BLEND_3D_NONE;
dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
+ /* Use merge_3d unless DSCMERGE topology is used */
if (phys_enc->split_role == ENC_ROLE_SOLO &&
+ hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
return BLEND_3D_H_ROW_INT;
return BLEND_3D_NONE;
}
>
> All that you have to do is in query whether DSC merge is used from the
> topology. You can do it in multiple ways:
>
> 1) Either query this from the encoder
> 2) Store a bool "dsc_merge" in the intf_cfg
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-17 7:12 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-17 7:12 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 17/02/2022 09:33, Abhinav Kumar wrote:
>
>
> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>> when we are using DSC
>>>>
>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>> enabled and pass this to .setup_intf_cfg()
>>>>
>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>
>>> We should not use 3D mux only when we use DSC merge topology.
>>> I agree that today we use only 2-2-1 topology for DSC which means its
>>> using
>>> DSC merge.
>>>
>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>
>>> You can detect DSC merge by checking if there are two encoders and one
>>> interface in the topology and if so, you can disable 3D mux.
>>
>> Right now with DSC we disable that as suggested by Dmitry last time.
>> Whenever we introduce merge we should revisit this, for now this should
>> suffice
>>
>
> Sorry I didnt follow.
>
> The topology which you are supporting today IS DSC merge 2-2-1. I didnt
> get what you mean by "whenever we introduce".
>
> I didnt follow Dmitry's comment either.
>
> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC handle
> this."
>
> 3D mux shouldnt be used when DSC merge is used.
>
> The topology Dmitry is referring to will not use DSC merge but you are
> using it here and thats why you had to make this patch in the first
> place. So I am not sure why would someone who uses 3D merge topology
> worry about DSC merge. Your patch is the one which deals with the
> topology in question.
>
> What I am suggesting is a small but necessary improvement to this patch.
It seems that we can replace this patch by changing
dpu_encoder_helper_get_3d_blend_mode() to contain the following
condition (instead of the one present there). Does the following seem
correct to you:
static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
struct dpu_encoder_phys *phys_enc)
{
struct dpu_crtc_state *dpu_cstate;
if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
return BLEND_3D_NONE;
dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
+ /* Use merge_3d unless DSCMERGE topology is used */
if (phys_enc->split_role == ENC_ROLE_SOLO &&
+ hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
return BLEND_3D_H_ROW_INT;
return BLEND_3D_NONE;
}
>
> All that you have to do is in query whether DSC merge is used from the
> topology. You can do it in multiple ways:
>
> 1) Either query this from the encoder
> 2) Store a bool "dsc_merge" in the intf_cfg
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 9:27 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 9:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Vinod,
On 2022-02-10 16:04:23, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
I supplied a rather extensive - yet merely scratching the surface -
review of this patch in:
https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
It seems none of those points have been addressed, bar creating a mesa
MR to update dsi.xml with a subpar description of the registers (offsets
only).
For every point that is intentionally ignored, please at least supply a
justification of why you think this is the right thing to do.
Thanks,
- Marijn
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-17 9:27 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 9:27 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
Vinod,
On 2022-02-10 16:04:23, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
I supplied a rather extensive - yet merely scratching the surface -
review of this patch in:
https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
It seems none of those points have been addressed, bar creating a mesa
MR to update dsi.xml with a subpar description of the registers (offsets
only).
For every point that is intentionally ignored, please at least supply a
justification of why you think this is the right thing to do.
Thanks,
- Marijn
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-17 9:27 ` Marijn Suijten
@ 2022-02-17 10:51 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 10:51 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Rob Clark, dri-devel,
Daniel Vetter, Dmitry Baryshkov, freedreno
Hi Marijn,
On 17-02-22, 10:27, Marijn Suijten wrote:
> Vinod,
>
> On 2022-02-10 16:04:23, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> I supplied a rather extensive - yet merely scratching the surface -
> review of this patch in:
>
> https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
Sorry somehow I seem to have overlooked this one.
>
> It seems none of those points have been addressed, bar creating a mesa
> MR to update dsi.xml with a subpar description of the registers (offsets
> only).
Mesa MR was planned as we get more closer to having reviews.
> For every point that is intentionally ignored, please at least supply a
> justification of why you think this is the right thing to do.
Ofcourse, i will reply to these now and address as required.
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-17 10:51 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-02-17 10:51 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
Hi Marijn,
On 17-02-22, 10:27, Marijn Suijten wrote:
> Vinod,
>
> On 2022-02-10 16:04:23, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> I supplied a rather extensive - yet merely scratching the surface -
> review of this patch in:
>
> https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
Sorry somehow I seem to have overlooked this one.
>
> It seems none of those points have been addressed, bar creating a mesa
> MR to update dsi.xml with a subpar description of the registers (offsets
> only).
Mesa MR was planned as we get more closer to having reviews.
> For every point that is intentionally ignored, please at least supply a
> justification of why you think this is the right thing to do.
Ofcourse, i will reply to these now and address as required.
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-17 10:51 ` Vinod Koul
@ 2022-02-17 14:38 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 14:38 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Rob Clark, dri-devel,
Daniel Vetter, Dmitry Baryshkov, freedreno
Hi Vinod,
On 2022-02-17 16:21:35, Vinod Koul wrote:
> Hi Marijn,
>
> On 17-02-22, 10:27, Marijn Suijten wrote:
> > Vinod,
> >
> > On 2022-02-10 16:04:23, Vinod Koul wrote:
> > > When DSC is enabled, we need to configure DSI registers accordingly and
> > > configure the respective stream compression registers.
> > >
> > > Add support to calculate the register setting based on DSC params and
> > > timing information and configure these registers.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> >
> > I supplied a rather extensive - yet merely scratching the surface -
> > review of this patch in:
> >
> > https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
>
> Sorry somehow I seem to have overlooked this one.
Glad to hear it was only just missed, hope it helps making these patches
truly a step-up from the downstream driver it was based on :)
> >
> > It seems none of those points have been addressed, bar creating a mesa
> > MR to update dsi.xml with a subpar description of the registers (offsets
> > only).
>
> Mesa MR was planned as we get more closer to having reviews.
I would have submitted them in parallel straight away and link them
together, so that review can commence immediately on both. Perhaps then
the XML could be merged up-front so that these patches don't need to
block on a stable commit-hash to regenerate the headers from?
In this case I/we would have immediately requested to move all the
register constants and offsets (even those that currently have an
unknown meaning) into the XML, and we can later fill in the details.
> > For every point that is intentionally ignored, please at least supply a
> > justification of why you think this is the right thing to do.
>
> Ofcourse, i will reply to these now and address as required.
Thanks, I'll try to clarify some points ASAP before you respin this.
- Marijn
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-17 14:38 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 14:38 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
Hi Vinod,
On 2022-02-17 16:21:35, Vinod Koul wrote:
> Hi Marijn,
>
> On 17-02-22, 10:27, Marijn Suijten wrote:
> > Vinod,
> >
> > On 2022-02-10 16:04:23, Vinod Koul wrote:
> > > When DSC is enabled, we need to configure DSI registers accordingly and
> > > configure the respective stream compression registers.
> > >
> > > Add support to calculate the register setting based on DSC params and
> > > timing information and configure these registers.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> >
> > I supplied a rather extensive - yet merely scratching the surface -
> > review of this patch in:
> >
> > https://lore.kernel.org/linux-arm-msm/20211211000315.pavmcc7cc73ilb6l@SoMainline.org/
>
> Sorry somehow I seem to have overlooked this one.
Glad to hear it was only just missed, hope it helps making these patches
truly a step-up from the downstream driver it was based on :)
> >
> > It seems none of those points have been addressed, bar creating a mesa
> > MR to update dsi.xml with a subpar description of the registers (offsets
> > only).
>
> Mesa MR was planned as we get more closer to having reviews.
I would have submitted them in parallel straight away and link them
together, so that review can commence immediately on both. Perhaps then
the XML could be merged up-front so that these patches don't need to
block on a stable commit-hash to regenerate the headers from?
In this case I/we would have immediately requested to move all the
register constants and offsets (even those that currently have an
unknown meaning) into the XML, and we can later fill in the details.
> > For every point that is intentionally ignored, please at least supply a
> > justification of why you think this is the right thing to do.
>
> Ofcourse, i will reply to these now and address as required.
Thanks, I'll try to clarify some points ASAP before you respin this.
- Marijn
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 20:06 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 20:06 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
As we spoke during the sync up, since migration to the upstream API has
been agreed upon to be done later, this change LGTM. Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
@ 2022-02-17 20:06 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-17 20:06 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2/10/2022 2:34 AM, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
As we spoke during the sync up, since migration to the upstream API has
been agreed upon to be done later, this change LGTM. Hence,
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 21:44 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 21:44 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 2022-02-10 16:04:20, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
> + * 2 encoders, 2 line mixers and 1 interface
LM is a layer mixer, not a line mixer, right?
- Marijn
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-02-17 21:44 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 21:44 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2022-02-10 16:04:20, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
> + * 2 encoders, 2 line mixers and 1 interface
LM is a layer mixer, not a line mixer, right?
- Marijn
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 22:20 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:20 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 2022-02-10 16:04:16, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> bits so that DSC would work there as well
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 02da9ecf71f1..49659165cea8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
This define does not seem used in any of these patches. Is that
intended?
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
> #define CTL_DEFAULT_GROUP_ID 0xf
> @@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> -
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> ctx->pending_merge_3d_flush_mask);
> @@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> + if (cfg->dsc)
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> +
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> mode_sel |= BIT(17);
>
> @@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + if (cfg->dsc) {
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
Perhaps this should have been `DSC_IDX`, as the index to flush is set in
the CTL_DSC_FLUSH register already? Should this go through
pending_flush_mask machinery?
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> + }
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 806c171e5df2..9847c9c46d6f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> * @merge_3d: 3d merge block used
> * @intf_mode_sel: Interface mode, cmd / vid
> * @stream_sel: Stream selection for multi-stream interfaces
> + * @dsc: DSC BIT masks
Bit masks of what? Enabled DSCs? A more verbose doc-comment is desired
here, matching the rest of the fields :) - something like "DSC block(s)
used" similar to merge_3d? Or copy the docs from `dsc_mask`, which is
the value that is written into this field.
- Marijn
> */
> struct dpu_hw_intf_cfg {
> enum dpu_intf intf;
> @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
> enum dpu_merge_3d merge_3d;
> enum dpu_ctl_mode_sel intf_mode_sel;
> int stream_sel;
> + unsigned int dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
@ 2022-02-17 22:20 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:20 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2022-02-10 16:04:16, Vinod Koul wrote:
> Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> bits so that DSC would work there as well
>
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> 2 files changed, 12 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> index 02da9ecf71f1..49659165cea8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> @@ -25,6 +25,8 @@
> #define CTL_MERGE_3D_ACTIVE 0x0E4
> #define CTL_INTF_ACTIVE 0x0F4
> #define CTL_MERGE_3D_FLUSH 0x100
> +#define CTL_DSC_ACTIVE 0x0E8
> +#define CTL_DSC_FLUSH 0x104
> #define CTL_INTF_FLUSH 0x110
> #define CTL_INTF_MASTER 0x134
> #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> @@ -34,6 +36,7 @@
>
> #define DPU_REG_RESET_TIMEOUT_US 2000
> #define MERGE_3D_IDX 23
> +#define DSC_IDX 22
This define does not seem used in any of these patches. Is that
intended?
> #define INTF_IDX 31
> #define CTL_INVALID_BIT 0xffff
> #define CTL_DEFAULT_GROUP_ID 0xf
> @@ -121,7 +124,6 @@ static u32 dpu_hw_ctl_get_pending_flush(struct dpu_hw_ctl *ctx)
>
> static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx)
> {
> -
> if (ctx->pending_flush_mask & BIT(MERGE_3D_IDX))
> DPU_REG_WRITE(&ctx->hw, CTL_MERGE_3D_FLUSH,
> ctx->pending_merge_3d_flush_mask);
> @@ -506,6 +508,9 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if ((test_bit(DPU_CTL_VM_CFG, &ctx->caps->features)))
> mode_sel = CTL_DEFAULT_GROUP_ID << 28;
>
> + if (cfg->dsc)
> + DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, cfg->dsc);
> +
> if (cfg->intf_mode_sel == DPU_CTL_MODE_SEL_CMD)
> mode_sel |= BIT(17);
>
> @@ -517,6 +522,10 @@ static void dpu_hw_ctl_intf_cfg_v1(struct dpu_hw_ctl *ctx,
> if (cfg->merge_3d)
> DPU_REG_WRITE(c, CTL_MERGE_3D_ACTIVE,
> BIT(cfg->merge_3d - MERGE_3D_0));
> + if (cfg->dsc) {
> + DPU_REG_WRITE(&ctx->hw, CTL_FLUSH, cfg->dsc);
Perhaps this should have been `DSC_IDX`, as the index to flush is set in
the CTL_DSC_FLUSH register already? Should this go through
pending_flush_mask machinery?
> + DPU_REG_WRITE(c, CTL_DSC_ACTIVE, cfg->dsc);
> + }
> }
>
> static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> index 806c171e5df2..9847c9c46d6f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> * @merge_3d: 3d merge block used
> * @intf_mode_sel: Interface mode, cmd / vid
> * @stream_sel: Stream selection for multi-stream interfaces
> + * @dsc: DSC BIT masks
Bit masks of what? Enabled DSCs? A more verbose doc-comment is desired
here, matching the rest of the fields :) - something like "DSC block(s)
used" similar to merge_3d? Or copy the docs from `dsc_mask`, which is
the value that is written into this field.
- Marijn
> */
> struct dpu_hw_intf_cfg {
> enum dpu_intf intf;
> @@ -47,6 +48,7 @@ struct dpu_hw_intf_cfg {
> enum dpu_merge_3d merge_3d;
> enum dpu_ctl_mode_sel intf_mode_sel;
> int stream_sel;
> + unsigned int dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 22:32 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:32 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 2022-02-10 16:04:17, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
No need for "^The" prefix here.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
Perhaps move this definition outside the if, and unconditionally
perform:
dpu_enc->dsc_mask = dsc_mask;
Below the if, instead of having to write it twice when ->dsc is truthy?
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
Perhaps you can merge these loops? Assuming hw_dsc is already
NULL-initialized, you only need to iterate to `i<num_dsc` once without
extra conditional anyway?
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
What's the forward slash for?
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
I've seen the same calculations duplicated twice in dsi code. Since the
msm_display_dsc_config struct is available in a header, perhaps a single
- easily reviewable and maintainable - calculation function should be
available there too?
- Marijn
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-17 22:32 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:32 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2022-02-10 16:04:17, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
No need for "^The" prefix here.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
Perhaps move this definition outside the if, and unconditionally
perform:
dpu_enc->dsc_mask = dsc_mask;
Below the if, instead of having to write it twice when ->dsc is truthy?
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
Perhaps you can merge these loops? Assuming hw_dsc is already
NULL-initialized, you only need to iterate to `i<num_dsc` once without
extra conditional anyway?
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
What's the forward slash for?
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
> +}
I've seen the same calculations duplicated twice in dsi code. Since the
msm_display_dsc_config struct is available in a header, perhaps a single
- easily reviewable and maintainable - calculation function should be
available there too?
- Marijn
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 22:34 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:34 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
Replace "missing structure" with "missing num_dspp field" in the title?
On 2022-02-10 16:04:19, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation
@ 2022-02-17 22:34 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:34 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
Replace "missing structure" with "missing num_dspp field" in the title?
On 2022-02-10 16:04:19, Vinod Koul wrote:
> Somehow documentation for dspp was missed, so add that
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/msm_drv.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index e7a312edfe67..6425a42e997c 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -102,6 +102,7 @@ enum msm_event_wait {
> * @num_lm: number of layer mixers used
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> + * @num_dspp: number of dspp blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-17 22:37 ` Marijn Suijten
-1 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:37 UTC (permalink / raw)
To: Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 2022-02-10 16:04:20, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
Just like elsewhere, since you wrote out Display Stream Compression,
write the "DSC" abbreviation between parentheses ()?
- Marijn
> + * 2 encoders, 2 line mixers and 1 interface
+ 2 DSC "blocks"?
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-02-17 22:37 ` Marijn Suijten
0 siblings, 0 replies; 127+ messages in thread
From: Marijn Suijten @ 2022-02-17 22:37 UTC (permalink / raw)
To: Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 2022-02-10 16:04:20, Vinod Koul wrote:
> For DSC to work we typically need a 2,2,1 configuration. This should
> suffice for resolutions up to 4k. For more resolutions like 8k this won't
> work.
>
> Also, it is better to use 2 LMs and DSC instances as half width results
> in lesser power consumption as compared to single LM, DSC at full width.
>
> The panel has been tested only with 2,2,1 configuration, so for
> now we blindly create 2,2,1 topology when DSC is enabled
>
> Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 2 ++
> 2 files changed, 15 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 95a7bf362e81..13ccb7b3cce5 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> topology.num_enc = 0;
> topology.num_intf = intf_count;
>
> + if (dpu_enc->dsc) {
> + /* In case of Display Stream Compression DSC, we would use
Just like elsewhere, since you wrote out Display Stream Compression,
write the "DSC" abbreviation between parentheses ()?
- Marijn
> + * 2 encoders, 2 line mixers and 1 interface
+ 2 DSC "blocks"?
> + * this is power optimal and can drive up to (including) 4k
> + * screens
> + */
> + topology.num_enc = 2;
> + topology.num_dsc = 2;
> + topology.num_intf = 1;
> + topology.num_lm = 2;
> + }
> +
> return topology;
> }
> +
> static int dpu_encoder_virt_atomic_check(
> struct drm_encoder *drm_enc,
> struct drm_crtc_state *crtc_state,
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 6425a42e997c..994d895d1a47 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -103,12 +103,14 @@ enum msm_event_wait {
> * @num_enc: number of compression encoder blocks used
> * @num_intf: number of interfaces the panel is mounted on
> * @num_dspp: number of dspp blocks used
> + * @num_dsc: number of Display Stream Compression (DSC) blocks used
> */
> struct msm_display_topology {
> u32 num_lm;
> u32 num_enc;
> u32 num_intf;
> u32 num_dspp;
> + u32 num_dsc;
> };
>
> /**
> --
> 2.31.1
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-17 7:12 ` Dmitry Baryshkov
@ 2022-02-18 20:46 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-18 20:46 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>
>>
>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>> when we are using DSC
>>>>>
>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>
>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>
>>>> We should not use 3D mux only when we use DSC merge topology.
>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>> its using
>>>> DSC merge.
>>>>
>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>
>>>> You can detect DSC merge by checking if there are two encoders and one
>>>> interface in the topology and if so, you can disable 3D mux.
>>>
>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>> Whenever we introduce merge we should revisit this, for now this should
>>> suffice
>>>
>>
>> Sorry I didnt follow.
>>
>> The topology which you are supporting today IS DSC merge 2-2-1. I
>> didnt get what you mean by "whenever we introduce".
>>
>> I didnt follow Dmitry's comment either.
>>
>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>> handle this."
>>
>> 3D mux shouldnt be used when DSC merge is used.
>>
>> The topology Dmitry is referring to will not use DSC merge but you are
>> using it here and thats why you had to make this patch in the first
>> place. So I am not sure why would someone who uses 3D merge topology
>> worry about DSC merge. Your patch is the one which deals with the
>> topology in question.
>>
>> What I am suggesting is a small but necessary improvement to this patch.
>
> It seems that we can replace this patch by changing
> dpu_encoder_helper_get_3d_blend_mode() to contain the following
> condition (instead of the one present there). Does the following seem
> correct to you:
>
> static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> struct dpu_encoder_phys *phys_enc)
> {
> struct dpu_crtc_state *dpu_cstate;
>
> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
> return BLEND_3D_NONE;
>
> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>
> + /* Use merge_3d unless DSCMERGE topology is used */
> if (phys_enc->split_role == ENC_ROLE_SOLO &&
> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
> return BLEND_3D_H_ROW_INT;
>
> return BLEND_3D_NONE;
> }
This will not be enough. To detect whether DSC merge is enabled you need
to query the topology. The above condition only checks if DSC is enabled
not DSC merge.
So the above function can be modified to use a helper like below instead
of the hweight.
bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
{
struct msm_display_topology topology = {0};
topology = dpu_encoder_get_topology(...);
if (topology.num_dsc > topology.num_intf)
return true;
else
return false;
}
if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
return BLEND_3D_H_ROW_INT;
else
BLEND_3D_NONE;
>
>
>>
>> All that you have to do is in query whether DSC merge is used from the
>> topology. You can do it in multiple ways:
>>
>> 1) Either query this from the encoder
>> 2) Store a bool "dsc_merge" in the intf_cfg
>>
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-18 20:46 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-18 20:46 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>
>>
>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>> when we are using DSC
>>>>>
>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>
>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>
>>>> We should not use 3D mux only when we use DSC merge topology.
>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>> its using
>>>> DSC merge.
>>>>
>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>
>>>> You can detect DSC merge by checking if there are two encoders and one
>>>> interface in the topology and if so, you can disable 3D mux.
>>>
>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>> Whenever we introduce merge we should revisit this, for now this should
>>> suffice
>>>
>>
>> Sorry I didnt follow.
>>
>> The topology which you are supporting today IS DSC merge 2-2-1. I
>> didnt get what you mean by "whenever we introduce".
>>
>> I didnt follow Dmitry's comment either.
>>
>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>> handle this."
>>
>> 3D mux shouldnt be used when DSC merge is used.
>>
>> The topology Dmitry is referring to will not use DSC merge but you are
>> using it here and thats why you had to make this patch in the first
>> place. So I am not sure why would someone who uses 3D merge topology
>> worry about DSC merge. Your patch is the one which deals with the
>> topology in question.
>>
>> What I am suggesting is a small but necessary improvement to this patch.
>
> It seems that we can replace this patch by changing
> dpu_encoder_helper_get_3d_blend_mode() to contain the following
> condition (instead of the one present there). Does the following seem
> correct to you:
>
> static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> struct dpu_encoder_phys *phys_enc)
> {
> struct dpu_crtc_state *dpu_cstate;
>
> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
> return BLEND_3D_NONE;
>
> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>
> + /* Use merge_3d unless DSCMERGE topology is used */
> if (phys_enc->split_role == ENC_ROLE_SOLO &&
> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
> return BLEND_3D_H_ROW_INT;
>
> return BLEND_3D_NONE;
> }
This will not be enough. To detect whether DSC merge is enabled you need
to query the topology. The above condition only checks if DSC is enabled
not DSC merge.
So the above function can be modified to use a helper like below instead
of the hweight.
bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
{
struct msm_display_topology topology = {0};
topology = dpu_encoder_get_topology(...);
if (topology.num_dsc > topology.num_intf)
return true;
else
return false;
}
if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
return BLEND_3D_H_ROW_INT;
else
BLEND_3D_NONE;
>
>
>>
>> All that you have to do is in query whether DSC merge is used from the
>> topology. You can do it in multiple ways:
>>
>> 1) Either query this from the encoder
>> 2) Store a bool "dsc_merge" in the intf_cfg
>>
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-18 20:46 ` Abhinav Kumar
@ 2022-02-18 21:21 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-18 21:21 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 18/02/2022 23:46, Abhinav Kumar wrote:
>
>
> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>
>>>>>
>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>> when we are using DSC
>>>>>>
>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>
>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>
>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>> its using
>>>>> DSC merge.
>>>>>
>>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>>
>>>>> You can detect DSC merge by checking if there are two encoders and one
>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>
>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>> Whenever we introduce merge we should revisit this, for now this should
>>>> suffice
>>>>
>>>
>>> Sorry I didnt follow.
>>>
>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>> didnt get what you mean by "whenever we introduce".
>>>
>>> I didnt follow Dmitry's comment either.
>>>
>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>> handle this."
>>>
>>> 3D mux shouldnt be used when DSC merge is used.
>>>
>>> The topology Dmitry is referring to will not use DSC merge but you
>>> are using it here and thats why you had to make this patch in the
>>> first place. So I am not sure why would someone who uses 3D merge
>>> topology worry about DSC merge. Your patch is the one which deals
>>> with the topology in question.
>>>
>>> What I am suggesting is a small but necessary improvement to this patch.
>>
>> It seems that we can replace this patch by changing
>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>> condition (instead of the one present there). Does the following seem
>> correct to you:
>>
>> static inline enum dpu_3d_blend_mode
>> dpu_encoder_helper_get_3d_blend_mode(
>> struct dpu_encoder_phys *phys_enc)
>> {
>> struct dpu_crtc_state *dpu_cstate;
>>
>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>> return BLEND_3D_NONE;
>>
>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>
>> + /* Use merge_3d unless DSCMERGE topology is used */
>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
Yes, the correct should be:
hweight(...) == 2
>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>> return BLEND_3D_H_ROW_INT;
>>
>> return BLEND_3D_NONE;
>> }
>
> This will not be enough. To detect whether DSC merge is enabled you need
> to query the topology. The above condition only checks if DSC is enabled
> not DSC merge.
>
> So the above function can be modified to use a helper like below instead
> of the hweight.
>
> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
> {
> struct msm_display_topology topology = {0};
>
> topology = dpu_encoder_get_topology(...);
>
> if (topology.num_dsc > topology.num_intf)
num_intf is 1 or 2. If it's one, the split_role is SOLO
hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
So, if the split_role is SOLO and hweight is 2, we get exactly your
condition.
Does that sound correct?
> return true;
> else
> return false;
> }
>
> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
> return BLEND_3D_H_ROW_INT;
> else
> BLEND_3D_NONE;
>>
>>
>>>
>>> All that you have to do is in query whether DSC merge is used from
>>> the topology. You can do it in multiple ways:
>>>
>>> 1) Either query this from the encoder
>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-18 21:21 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-18 21:21 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 18/02/2022 23:46, Abhinav Kumar wrote:
>
>
> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>
>>>>>
>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>> when we are using DSC
>>>>>>
>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>
>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>
>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>> its using
>>>>> DSC merge.
>>>>>
>>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>>
>>>>> You can detect DSC merge by checking if there are two encoders and one
>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>
>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>> Whenever we introduce merge we should revisit this, for now this should
>>>> suffice
>>>>
>>>
>>> Sorry I didnt follow.
>>>
>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>> didnt get what you mean by "whenever we introduce".
>>>
>>> I didnt follow Dmitry's comment either.
>>>
>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>> handle this."
>>>
>>> 3D mux shouldnt be used when DSC merge is used.
>>>
>>> The topology Dmitry is referring to will not use DSC merge but you
>>> are using it here and thats why you had to make this patch in the
>>> first place. So I am not sure why would someone who uses 3D merge
>>> topology worry about DSC merge. Your patch is the one which deals
>>> with the topology in question.
>>>
>>> What I am suggesting is a small but necessary improvement to this patch.
>>
>> It seems that we can replace this patch by changing
>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>> condition (instead of the one present there). Does the following seem
>> correct to you:
>>
>> static inline enum dpu_3d_blend_mode
>> dpu_encoder_helper_get_3d_blend_mode(
>> struct dpu_encoder_phys *phys_enc)
>> {
>> struct dpu_crtc_state *dpu_cstate;
>>
>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>> return BLEND_3D_NONE;
>>
>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>
>> + /* Use merge_3d unless DSCMERGE topology is used */
>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
Yes, the correct should be:
hweight(...) == 2
>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>> return BLEND_3D_H_ROW_INT;
>>
>> return BLEND_3D_NONE;
>> }
>
> This will not be enough. To detect whether DSC merge is enabled you need
> to query the topology. The above condition only checks if DSC is enabled
> not DSC merge.
>
> So the above function can be modified to use a helper like below instead
> of the hweight.
>
> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
> {
> struct msm_display_topology topology = {0};
>
> topology = dpu_encoder_get_topology(...);
>
> if (topology.num_dsc > topology.num_intf)
num_intf is 1 or 2. If it's one, the split_role is SOLO
hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
So, if the split_role is SOLO and hweight is 2, we get exactly your
condition.
Does that sound correct?
> return true;
> else
> return false;
> }
>
> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
> return BLEND_3D_H_ROW_INT;
> else
> BLEND_3D_NONE;
>>
>>
>>>
>>> All that you have to do is in query whether DSC merge is used from
>>> the topology. You can do it in multiple ways:
>>>
>>> 1) Either query this from the encoder
>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-18 21:21 ` Dmitry Baryshkov
@ 2022-02-18 21:29 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-18 21:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Rob Clark, dri-devel,
Daniel Vetter, freedreno
On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
> On 18/02/2022 23:46, Abhinav Kumar wrote:
>>
>>
>> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>>
>>>>>>
>>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>>> when we are using DSC
>>>>>>>
>>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>>
>>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>>
>>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>>> its using
>>>>>> DSC merge.
>>>>>>
>>>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>>>
>>>>>> You can detect DSC merge by checking if there are two encoders and
>>>>>> one
>>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>>
>>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>>> Whenever we introduce merge we should revisit this, for now this
>>>>> should
>>>>> suffice
>>>>>
>>>>
>>>> Sorry I didnt follow.
>>>>
>>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>>> didnt get what you mean by "whenever we introduce".
>>>>
>>>> I didnt follow Dmitry's comment either.
>>>>
>>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>>> handle this."
>>>>
>>>> 3D mux shouldnt be used when DSC merge is used.
>>>>
>>>> The topology Dmitry is referring to will not use DSC merge but you
>>>> are using it here and thats why you had to make this patch in the
>>>> first place. So I am not sure why would someone who uses 3D merge
>>>> topology worry about DSC merge. Your patch is the one which deals
>>>> with the topology in question.
>>>>
>>>> What I am suggesting is a small but necessary improvement to this
>>>> patch.
>>>
>>> It seems that we can replace this patch by changing
>>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>>> condition (instead of the one present there). Does the following seem
>>> correct to you:
>>>
>>> static inline enum dpu_3d_blend_mode
>>> dpu_encoder_helper_get_3d_blend_mode(
>>> struct dpu_encoder_phys *phys_enc)
>>> {
>>> struct dpu_crtc_state *dpu_cstate;
>>>
>>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>> return BLEND_3D_NONE;
>>>
>>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>>
>>> + /* Use merge_3d unless DSCMERGE topology is used */
>>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
>
> Yes, the correct should be:
> hweight(...) == 2
>
>>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>>> return BLEND_3D_H_ROW_INT;
>>>
>>> return BLEND_3D_NONE;
>>> }
>>
>> This will not be enough. To detect whether DSC merge is enabled you
>> need to query the topology. The above condition only checks if DSC is
>> enabled not DSC merge.
>>
>> So the above function can be modified to use a helper like below
>> instead of the hweight.
>>
>> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
>> {
>> struct msm_display_topology topology = {0};
>>
>> topology = dpu_encoder_get_topology(...);
>>
>> if (topology.num_dsc > topology.num_intf)
>
> num_intf is 1 or 2. If it's one, the split_role is SOLO
> hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
> So, if the split_role is SOLO and hweight is 2, we get exactly your
> condition.
>
num_intf is 1 in this case as only single interface is used. But even 4
dsc encoders going to 2 interfaces its DSC merge. So assuming num_intf
as 1 always is not right. Thats why I suggested a generalized confition
like above.
> Does that sound correct?
>
>> return true;
>> else
>> return false;
>> }
>>
>> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
>> return BLEND_3D_H_ROW_INT;
>> else
>> BLEND_3D_NONE;
>>>
>>>
>>>>
>>>> All that you have to do is in query whether DSC merge is used from
>>>> the topology. You can do it in multiple ways:
>>>>
>>>> 1) Either query this from the encoder
>>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>>
>>>
>>>
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-18 21:29 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-02-18 21:29 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
> On 18/02/2022 23:46, Abhinav Kumar wrote:
>>
>>
>> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>>
>>>>
>>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>>
>>>>>>
>>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>>> when we are using DSC
>>>>>>>
>>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>>
>>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>>
>>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>>> its using
>>>>>> DSC merge.
>>>>>>
>>>>>> But generalizing that 3D mux should not be used for DSC is not right.
>>>>>>
>>>>>> You can detect DSC merge by checking if there are two encoders and
>>>>>> one
>>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>>
>>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>>> Whenever we introduce merge we should revisit this, for now this
>>>>> should
>>>>> suffice
>>>>>
>>>>
>>>> Sorry I didnt follow.
>>>>
>>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>>> didnt get what you mean by "whenever we introduce".
>>>>
>>>> I didnt follow Dmitry's comment either.
>>>>
>>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>>> handle this."
>>>>
>>>> 3D mux shouldnt be used when DSC merge is used.
>>>>
>>>> The topology Dmitry is referring to will not use DSC merge but you
>>>> are using it here and thats why you had to make this patch in the
>>>> first place. So I am not sure why would someone who uses 3D merge
>>>> topology worry about DSC merge. Your patch is the one which deals
>>>> with the topology in question.
>>>>
>>>> What I am suggesting is a small but necessary improvement to this
>>>> patch.
>>>
>>> It seems that we can replace this patch by changing
>>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>>> condition (instead of the one present there). Does the following seem
>>> correct to you:
>>>
>>> static inline enum dpu_3d_blend_mode
>>> dpu_encoder_helper_get_3d_blend_mode(
>>> struct dpu_encoder_phys *phys_enc)
>>> {
>>> struct dpu_crtc_state *dpu_cstate;
>>>
>>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>> return BLEND_3D_NONE;
>>>
>>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>>
>>> + /* Use merge_3d unless DSCMERGE topology is used */
>>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
>
> Yes, the correct should be:
> hweight(...) == 2
>
>>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>>> return BLEND_3D_H_ROW_INT;
>>>
>>> return BLEND_3D_NONE;
>>> }
>>
>> This will not be enough. To detect whether DSC merge is enabled you
>> need to query the topology. The above condition only checks if DSC is
>> enabled not DSC merge.
>>
>> So the above function can be modified to use a helper like below
>> instead of the hweight.
>>
>> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
>> {
>> struct msm_display_topology topology = {0};
>>
>> topology = dpu_encoder_get_topology(...);
>>
>> if (topology.num_dsc > topology.num_intf)
>
> num_intf is 1 or 2. If it's one, the split_role is SOLO
> hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
> So, if the split_role is SOLO and hweight is 2, we get exactly your
> condition.
>
num_intf is 1 in this case as only single interface is used. But even 4
dsc encoders going to 2 interfaces its DSC merge. So assuming num_intf
as 1 always is not right. Thats why I suggested a generalized confition
like above.
> Does that sound correct?
>
>> return true;
>> else
>> return false;
>> }
>>
>> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
>> return BLEND_3D_H_ROW_INT;
>> else
>> BLEND_3D_NONE;
>>>
>>>
>>>>
>>>> All that you have to do is in query whether DSC merge is used from
>>>> the topology. You can do it in multiple ways:
>>>>
>>>> 1) Either query this from the encoder
>>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>>
>>>
>>>
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
2022-02-18 21:29 ` Abhinav Kumar
@ 2022-02-18 21:36 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-18 21:36 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Rob Clark, dri-devel,
Daniel Vetter, freedreno
On 19/02/2022 00:29, Abhinav Kumar wrote:
>
>
> On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
>> On 18/02/2022 23:46, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>>>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>>>
>>>>>
>>>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>>>> when we are using DSC
>>>>>>>>
>>>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>>>
>>>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>>>
>>>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>>>> its using
>>>>>>> DSC merge.
>>>>>>>
>>>>>>> But generalizing that 3D mux should not be used for DSC is not
>>>>>>> right.
>>>>>>>
>>>>>>> You can detect DSC merge by checking if there are two encoders
>>>>>>> and one
>>>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>>>
>>>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>>>> Whenever we introduce merge we should revisit this, for now this
>>>>>> should
>>>>>> suffice
>>>>>>
>>>>>
>>>>> Sorry I didnt follow.
>>>>>
>>>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>>>> didnt get what you mean by "whenever we introduce".
>>>>>
>>>>> I didnt follow Dmitry's comment either.
>>>>>
>>>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>>>> handle this."
>>>>>
>>>>> 3D mux shouldnt be used when DSC merge is used.
>>>>>
>>>>> The topology Dmitry is referring to will not use DSC merge but you
>>>>> are using it here and thats why you had to make this patch in the
>>>>> first place. So I am not sure why would someone who uses 3D merge
>>>>> topology worry about DSC merge. Your patch is the one which deals
>>>>> with the topology in question.
>>>>>
>>>>> What I am suggesting is a small but necessary improvement to this
>>>>> patch.
>>>>
>>>> It seems that we can replace this patch by changing
>>>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>>>> condition (instead of the one present there). Does the following
>>>> seem correct to you:
>>>>
>>>> static inline enum dpu_3d_blend_mode
>>>> dpu_encoder_helper_get_3d_blend_mode(
>>>> struct dpu_encoder_phys *phys_enc)
>>>> {
>>>> struct dpu_crtc_state *dpu_cstate;
>>>>
>>>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>>> return BLEND_3D_NONE;
>>>>
>>>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>>>
>>>> + /* Use merge_3d unless DSCMERGE topology is used */
>>>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>>>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
>>
>> Yes, the correct should be:
>> hweight(...) == 2
>>
>>>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>>>> return BLEND_3D_H_ROW_INT;
>>>>
>>>> return BLEND_3D_NONE;
>>>> }
>>>
>>> This will not be enough. To detect whether DSC merge is enabled you
>>> need to query the topology. The above condition only checks if DSC is
>>> enabled not DSC merge.
>>>
>>> So the above function can be modified to use a helper like below
>>> instead of the hweight.
>>>
>>> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
>>> {
>>> struct msm_display_topology topology = {0};
>>>
>>> topology = dpu_encoder_get_topology(...);
>>>
>>> if (topology.num_dsc > topology.num_intf)
>>
>> num_intf is 1 or 2. If it's one, the split_role is SOLO
>> hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
>> So, if the split_role is SOLO and hweight is 2, we get exactly your
>> condition.
>>
> num_intf is 1 in this case as only single interface is used. But even 4
> dsc encoders going to 2 interfaces its DSC merge. So assuming num_intf
> as 1 always is not right. Thats why I suggested a generalized confition
> like above.
Ah, quadpipe. Yes, then I was incorrect.
>
>> Does that sound correct?
>>
>>> return true;
>>> else
>>> return false;
>>> }
>>>
>>> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
>>> return BLEND_3D_H_ROW_INT;
>>> else
>>> BLEND_3D_NONE;
>>>>
>>>>
>>>>>
>>>>> All that you have to do is in query whether DSC merge is used from
>>>>> the topology. You can do it in multiple ways:
>>>>>
>>>>> 1) Either query this from the encoder
>>>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>>>
>>>>
>>>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d
@ 2022-02-18 21:36 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-18 21:36 UTC (permalink / raw)
To: Abhinav Kumar, Vinod Koul
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 19/02/2022 00:29, Abhinav Kumar wrote:
>
>
> On 2/18/2022 1:21 PM, Dmitry Baryshkov wrote:
>> On 18/02/2022 23:46, Abhinav Kumar wrote:
>>>
>>>
>>> On 2/16/2022 11:12 PM, Dmitry Baryshkov wrote:
>>>> On 17/02/2022 09:33, Abhinav Kumar wrote:
>>>>>
>>>>>
>>>>> On 2/16/2022 10:10 PM, Vinod Koul wrote:
>>>>>> On 16-02-22, 19:11, Abhinav Kumar wrote:
>>>>>>>
>>>>>>>
>>>>>>> On 2/10/2022 2:34 AM, Vinod Koul wrote:
>>>>>>>> We cannot enable mode_3d when we are using the DSC. So pass
>>>>>>>> configuration to detect DSC is enabled and not enable mode_3d
>>>>>>>> when we are using DSC
>>>>>>>>
>>>>>>>> We add a helper dpu_encoder_helper_get_dsc() to detect dsc
>>>>>>>> enabled and pass this to .setup_intf_cfg()
>>>>>>>>
>>>>>>>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>>>>>>>
>>>>>>> We should not use 3D mux only when we use DSC merge topology.
>>>>>>> I agree that today we use only 2-2-1 topology for DSC which means
>>>>>>> its using
>>>>>>> DSC merge.
>>>>>>>
>>>>>>> But generalizing that 3D mux should not be used for DSC is not
>>>>>>> right.
>>>>>>>
>>>>>>> You can detect DSC merge by checking if there are two encoders
>>>>>>> and one
>>>>>>> interface in the topology and if so, you can disable 3D mux.
>>>>>>
>>>>>> Right now with DSC we disable that as suggested by Dmitry last time.
>>>>>> Whenever we introduce merge we should revisit this, for now this
>>>>>> should
>>>>>> suffice
>>>>>>
>>>>>
>>>>> Sorry I didnt follow.
>>>>>
>>>>> The topology which you are supporting today IS DSC merge 2-2-1. I
>>>>> didnt get what you mean by "whenever we introduce".
>>>>>
>>>>> I didnt follow Dmitry's comment either.
>>>>>
>>>>> "anybody adding support for SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC
>>>>> handle this."
>>>>>
>>>>> 3D mux shouldnt be used when DSC merge is used.
>>>>>
>>>>> The topology Dmitry is referring to will not use DSC merge but you
>>>>> are using it here and thats why you had to make this patch in the
>>>>> first place. So I am not sure why would someone who uses 3D merge
>>>>> topology worry about DSC merge. Your patch is the one which deals
>>>>> with the topology in question.
>>>>>
>>>>> What I am suggesting is a small but necessary improvement to this
>>>>> patch.
>>>>
>>>> It seems that we can replace this patch by changing
>>>> dpu_encoder_helper_get_3d_blend_mode() to contain the following
>>>> condition (instead of the one present there). Does the following
>>>> seem correct to you:
>>>>
>>>> static inline enum dpu_3d_blend_mode
>>>> dpu_encoder_helper_get_3d_blend_mode(
>>>> struct dpu_encoder_phys *phys_enc)
>>>> {
>>>> struct dpu_crtc_state *dpu_cstate;
>>>>
>>>> if (!phys_enc || phys_enc->enable_state == DPU_ENC_DISABLING)
>>>> return BLEND_3D_NONE;
>>>>
>>>> dpu_cstate = to_dpu_crtc_state(phys_enc->parent->crtc->state);
>>>>
>>>> + /* Use merge_3d unless DSCMERGE topology is used */
>>>> if (phys_enc->split_role == ENC_ROLE_SOLO &&
>>>> + hweight(dpu_encoder_helper_get_dsc(phys_enc)) != 1 &&
>>
>> Yes, the correct should be:
>> hweight(...) == 2
>>
>>>> dpu_cstate->num_mixers == CRTC_DUAL_MIXERS)
>>>> return BLEND_3D_H_ROW_INT;
>>>>
>>>> return BLEND_3D_NONE;
>>>> }
>>>
>>> This will not be enough. To detect whether DSC merge is enabled you
>>> need to query the topology. The above condition only checks if DSC is
>>> enabled not DSC merge.
>>>
>>> So the above function can be modified to use a helper like below
>>> instead of the hweight.
>>>
>>> bool dpu_encoder_get_dsc_merge_info(struct dpu_encoder_virt *dpu_enc)
>>> {
>>> struct msm_display_topology topology = {0};
>>>
>>> topology = dpu_encoder_get_topology(...);
>>>
>>> if (topology.num_dsc > topology.num_intf)
>>
>> num_intf is 1 or 2. If it's one, the split_role is SOLO
>> hweight would return a num of bits in the DSC mask. It's 0, 1 or 2.
>> So, if the split_role is SOLO and hweight is 2, we get exactly your
>> condition.
>>
> num_intf is 1 in this case as only single interface is used. But even 4
> dsc encoders going to 2 interfaces its DSC merge. So assuming num_intf
> as 1 always is not right. Thats why I suggested a generalized confition
> like above.
Ah, quadpipe. Yes, then I was incorrect.
>
>> Does that sound correct?
>>
>>> return true;
>>> else
>>> return false;
>>> }
>>>
>>> if (!dpu_encoder_get_dsc_merge_info() && other conditions listed above)
>>> return BLEND_3D_H_ROW_INT;
>>> else
>>> BLEND_3D_NONE;
>>>>
>>>>
>>>>>
>>>>> All that you have to do is in query whether DSC merge is used from
>>>>> the topology. You can do it in multiple ways:
>>>>>
>>>>> 1) Either query this from the encoder
>>>>> 2) Store a bool "dsc_merge" in the intf_cfg
>>>>>
>>>>
>>>>
>>
>>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-21 1:41 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 1:41 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
I think these params are calculated again in dsi_timing_setup(), so we
can drop this function completely.
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-02-21 1:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 1:41 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> We need to configure the encoder for DSC configuration and calculate DSC
> parameters for the given timing so this patch adds that support by
> adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> 2 files changed, 171 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> index 1e648db439f9..95a7bf362e81 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> @@ -21,6 +21,7 @@
> #include "dpu_hw_intf.h"
> #include "dpu_hw_ctl.h"
> #include "dpu_hw_dspp.h"
> +#include "dpu_hw_dsc.h"
> #include "dpu_formats.h"
> #include "dpu_encoder_phys.h"
> #include "dpu_crtc.h"
> @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> * @cur_slave: As above but for the slave encoder.
> * @hw_pp: Handle to the pingpong blocks used for the display. No.
> * pingpong blocks can be different than num_phys_encs.
> + * @hw_dsc: Handle to the DSC blocks used for the display.
> + * @dsc_mask: The bitmask of used DSC blocks.
> * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> * for partial update right-only cases, such as pingpong
> * split where virtual pingpong does not generate IRQs
> @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> * @topology: topology of the display
> * @idle_timeout: idle timeout duration in milliseconds
> * @dp: msm_dp pointer, for DP encoders
> + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> */
> struct dpu_encoder_virt {
> struct drm_encoder base;
> @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> struct dpu_encoder_phys *cur_master;
> struct dpu_encoder_phys *cur_slave;
> struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> +
> + unsigned int dsc_mask;
>
> bool intfs_swapped;
>
> @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> u32 idle_timeout;
>
> struct msm_dp *dp;
> +
> + /* DSC configuration */
> + struct msm_display_dsc_config *dsc;
> };
>
> #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> - int num_lm, num_ctl, num_pp;
> + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> + int num_lm, num_ctl, num_pp, num_dsc;
> int i, j;
>
> if (!drm_enc) {
> @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> : NULL;
>
> + dpu_enc->dsc_mask = 0;
> +
> + if (dpu_enc->dsc) {
> + unsigned int dsc_mask = 0;
> +
> + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> + drm_enc->base.id, DPU_HW_BLK_DSC,
> + hw_dsc, ARRAY_SIZE(hw_dsc));
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> +
> + for (i = 0; i < num_dsc; i++)
> + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
> +
> + dpu_enc->dsc_mask = dsc_mask;
> + }
> +
> cstate = to_dpu_crtc_state(drm_crtc->state);
>
> for (i = 0; i < num_lm; i++) {
> @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> }
>
> +static void
> +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> +{
> + int slice_count, slice_per_intf;
> + int bytes_in_slice, total_bytes_per_intf;
> +
> + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> + DPU_ERROR("Invalid DSC/slices\n");
> + return;
> + }
> +
> + slice_count = dsc->drm->slice_count;
> + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> +
> + /*
> + * If slice_count is greater than slice_per_intf then default to 1.
> + * This can happen during partial update.
> + */
> + if (slice_count > slice_per_intf)
> + slice_count = 1;
> +
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_in_slice = bytes_in_slice;
> + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> + dsc->pkt_per_line = slice_per_intf / slice_count;
I think these params are calculated again in dsi_timing_setup(), so we
can drop this function completely.
> +}
> +
> +static void
> +dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_config *dsc,
> + u32 enc_ip_width)
> +{
> + int ssm_delay, total_pixels, soft_slice_per_enc;
> +
> + soft_slice_per_enc = enc_ip_width / dsc->drm->slice_width;
> +
> + /*
> + * minimum number of initial line pixels is a sum of:
> + * 1. sub-stream multiplexer delay (83 groups for 8bpc,
> + * 91 for 10 bpc) * 3
> + * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
> + * 3. the initial xmit delay
> + * 4. total pipeline delay through the "lock step" of encoder (47)
> + * 5. 6 additional pixels as the output of the rate buffer is
> + * 48 bits wide
> + */
> + ssm_delay = ((dsc->drm->bits_per_component < 10) ? 84 : 92);
> + total_pixels = ssm_delay * 3 + dsc->drm->initial_xmit_delay + 47;
> + if (soft_slice_per_enc > 1)
> + total_pixels += (ssm_delay * 3);
> + dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->drm->slice_width);
> +}
> +
> +static void dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
> + struct dpu_hw_pingpong *hw_pp,
> + struct msm_display_dsc_config *dsc,
> + u32 common_mode)
> +{
> + if (hw_dsc->ops.dsc_config)
> + hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode);
> +
> + if (hw_dsc->ops.dsc_config_thresh)
> + hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
> +
> + if (hw_pp->ops.setup_dsc)
> + hw_pp->ops.setup_dsc(hw_pp);
> +
> + if (hw_pp->ops.enable_dsc)
> + hw_pp->ops.enable_dsc(hw_pp);
> +}
> +
> +static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc,
> + struct msm_display_dsc_config *dsc)
> +{
> + /* coding only for 2LM, 2enc, 1 dsc config */
> + struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
> + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> + struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> + int this_frame_slices;
> + int intf_ip_w, enc_ip_w;
> + int dsc_common_mode;
> + int pic_width;
> + int i;
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
> + hw_pp[i] = dpu_enc->hw_pp[i];
> + hw_dsc[i] = dpu_enc->hw_dsc[i];
> +
> + if (!hw_pp[i] || !hw_dsc[i]) {
> + DPU_ERROR_ENC(dpu_enc, "invalid params for DSC\n");
> + return;
> + }
> + }
> +
> + dsc_common_mode = 0;
> + pic_width = dsc->drm->pic_width;
> +
> + dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
> + if (enc_master->intf_mode == INTF_MODE_VIDEO)
> + dsc_common_mode |= DSC_MODE_VIDEO;
> +
> + this_frame_slices = pic_width / dsc->drm->slice_width;
> + intf_ip_w = this_frame_slices * dsc->drm->slice_width;
> +
> + dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
> +
> + /*
> + * dsc merge case: when using 2 encoders for the same stream,
> + * no. of slices need to be same on both the encoders.
> + */
> + enc_ip_w = intf_ip_w / 2;
> + dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
> +
> + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> + dpu_encoder_dsc_pipe_cfg(hw_dsc[i], hw_pp[i], dsc, dsc_common_mode);
> +}
> +
> void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> {
> struct dpu_encoder_virt *dpu_enc;
> @@ -1770,6 +1919,9 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc)
> dpu_encoder_helper_hw_reset(dpu_enc->phys_encs[i]);
> }
> }
> +
> + if (dpu_enc->dsc)
> + dpu_encoder_prep_dsc(dpu_enc, dpu_enc->dsc);
> }
>
> void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
> @@ -2015,6 +2167,8 @@ static int dpu_encoder_setup_display(struct dpu_encoder_virt *dpu_enc,
> dpu_enc->idle_pc_supported =
> dpu_kms->catalog->caps->has_idle_pc;
>
> + dpu_enc->dsc = disp_info->dsc;
> +
> mutex_lock(&dpu_enc->enc_lock);
> for (i = 0; i < disp_info->num_of_h_tiles && !ret; i++) {
> /*
> @@ -2244,3 +2398,11 @@ enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder)
>
> return INTF_MODE_NONE;
> }
> +
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc)
> +{
> + struct drm_encoder *encoder = phys_enc->parent;
> + struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(encoder);
> +
> + return dpu_enc->dsc_mask;
> +}
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> index e7270eb6b84b..7b90d644a41b 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
> @@ -332,6 +332,14 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
> return BLEND_3D_NONE;
> }
>
> +/**
> + * dpu_encoder_helper_get_dsc - get DSC blocks mask for the DPU encoder
> + * This helper function is used by physical encoder to get DSC blocks mask
> + * used for this encoder.
> + * @phys_enc: Pointer to physical encoder structure
> + */
> +unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc);
> +
> /**
> * dpu_encoder_helper_split_config - split display configuration helper function
> * This helper function may be used by physical encoders to configure
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-21 2:11 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 2:11 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
Should we use dsc->bytes_in_slice or just bytes_in_slice here?
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-02-21 2:11 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 2:11 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to configure DSI registers accordingly and
> configure the respective stream compression registers.
>
> Add support to calculate the register setting based on DSC params and
> timing information and configure these registers.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> 2 files changed, 118 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> index 49b551ad1bff..c1c85df58c4b 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
>
>
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> +
> +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> +
> +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> +
> #endif /* DSI_XML */
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 438c80750682..3d8d5a1daaa3 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> }
>
> +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> + int pic_width, int pic_height)
> +{
> + if (!dsc || !pic_width || !pic_height) {
> + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> + return -EINVAL;
> + }
> +
> + dsc->drm->pic_width = pic_width;
> + dsc->drm->pic_height = pic_height;
> +
> + return 0;
> +}
> +
> static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> {
> struct drm_display_mode *mode = msm_host->mode;
> @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> hdisplay /= 2;
> }
>
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + /* update dsc params with timing params */
> + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> +
> + /* we do the calculations for dsc parameters here so that
> + * panel can use these parameters
> + */
> + dsi_populate_dsc_params(dsc);
> +
> + /* Divide the display by 3 but keep back/font porch and
> + * pulse width same
> + */
> + h_total -= hdisplay;
> + hdisplay /= 3;
> + h_total += hdisplay;
> + ha_end = ha_start + hdisplay;
> + }
> +
> if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, intf_width, slice_per_intf;
> + u32 total_bytes_per_intf;
> +
> + /* first calculate dsc parameters and then program
> + * compress mode registers
> + */
> + intf_width = hdisplay;
> + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> +
> + dsc->drm->slice_count = 1;
> + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = dsc->bytes_per_pkt << 16;
> + reg |= (0x0b << 8); /* dtype of compressed image */
> +
> + /* pkt_per_line:
> + * 0 == 1 pkt
> + * 1 == 2 pkt
> + * 2 == 4 pkt
> + * 3 pkt is not supported
> + * above translates to ffs() - 1
> + */
> + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + dsi_write(msm_host,
> + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> + }
> +
> dsi_write(msm_host, REG_DSI_ACTIVE_H,
> DSI_ACTIVE_H_START(ha_start) |
> DSI_ACTIVE_H_END(ha_end));
> @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> } else { /* command mode */
> + if (msm_host->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> + u32 reg, reg_ctrl, reg_ctrl2;
> + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> +
> + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> +
> + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> + dsc->drm->bits_per_pixel, 8);
> + dsc->drm->slice_chunk_size = bytes_in_slice;
> + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
Should we use dsc->bytes_in_slice or just bytes_in_slice here?
> + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> +
> + reg = 0x39 << 8;
> + reg |= ffs(dsc->pkt_per_line) << 6;
> +
> + dsc->eol_byte_num = total_bytes_per_intf % 3;
> + reg |= dsc->eol_byte_num << 4;
> + reg |= 1;
> +
> + reg_ctrl |= reg;
> + reg_ctrl2 |= bytes_in_slice;
> +
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL, reg);
> + dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2);
> + }
> +
> /* image data and 1 byte write_memory_start cmd */
> - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + if (!msm_host->dsc)
> + wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1;
> + else
> + wc = mode->hdisplay / 2 + 1;
>
> dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_CTRL,
> DSI_CMD_MDP_STREAM0_CTRL_WORD_COUNT(wc) |
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-21 2:17 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 2:17 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
I have been looking throught the dsc params calculation. And it looks
like this struct is not necessary at all.
inital_lines can be passed to dpu_encoder_dsc_pipe_cfg() /
hw_dsc->ops.dsc_config() directly.
slice_last_group_size and det_thresh_flatness can be calculated in
dpu_hw_dsc_config() directly. And the rest is only used in
dsi_timing_setup(), where they are calculated an immediately used to set
the hardware. Let's probably drop it, unless there is a good reason to
have it?
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data
@ 2022-02-21 2:17 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 2:17 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> Display Stream Compression (DSC) parameters need to be calculated. Add
> helpers and struct msm_display_dsc_config in msm_drv for this
> msm_display_dsc_config uses drm_dsc_config for DSC parameters.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/dsi/dsi_host.c | 132 +++++++++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 15 ++++
> 2 files changed, 147 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 6b3ced4aaaf5..27553194f9fa 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -31,6 +31,8 @@
>
> #define DSI_RESET_TOGGLE_DELAY_MS 20
>
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc);
> +
> static int dsi_get_version(const void __iomem *base, u32 *major, u32 *minor)
> {
> u32 ver;
> @@ -157,6 +159,7 @@ struct msm_dsi_host {
> struct regmap *sfpb;
>
> struct drm_display_mode *mode;
> + struct msm_display_dsc_config *dsc;
>
> /* connected device info */
> struct device_node *device_node;
> @@ -1718,6 +1721,135 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host,
> return -EINVAL;
> }
>
> +static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = {
> + 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62,
> + 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e
> +};
> +
> +/* only 8bpc, 8bpp added */
> +static char min_qp[DSC_NUM_BUF_RANGES] = {
> + 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13
> +};
> +
> +static char max_qp[DSC_NUM_BUF_RANGES] = {
> + 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15
> +};
> +
> +static char bpg_offset[DSC_NUM_BUF_RANGES] = {
> + 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12
> +};
> +
> +static int dsi_populate_dsc_params(struct msm_display_dsc_config *dsc)
> +{
> + int mux_words_size;
> + int groups_per_line, groups_total;
> + int min_rate_buffer_size;
> + int hrd_delay;
> + int pre_num_extra_mux_bits, num_extra_mux_bits;
> + int slice_bits;
> + int target_bpp_x16;
> + int data;
> + int final_value, final_scale;
> + int i;
> +
> + dsc->drm->rc_model_size = 8192;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->rc_edge_factor = 6;
> + dsc->drm->rc_tgt_offset_high = 3;
> + dsc->drm->rc_tgt_offset_low = 3;
> + dsc->drm->simple_422 = 0;
> + dsc->drm->convert_rgb = 1;
> + dsc->drm->vbr_enable = 0;
> +
> + /* handle only bpp = bpc = 8 */
> + for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++)
> + dsc->drm->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i];
> +
> + for (i = 0; i < DSC_NUM_BUF_RANGES; i++) {
> + dsc->drm->rc_range_params[i].range_min_qp = min_qp[i];
> + dsc->drm->rc_range_params[i].range_max_qp = max_qp[i];
> + dsc->drm->rc_range_params[i].range_bpg_offset = bpg_offset[i];
> + }
> +
> + dsc->drm->initial_offset = 6144; /* Not bpp 12 */
> + if (dsc->drm->bits_per_pixel != 8)
> + dsc->drm->initial_offset = 2048; /* bpp = 12 */
> +
> + mux_words_size = 48; /* bpc == 8/10 */
> + if (dsc->drm->bits_per_component == 12)
> + mux_words_size = 64;
> +
> + dsc->drm->initial_xmit_delay = 512;
> + dsc->drm->initial_scale_value = 32;
> + dsc->drm->first_line_bpg_offset = 12;
> + dsc->drm->line_buf_depth = dsc->drm->bits_per_component + 1;
> +
> + /* bpc 8 */
> + dsc->drm->flatness_min_qp = 3;
> + dsc->drm->flatness_max_qp = 12;
> + dsc->det_thresh_flatness = 7 + 2 * (dsc->drm->bits_per_component - 8);
> + dsc->drm->rc_quant_incr_limit0 = 11;
> + dsc->drm->rc_quant_incr_limit1 = 11;
> + dsc->drm->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC;
> +
> + /* FIXME: need to call drm_dsc_compute_rc_parameters() so that rest of
> + * params are calculated
> + */
> + dsc->slice_last_group_size = 3 - (dsc->drm->slice_width % 3);
> + groups_per_line = DIV_ROUND_UP(dsc->drm->slice_width, 3);
> + dsc->drm->slice_chunk_size = dsc->drm->slice_width * dsc->drm->bits_per_pixel / 8;
> + if ((dsc->drm->slice_width * dsc->drm->bits_per_pixel) % 8)
> + dsc->drm->slice_chunk_size++;
> +
> + /* rbs-min */
> + min_rate_buffer_size = dsc->drm->rc_model_size - dsc->drm->initial_offset +
> + dsc->drm->initial_xmit_delay * dsc->drm->bits_per_pixel +
> + groups_per_line * dsc->drm->first_line_bpg_offset;
> +
> + hrd_delay = DIV_ROUND_UP(min_rate_buffer_size, dsc->drm->bits_per_pixel);
> +
> + dsc->drm->initial_dec_delay = hrd_delay - dsc->drm->initial_xmit_delay;
> +
> + dsc->drm->initial_scale_value = 8 * dsc->drm->rc_model_size /
> + (dsc->drm->rc_model_size - dsc->drm->initial_offset);
> +
> + slice_bits = 8 * dsc->drm->slice_chunk_size * dsc->drm->slice_height;
> +
> + groups_total = groups_per_line * dsc->drm->slice_height;
> +
> + data = dsc->drm->first_line_bpg_offset * 2048;
> +
> + dsc->drm->nfl_bpg_offset = DIV_ROUND_UP(data, (dsc->drm->slice_height - 1));
> +
> + pre_num_extra_mux_bits = 3 * (mux_words_size + (4 * dsc->drm->bits_per_component + 4) - 2);
> +
> + num_extra_mux_bits = pre_num_extra_mux_bits - (mux_words_size -
> + ((slice_bits - pre_num_extra_mux_bits) % mux_words_size));
> +
> + data = 2048 * (dsc->drm->rc_model_size - dsc->drm->initial_offset + num_extra_mux_bits);
> + dsc->drm->slice_bpg_offset = DIV_ROUND_UP(data, groups_total);
> +
> + /* bpp * 16 + 0.5 */
> + data = dsc->drm->bits_per_pixel * 16;
> + data *= 2;
> + data++;
> + data /= 2;
> + target_bpp_x16 = data;
> +
> + data = (dsc->drm->initial_xmit_delay * target_bpp_x16) / 16;
> + final_value = dsc->drm->rc_model_size - data + num_extra_mux_bits;
> + dsc->drm->final_offset = final_value;
> +
> + final_scale = 8 * dsc->drm->rc_model_size / (dsc->drm->rc_model_size - final_value);
> +
> + data = (final_scale - 9) * (dsc->drm->nfl_bpg_offset + dsc->drm->slice_bpg_offset);
> + dsc->drm->scale_increment_interval = (2048 * dsc->drm->final_offset) / data;
> +
> + dsc->drm->scale_decrement_interval = groups_per_line / (dsc->drm->initial_scale_value - 8);
> +
> + return 0;
> +}
> +
> static int dsi_host_parse_dt(struct msm_dsi_host *msm_host)
> {
> struct device *dev = &msm_host->pdev->dev;
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index d7574e6bd4e4..384f9bad4760 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -30,6 +30,7 @@
> #include <drm/drm_plane_helper.h>
> #include <drm/drm_probe_helper.h>
> #include <drm/drm_fb_helper.h>
> +#include <drm/drm_dsc.h>
> #include <drm/msm_drm.h>
> #include <drm/drm_gem.h>
>
> @@ -134,6 +135,20 @@ struct msm_drm_thread {
> struct kthread_worker *worker;
> };
>
> +/* DSC config */
> +struct msm_display_dsc_config {
> + struct drm_dsc_config *drm;
> +
> + u32 initial_lines;
> + u32 pkt_per_line;
> + u32 bytes_in_slice;
> + u32 bytes_per_pkt;
> + u32 eol_byte_num;
> + u32 pclk_per_line;
> + u32 slice_last_group_size;
> + u32 det_thresh_flatness;
I have been looking throught the dsc params calculation. And it looks
like this struct is not necessary at all.
inital_lines can be passed to dpu_encoder_dsc_pipe_cfg() /
hw_dsc->ops.dsc_config() directly.
slice_last_group_size and det_thresh_flatness can be calculated in
dpu_hw_dsc_config() directly. And the rest is only used in
dsi_timing_setup(), where they are calculated an immediately used to set
the hardware. Let's probably drop it, unless there is a good reason to
have it?
> +};
> +
> struct msm_drm_private {
>
> struct drm_device *dev;
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
2022-02-10 10:34 ` Vinod Koul
@ 2022-02-21 12:37 ` Dmitry Baryshkov
-1 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 12:37 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: linux-arm-msm, Bjorn Andersson, David Airlie, Daniel Vetter,
Jonathan Marek, Abhinav Kumar, linux-kernel, dri-devel,
freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
This is not a blocker or a request for a change, just a kind of thought:
I've been looking onto this change for a while from the following point
of view. I'd like to switch DSI driver to use panel
bridge/drm_bridge_connector(). This simplifies handling of DRM bridge
chains.
Also since DSC can be consumed not by the panel itself, but by the next
bridge in chain (e.g. it's supported on the DSI input by the ANX7625
bridge), using drm_panel doesn't look completely correct.
So, I have been looking for a better way to pass DSC configuration.
For DSI we can use struct mipi_dsi_device (together with the rest of
data we are passing from DSI device driver to DSI host). This would
allow both DSI panels and DSI bridges to pass the DSC config to the
previous deivce in chain (DSI host).
Any comments/thoughs?
Note, for DP this problem doesn't exist. The DSC config is a part of
DPDC, so it will be parsed by the msm/dp driver in a natural way.
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
@ 2022-02-21 12:37 ` Dmitry Baryshkov
0 siblings, 0 replies; 127+ messages in thread
From: Dmitry Baryshkov @ 2022-02-21 12:37 UTC (permalink / raw)
To: Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 10/02/2022 13:34, Vinod Koul wrote:
> When DSC is enabled, we need to pass the DSC parameters to panel driver
> as well, so add a dsc parameter in panel and set it when DSC is enabled
>
> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
> which will enable and configure DSC hardware blocks accordingly.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
> include/drm/drm_panel.h | 7 +++++++
> 6 files changed, 45 insertions(+)
>
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> index 47fe11a84a77..ef6ddac22767 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct drm_device *dev,
> MSM_DISPLAY_CAP_CMD_MODE :
> MSM_DISPLAY_CAP_VID_MODE;
>
> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
> +
> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
> if (rc) {
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c
> index 052548883d27..3aeac15e7421 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
> return !(host_flags & MIPI_DSI_MODE_VIDEO);
> }
>
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
> +}
> +
> static int dsi_get_phy(struct msm_dsi *msm_dsi)
> {
> struct platform_device *pdev = msm_dsi->pdev;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h
> index c8dedc95428c..16cd9b2fce86 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi.h
> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi);
> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_dsi_host *host);
> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host);
>
> /* dsi phy */
> struct msm_dsi_phy;
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index 27553194f9fa..7e9913eff724 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct mipi_dsi_host *host,
> {
> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> + struct drm_panel *panel;
> int ret;
>
> msm_host->dev = dev;
> + panel = msm_dsi_host_get_panel(&msm_host->base);
> +
> + if (panel && panel->dsc) {
> + struct msm_display_dsc_config *dsc = msm_host->dsc;
> +
> + if (!dsc) {
> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc), GFP_KERNEL);
> + if (!dsc)
> + return -ENOMEM;
> + dsc->drm = panel->dsc;
> + msm_host->dsc = dsc;
> + }
> + }
> +
> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
> if (ret) {
> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host)
> dsi_write(msm_host, REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
> }
> +
> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct mipi_dsi_host *host)
> +{
> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
> +
> + return msm_host->dsc;
> +}
> diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
> index 384f9bad4760..e7a312edfe67 100644
> --- a/drivers/gpu/drm/msm/msm_drv.h
> +++ b/drivers/gpu/drm/msm/msm_drv.h
> @@ -119,6 +119,7 @@ struct msm_display_topology {
> * based on num_of_h_tiles
> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
> * used instead of panel TE in cmd mode panels
> + * @dsc: DSC configuration data for DSC-enabled displays
> */
> struct msm_display_info {
> int intf_type;
> @@ -126,6 +127,7 @@ struct msm_display_info {
> uint32_t num_of_h_tiles;
> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
> bool is_te_using_watchdog_timer;
> + struct msm_display_dsc_config *dsc;
> };
>
> /* Commit/Event thread specific structure */
> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state *disp_state, struct msm_dsi *msm_dsi
> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi);
> #else
> static inline void __init msm_dsi_register(void)
> {
> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi)
> {
> return false;
> }
> +
> +static inline struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
> +{
> + return NULL;
> +}
> #endif
>
> #ifdef CONFIG_DRM_MSM_DP
> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
> index 4602f833eb51..eb8ae9bf32ed 100644
> --- a/include/drm/drm_panel.h
> +++ b/include/drm/drm_panel.h
> @@ -171,6 +171,13 @@ struct drm_panel {
> * Panel entry in registry.
> */
> struct list_head list;
> +
> + /**
> + * @dsc:
> + *
> + * Panel DSC pps payload to be sent
> + */
> + struct drm_dsc_config *dsc;
This is not a blocker or a request for a change, just a kind of thought:
I've been looking onto this change for a while from the following point
of view. I'd like to switch DSI driver to use panel
bridge/drm_bridge_connector(). This simplifies handling of DRM bridge
chains.
Also since DSC can be consumed not by the panel itself, but by the next
bridge in chain (e.g. it's supported on the DSI input by the ANX7625
bridge), using drm_panel doesn't look completely correct.
So, I have been looking for a better way to pass DSC configuration.
For DSI we can use struct mipi_dsi_device (together with the rest of
data we are passing from DSI device driver to DSI host). This would
allow both DSI panels and DSI bridges to pass the DSC config to the
previous deivce in chain (DSI host).
Any comments/thoughs?
Note, for DP this problem doesn't exist. The DSC config is a part of
DPDC, so it will be parsed by the msm/dp driver in a natural way.
> };
>
> void drm_panel_init(struct drm_panel *panel, struct device *dev,
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
2022-02-21 12:37 ` Dmitry Baryshkov
@ 2022-03-03 19:08 ` Abhinav Kumar
-1 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-03-03 19:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 2/21/2022 4:37 AM, Dmitry Baryshkov wrote:
> On 10/02/2022 13:34, Vinod Koul wrote:
>> When DSC is enabled, we need to pass the DSC parameters to panel driver
>> as well, so add a dsc parameter in panel and set it when DSC is enabled
>>
>> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
>> which will enable and configure DSC hardware blocks accordingly.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
>> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
>> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
>> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
>> include/drm/drm_panel.h | 7 +++++++
>> 6 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 47fe11a84a77..ef6ddac22767 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct
>> drm_device *dev,
>> MSM_DISPLAY_CAP_CMD_MODE :
>> MSM_DISPLAY_CAP_VID_MODE;
>> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
>> +
>> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
>> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
>> if (rc) {
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c
>> b/drivers/gpu/drm/msm/dsi/dsi.c
>> index 052548883d27..3aeac15e7421 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
>> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
>> return !(host_flags & MIPI_DSI_MODE_VIDEO);
>> }
>> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi
>> *msm_dsi)
>> +{
>> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
>> +}
>> +
>> static int dsi_get_phy(struct msm_dsi *msm_dsi)
>> {
>> struct platform_device *pdev = msm_dsi->pdev;
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
>> b/drivers/gpu/drm/msm/dsi/dsi.h
>> index c8dedc95428c..16cd9b2fce86 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
>> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host
>> *msm_host, bool is_bonded_dsi);
>> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
>> is_bonded_dsi);
>> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct
>> mipi_dsi_host *host);
>> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
>> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct
>> mipi_dsi_host *host);
>> /* dsi phy */
>> struct msm_dsi_phy;
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 27553194f9fa..7e9913eff724 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct
>> mipi_dsi_host *host,
>> {
>> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
>> + struct drm_panel *panel;
>> int ret;
>> msm_host->dev = dev;
>> + panel = msm_dsi_host_get_panel(&msm_host->base);
>> +
>> + if (panel && panel->dsc) {
>> + struct msm_display_dsc_config *dsc = msm_host->dsc;
>> +
>> + if (!dsc) {
>> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc),
>> GFP_KERNEL);
>> + if (!dsc)
>> + return -ENOMEM;
>> + dsc->drm = panel->dsc;
>> + msm_host->dsc = dsc;
>> + }
>> + }
>> +
>> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
>> if (ret) {
>> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
>> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct
>> mipi_dsi_host *host)
>> dsi_write(msm_host,
>> REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
>> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
>> }
>> +
>> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct
>> mipi_dsi_host *host)
>> +{
>> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>> +
>> + return msm_host->dsc;
>> +}
>> diff --git a/drivers/gpu/drm/msm/msm_drv.h
>> b/drivers/gpu/drm/msm/msm_drv.h
>> index 384f9bad4760..e7a312edfe67 100644
>> --- a/drivers/gpu/drm/msm/msm_drv.h
>> +++ b/drivers/gpu/drm/msm/msm_drv.h
>> @@ -119,6 +119,7 @@ struct msm_display_topology {
>> * based on num_of_h_tiles
>> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
>> * used instead of panel TE in cmd mode panels
>> + * @dsc: DSC configuration data for DSC-enabled displays
>> */
>> struct msm_display_info {
>> int intf_type;
>> @@ -126,6 +127,7 @@ struct msm_display_info {
>> uint32_t num_of_h_tiles;
>> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
>> bool is_te_using_watchdog_timer;
>> + struct msm_display_dsc_config *dsc;
>> };
>> /* Commit/Event thread specific structure */
>> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state
>> *disp_state, struct msm_dsi *msm_dsi
>> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
>> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
>> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
>> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi
>> *msm_dsi);
>> #else
>> static inline void __init msm_dsi_register(void)
>> {
>> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct
>> msm_dsi *msm_dsi)
>> {
>> return false;
>> }
>> +
>> +static inline struct msm_display_dsc_config
>> *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
>> +{
>> + return NULL;
>> +}
>> #endif
>> #ifdef CONFIG_DRM_MSM_DP
>> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
>> index 4602f833eb51..eb8ae9bf32ed 100644
>> --- a/include/drm/drm_panel.h
>> +++ b/include/drm/drm_panel.h
>> @@ -171,6 +171,13 @@ struct drm_panel {
>> * Panel entry in registry.
>> */
>> struct list_head list;
>> +
>> + /**
>> + * @dsc:
>> + *
>> + * Panel DSC pps payload to be sent
>> + */
>> + struct drm_dsc_config *dsc;
>
> This is not a blocker or a request for a change, just a kind of thought:
>
> I've been looking onto this change for a while from the following point
> of view. I'd like to switch DSI driver to use panel
> bridge/drm_bridge_connector(). This simplifies handling of DRM bridge
> chains.
>
> Also since DSC can be consumed not by the panel itself, but by the next
> bridge in chain (e.g. it's supported on the DSI input by the ANX7625
> bridge), using drm_panel doesn't look completely correct.
>
> So, I have been looking for a better way to pass DSC configuration.
>
> For DSI we can use struct mipi_dsi_device (together with the rest of
> data we are passing from DSI device driver to DSI host). This would
> allow both DSI panels and DSI bridges to pass the DSC config to the
> previous deivce in chain (DSI host).
>
> Any comments/thoughs?
>
> Note, for DP this problem doesn't exist. The DSC config is a part of
> DPDC, so it will be parsed by the msm/dp driver in a natural way.
>
Yes, i do agree that in case of bridges in between , drm_panel is not
necessarily the best place to do it and mipi_dsi_device is better.
However, I also think we can do this post the cleanup fo move to panel
bridge.
>
>> };
>> void drm_panel_init(struct drm_panel *panel, struct device *dev,
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel
@ 2022-03-03 19:08 ` Abhinav Kumar
0 siblings, 0 replies; 127+ messages in thread
From: Abhinav Kumar @ 2022-03-03 19:08 UTC (permalink / raw)
To: Dmitry Baryshkov, Vinod Koul, Rob Clark
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 2/21/2022 4:37 AM, Dmitry Baryshkov wrote:
> On 10/02/2022 13:34, Vinod Koul wrote:
>> When DSC is enabled, we need to pass the DSC parameters to panel driver
>> as well, so add a dsc parameter in panel and set it when DSC is enabled
>>
>> Also, fetch and pass DSC configuration for DSI panels to DPU encoder,
>> which will enable and configure DSC hardware blocks accordingly.
>>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>> Signed-off-by: Vinod Koul <vkoul@kernel.org>
>> ---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 2 ++
>> drivers/gpu/drm/msm/dsi/dsi.c | 5 +++++
>> drivers/gpu/drm/msm/dsi/dsi.h | 1 +
>> drivers/gpu/drm/msm/dsi/dsi_host.c | 22 ++++++++++++++++++++++
>> drivers/gpu/drm/msm/msm_drv.h | 8 ++++++++
>> include/drm/drm_panel.h | 7 +++++++
>> 6 files changed, 45 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> index 47fe11a84a77..ef6ddac22767 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
>> @@ -578,6 +578,8 @@ static int _dpu_kms_initialize_dsi(struct
>> drm_device *dev,
>> MSM_DISPLAY_CAP_CMD_MODE :
>> MSM_DISPLAY_CAP_VID_MODE;
>> + info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
>> +
>> if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
>> rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
>> if (rc) {
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.c
>> b/drivers/gpu/drm/msm/dsi/dsi.c
>> index 052548883d27..3aeac15e7421 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.c
>> @@ -20,6 +20,11 @@ bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi)
>> return !(host_flags & MIPI_DSI_MODE_VIDEO);
>> }
>> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi
>> *msm_dsi)
>> +{
>> + return msm_dsi_host_get_dsc_config(msm_dsi->host);
>> +}
>> +
>> static int dsi_get_phy(struct msm_dsi *msm_dsi)
>> {
>> struct platform_device *pdev = msm_dsi->pdev;
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi.h
>> b/drivers/gpu/drm/msm/dsi/dsi.h
>> index c8dedc95428c..16cd9b2fce86 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi.h
>> +++ b/drivers/gpu/drm/msm/dsi/dsi.h
>> @@ -152,6 +152,7 @@ int dsi_calc_clk_rate_v2(struct msm_dsi_host
>> *msm_host, bool is_bonded_dsi);
>> int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool
>> is_bonded_dsi);
>> void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct
>> mipi_dsi_host *host);
>> void msm_dsi_host_test_pattern_en(struct mipi_dsi_host *host);
>> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct
>> mipi_dsi_host *host);
>> /* dsi phy */
>> struct msm_dsi_phy;
>> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> index 27553194f9fa..7e9913eff724 100644
>> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
>> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
>> @@ -2059,9 +2059,24 @@ int msm_dsi_host_modeset_init(struct
>> mipi_dsi_host *host,
>> {
>> struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>> const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
>> + struct drm_panel *panel;
>> int ret;
>> msm_host->dev = dev;
>> + panel = msm_dsi_host_get_panel(&msm_host->base);
>> +
>> + if (panel && panel->dsc) {
>> + struct msm_display_dsc_config *dsc = msm_host->dsc;
>> +
>> + if (!dsc) {
>> + dsc = devm_kzalloc(&msm_host->pdev->dev, sizeof(*dsc),
>> GFP_KERNEL);
>> + if (!dsc)
>> + return -ENOMEM;
>> + dsc->drm = panel->dsc;
>> + msm_host->dsc = dsc;
>> + }
>> + }
>> +
>> ret = cfg_hnd->ops->tx_buf_alloc(msm_host, SZ_4K);
>> if (ret) {
>> pr_err("%s: alloc tx gem obj failed, %d\n", __func__, ret);
>> @@ -2626,3 +2641,10 @@ void msm_dsi_host_test_pattern_en(struct
>> mipi_dsi_host *host)
>> dsi_write(msm_host,
>> REG_DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER,
>> DSI_TEST_PATTERN_GEN_CMD_STREAM0_TRIGGER_SW_TRIGGER);
>> }
>> +
>> +struct msm_display_dsc_config *msm_dsi_host_get_dsc_config(struct
>> mipi_dsi_host *host)
>> +{
>> + struct msm_dsi_host *msm_host = to_msm_dsi_host(host);
>> +
>> + return msm_host->dsc;
>> +}
>> diff --git a/drivers/gpu/drm/msm/msm_drv.h
>> b/drivers/gpu/drm/msm/msm_drv.h
>> index 384f9bad4760..e7a312edfe67 100644
>> --- a/drivers/gpu/drm/msm/msm_drv.h
>> +++ b/drivers/gpu/drm/msm/msm_drv.h
>> @@ -119,6 +119,7 @@ struct msm_display_topology {
>> * based on num_of_h_tiles
>> * @is_te_using_watchdog_timer: Boolean to indicate watchdog TE is
>> * used instead of panel TE in cmd mode panels
>> + * @dsc: DSC configuration data for DSC-enabled displays
>> */
>> struct msm_display_info {
>> int intf_type;
>> @@ -126,6 +127,7 @@ struct msm_display_info {
>> uint32_t num_of_h_tiles;
>> uint32_t h_tile_instance[MAX_H_TILES_PER_DISPLAY];
>> bool is_te_using_watchdog_timer;
>> + struct msm_display_dsc_config *dsc;
>> };
>> /* Commit/Event thread specific structure */
>> @@ -365,6 +367,7 @@ void msm_dsi_snapshot(struct msm_disp_state
>> *disp_state, struct msm_dsi *msm_dsi
>> bool msm_dsi_is_cmd_mode(struct msm_dsi *msm_dsi);
>> bool msm_dsi_is_bonded_dsi(struct msm_dsi *msm_dsi);
>> bool msm_dsi_is_master_dsi(struct msm_dsi *msm_dsi);
>> +struct msm_display_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi
>> *msm_dsi);
>> #else
>> static inline void __init msm_dsi_register(void)
>> {
>> @@ -393,6 +396,11 @@ static inline bool msm_dsi_is_master_dsi(struct
>> msm_dsi *msm_dsi)
>> {
>> return false;
>> }
>> +
>> +static inline struct msm_display_dsc_config
>> *msm_dsi_get_dsc_config(struct msm_dsi *msm_dsi)
>> +{
>> + return NULL;
>> +}
>> #endif
>> #ifdef CONFIG_DRM_MSM_DP
>> diff --git a/include/drm/drm_panel.h b/include/drm/drm_panel.h
>> index 4602f833eb51..eb8ae9bf32ed 100644
>> --- a/include/drm/drm_panel.h
>> +++ b/include/drm/drm_panel.h
>> @@ -171,6 +171,13 @@ struct drm_panel {
>> * Panel entry in registry.
>> */
>> struct list_head list;
>> +
>> + /**
>> + * @dsc:
>> + *
>> + * Panel DSC pps payload to be sent
>> + */
>> + struct drm_dsc_config *dsc;
>
> This is not a blocker or a request for a change, just a kind of thought:
>
> I've been looking onto this change for a while from the following point
> of view. I'd like to switch DSI driver to use panel
> bridge/drm_bridge_connector(). This simplifies handling of DRM bridge
> chains.
>
> Also since DSC can be consumed not by the panel itself, but by the next
> bridge in chain (e.g. it's supported on the DSI input by the ANX7625
> bridge), using drm_panel doesn't look completely correct.
>
> So, I have been looking for a better way to pass DSC configuration.
>
> For DSI we can use struct mipi_dsi_device (together with the rest of
> data we are passing from DSI device driver to DSI host). This would
> allow both DSI panels and DSI bridges to pass the DSC config to the
> previous deivce in chain (DSI host).
>
> Any comments/thoughs?
>
> Note, for DP this problem doesn't exist. The DSC config is a part of
> DPDC, so it will be parsed by the msm/dp driver in a natural way.
>
Yes, i do agree that in case of bridges in between , drm_panel is not
necessarily the best place to do it and mipi_dsi_device is better.
However, I also think we can do this post the cleanup fo move to panel
bridge.
>
>> };
>> void drm_panel_init(struct drm_panel *panel, struct device *dev,
>
>
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-17 21:44 ` Marijn Suijten
@ 2022-03-23 11:38 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 11:38 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, Rob Clark, dri-devel,
Daniel Vetter, Dmitry Baryshkov, freedreno
On 17-02-22, 22:44, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > Also, it is better to use 2 LMs and DSC instances as half width results
> > in lesser power consumption as compared to single LM, DSC at full width.
> >
> > The panel has been tested only with 2,2,1 configuration, so for
> > now we blindly create 2,2,1 topology when DSC is enabled
> >
> > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> > drivers/gpu/drm/msm/msm_drv.h | 2 ++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 95a7bf362e81..13ccb7b3cce5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > topology.num_enc = 0;
> > topology.num_intf = intf_count;
> >
> > + if (dpu_enc->dsc) {
> > + /* In case of Display Stream Compression DSC, we would use
> > + * 2 encoders, 2 line mixers and 1 interface
>
> LM is a layer mixer, not a line mixer, right?
Right, thanks for spotting
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [Freedreno] [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-03-23 11:38 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 11:38 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 17-02-22, 22:44, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > Also, it is better to use 2 LMs and DSC instances as half width results
> > in lesser power consumption as compared to single LM, DSC at full width.
> >
> > The panel has been tested only with 2,2,1 configuration, so for
> > now we blindly create 2,2,1 topology when DSC is enabled
> >
> > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> > drivers/gpu/drm/msm/msm_drv.h | 2 ++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 95a7bf362e81..13ccb7b3cce5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > topology.num_enc = 0;
> > topology.num_intf = intf_count;
> >
> > + if (dpu_enc->dsc) {
> > + /* In case of Display Stream Compression DSC, we would use
> > + * 2 encoders, 2 line mixers and 1 interface
>
> LM is a layer mixer, not a line mixer, right?
Right, thanks for spotting
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
2022-02-17 22:37 ` Marijn Suijten
@ 2022-03-23 11:39 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 11:39 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 17-02-22, 23:37, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > Also, it is better to use 2 LMs and DSC instances as half width results
> > in lesser power consumption as compared to single LM, DSC at full width.
> >
> > The panel has been tested only with 2,2,1 configuration, so for
> > now we blindly create 2,2,1 topology when DSC is enabled
> >
> > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> > drivers/gpu/drm/msm/msm_drv.h | 2 ++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 95a7bf362e81..13ccb7b3cce5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > topology.num_enc = 0;
> > topology.num_intf = intf_count;
> >
> > + if (dpu_enc->dsc) {
> > + /* In case of Display Stream Compression DSC, we would use
>
> Just like elsewhere, since you wrote out Display Stream Compression,
> write the "DSC" abbreviation between parentheses ()?
Updated
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology
@ 2022-03-23 11:39 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 11:39 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 17-02-22, 23:37, Marijn Suijten wrote:
> On 2022-02-10 16:04:20, Vinod Koul wrote:
> > For DSC to work we typically need a 2,2,1 configuration. This should
> > suffice for resolutions up to 4k. For more resolutions like 8k this won't
> > work.
> >
> > Also, it is better to use 2 LMs and DSC instances as half width results
> > in lesser power consumption as compared to single LM, DSC at full width.
> >
> > The panel has been tested only with 2,2,1 configuration, so for
> > now we blindly create 2,2,1 topology when DSC is enabled
> >
> > Co-developed-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 13 +++++++++++++
> > drivers/gpu/drm/msm/msm_drv.h | 2 ++
> > 2 files changed, 15 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 95a7bf362e81..13ccb7b3cce5 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -574,8 +574,21 @@ static struct msm_display_topology dpu_encoder_get_topology(
> > topology.num_enc = 0;
> > topology.num_intf = intf_count;
> >
> > + if (dpu_enc->dsc) {
> > + /* In case of Display Stream Compression DSC, we would use
>
> Just like elsewhere, since you wrote out Display Stream Compression,
> write the "DSC" abbreviation between parentheses ()?
Updated
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-02-17 22:32 ` Marijn Suijten
@ 2022-03-23 14:40 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 14:40 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 17-02-22, 23:32, Marijn Suijten wrote:
> On 2022-02-10 16:04:17, Vinod Koul wrote:
> > We need to configure the encoder for DSC configuration and calculate DSC
> > parameters for the given timing so this patch adds that support by
> > adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> > 2 files changed, 171 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 1e648db439f9..95a7bf362e81 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -21,6 +21,7 @@
> > #include "dpu_hw_intf.h"
> > #include "dpu_hw_ctl.h"
> > #include "dpu_hw_dspp.h"
> > +#include "dpu_hw_dsc.h"
> > #include "dpu_formats.h"
> > #include "dpu_encoder_phys.h"
> > #include "dpu_crtc.h"
> > @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> > * @cur_slave: As above but for the slave encoder.
> > * @hw_pp: Handle to the pingpong blocks used for the display. No.
> > * pingpong blocks can be different than num_phys_encs.
> > + * @hw_dsc: Handle to the DSC blocks used for the display.
> > + * @dsc_mask: The bitmask of used DSC blocks.
>
> No need for "^The" prefix here.
Removed
>
> > * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> > * for partial update right-only cases, such as pingpong
> > * split where virtual pingpong does not generate IRQs
> > @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> > * @topology: topology of the display
> > * @idle_timeout: idle timeout duration in milliseconds
> > * @dp: msm_dp pointer, for DP encoders
> > + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> > */
> > struct dpu_encoder_virt {
> > struct drm_encoder base;
> > @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> > struct dpu_encoder_phys *cur_master;
> > struct dpu_encoder_phys *cur_slave;
> > struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> > + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> > +
> > + unsigned int dsc_mask;
> >
> > bool intfs_swapped;
> >
> > @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> > u32 idle_timeout;
> >
> > struct msm_dp *dp;
> > +
> > + /* DSC configuration */
> > + struct msm_display_dsc_config *dsc;
> > };
> >
> > #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> > @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> > struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> > - int num_lm, num_ctl, num_pp;
> > + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> > + int num_lm, num_ctl, num_pp, num_dsc;
> > int i, j;
> >
> > if (!drm_enc) {
> > @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> > dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> > : NULL;
> >
> > + dpu_enc->dsc_mask = 0;
> > +
> > + if (dpu_enc->dsc) {
> > + unsigned int dsc_mask = 0;
>
> Perhaps move this definition outside the if, and unconditionally
> perform:
>
> dpu_enc->dsc_mask = dsc_mask;
>
> Below the if, instead of having to write it twice when ->dsc is truthy?
That is a good suggestion, updated now
>
> > +
> > + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > + drm_enc->base.id, DPU_HW_BLK_DSC,
> > + hw_dsc, ARRAY_SIZE(hw_dsc));
> > + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> > + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> > +
> > + for (i = 0; i < num_dsc; i++)
> > + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
>
> Perhaps you can merge these loops? Assuming hw_dsc is already
> NULL-initialized, you only need to iterate to `i<num_dsc` once without
> extra conditional anyway?
Agreed, this does make it look neat
>
> > +
> > + dpu_enc->dsc_mask = dsc_mask;
> > + }
> > +
> > cstate = to_dpu_crtc_state(drm_crtc->state);
> >
> > for (i = 0; i < num_lm; i++) {
> > @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> > nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> > }
> >
> > +static void
> > +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> > +{
> > + int slice_count, slice_per_intf;
> > + int bytes_in_slice, total_bytes_per_intf;
> > +
> > + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> > + DPU_ERROR("Invalid DSC/slices\n");
>
> What's the forward slash for?
forward slash denotes an OR case in written, so above would imply
Invalid DSC or slices, I will make it 'or' to be clear
>
> > + return;
> > + }
> > +
> > + slice_count = dsc->drm->slice_count;
> > + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> > +
> > + /*
> > + * If slice_count is greater than slice_per_intf then default to 1.
> > + * This can happen during partial update.
> > + */
> > + if (slice_count > slice_per_intf)
> > + slice_count = 1;
> > +
> > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > + dsc->drm->bits_per_pixel, 8);
> > + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > + dsc->bytes_in_slice = bytes_in_slice;
> > + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> > + dsc->pkt_per_line = slice_per_intf / slice_count;
> > +}
>
> I've seen the same calculations duplicated twice in dsi code. Since the
> msm_display_dsc_config struct is available in a header, perhaps a single
> - easily reviewable and maintainable - calculation function should be
> available there too?
Let me try check if we can make it common..
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-03-23 14:40 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-23 14:40 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 17-02-22, 23:32, Marijn Suijten wrote:
> On 2022-02-10 16:04:17, Vinod Koul wrote:
> > We need to configure the encoder for DSC configuration and calculate DSC
> > parameters for the given timing so this patch adds that support by
> > adding dpu_encoder_prep_dsc() which is invoked when DSC is enabled.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 164 +++++++++++++++++-
> > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 8 +
> > 2 files changed, 171 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > index 1e648db439f9..95a7bf362e81 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
> > @@ -21,6 +21,7 @@
> > #include "dpu_hw_intf.h"
> > #include "dpu_hw_ctl.h"
> > #include "dpu_hw_dspp.h"
> > +#include "dpu_hw_dsc.h"
> > #include "dpu_formats.h"
> > #include "dpu_encoder_phys.h"
> > #include "dpu_crtc.h"
> > @@ -136,6 +137,8 @@ enum dpu_enc_rc_states {
> > * @cur_slave: As above but for the slave encoder.
> > * @hw_pp: Handle to the pingpong blocks used for the display. No.
> > * pingpong blocks can be different than num_phys_encs.
> > + * @hw_dsc: Handle to the DSC blocks used for the display.
> > + * @dsc_mask: The bitmask of used DSC blocks.
>
> No need for "^The" prefix here.
Removed
>
> > * @intfs_swapped: Whether or not the phys_enc interfaces have been swapped
> > * for partial update right-only cases, such as pingpong
> > * split where virtual pingpong does not generate IRQs
> > @@ -169,6 +172,7 @@ enum dpu_enc_rc_states {
> > * @topology: topology of the display
> > * @idle_timeout: idle timeout duration in milliseconds
> > * @dp: msm_dp pointer, for DP encoders
> > + * @dsc: msm_display_dsc_config pointer, for DSC-enabled encoders
> > */
> > struct dpu_encoder_virt {
> > struct drm_encoder base;
> > @@ -182,6 +186,9 @@ struct dpu_encoder_virt {
> > struct dpu_encoder_phys *cur_master;
> > struct dpu_encoder_phys *cur_slave;
> > struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
> > + struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
> > +
> > + unsigned int dsc_mask;
> >
> > bool intfs_swapped;
> >
> > @@ -209,6 +216,9 @@ struct dpu_encoder_virt {
> > u32 idle_timeout;
> >
> > struct msm_dp *dp;
> > +
> > + /* DSC configuration */
> > + struct msm_display_dsc_config *dsc;
> > };
> >
> > #define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
> > @@ -972,7 +982,8 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> > struct dpu_hw_blk *hw_ctl[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC];
> > struct dpu_hw_blk *hw_dspp[MAX_CHANNELS_PER_ENC] = { NULL };
> > - int num_lm, num_ctl, num_pp;
> > + struct dpu_hw_blk *hw_dsc[MAX_CHANNELS_PER_ENC];
> > + int num_lm, num_ctl, num_pp, num_dsc;
> > int i, j;
> >
> > if (!drm_enc) {
> > @@ -1027,6 +1038,23 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
> > dpu_enc->hw_pp[i] = i < num_pp ? to_dpu_hw_pingpong(hw_pp[i])
> > : NULL;
> >
> > + dpu_enc->dsc_mask = 0;
> > +
> > + if (dpu_enc->dsc) {
> > + unsigned int dsc_mask = 0;
>
> Perhaps move this definition outside the if, and unconditionally
> perform:
>
> dpu_enc->dsc_mask = dsc_mask;
>
> Below the if, instead of having to write it twice when ->dsc is truthy?
That is a good suggestion, updated now
>
> > +
> > + num_dsc = dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state,
> > + drm_enc->base.id, DPU_HW_BLK_DSC,
> > + hw_dsc, ARRAY_SIZE(hw_dsc));
> > + for (i = 0; i < MAX_CHANNELS_PER_ENC; i++)
> > + dpu_enc->hw_dsc[i] = i < num_dsc ? to_dpu_hw_dsc(hw_dsc[i]) : NULL;
> > +
> > + for (i = 0; i < num_dsc; i++)
> > + dsc_mask |= BIT(dpu_enc->hw_dsc[i]->idx - DSC_0);
>
> Perhaps you can merge these loops? Assuming hw_dsc is already
> NULL-initialized, you only need to iterate to `i<num_dsc` once without
> extra conditional anyway?
Agreed, this does make it look neat
>
> > +
> > + dpu_enc->dsc_mask = dsc_mask;
> > + }
> > +
> > cstate = to_dpu_crtc_state(drm_crtc->state);
> >
> > for (i = 0; i < num_lm; i++) {
> > @@ -1739,6 +1767,127 @@ static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work)
> > nsecs_to_jiffies(ktime_to_ns(wakeup_time)));
> > }
> >
> > +static void
> > +dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_config *dsc, u32 width)
> > +{
> > + int slice_count, slice_per_intf;
> > + int bytes_in_slice, total_bytes_per_intf;
> > +
> > + if (!dsc || !dsc->drm->slice_width || !dsc->drm->slice_count) {
> > + DPU_ERROR("Invalid DSC/slices\n");
>
> What's the forward slash for?
forward slash denotes an OR case in written, so above would imply
Invalid DSC or slices, I will make it 'or' to be clear
>
> > + return;
> > + }
> > +
> > + slice_count = dsc->drm->slice_count;
> > + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> > +
> > + /*
> > + * If slice_count is greater than slice_per_intf then default to 1.
> > + * This can happen during partial update.
> > + */
> > + if (slice_count > slice_per_intf)
> > + slice_count = 1;
> > +
> > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > + dsc->drm->bits_per_pixel, 8);
> > + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > + dsc->bytes_in_slice = bytes_in_slice;
> > + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> > + dsc->pkt_per_line = slice_per_intf / slice_count;
> > +}
>
> I've seen the same calculations duplicated twice in dsi code. Since the
> msm_display_dsc_config struct is available in a header, perhaps a single
> - easily reviewable and maintainable - calculation function should be
> available there too?
Let me try check if we can make it common..
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
2022-03-23 14:40 ` Vinod Koul
@ 2022-03-24 15:41 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 15:41 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 23-03-22, 20:10, Vinod Koul wrote:
> On 17-02-22, 23:32, Marijn Suijten wrote:
> > On 2022-02-10 16:04:17, Vinod Koul wrote:
> > > +
> > > + slice_count = dsc->drm->slice_count;
> > > + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> > > +
> > > + /*
> > > + * If slice_count is greater than slice_per_intf then default to 1.
> > > + * This can happen during partial update.
> > > + */
> > > + if (slice_count > slice_per_intf)
> > > + slice_count = 1;
> > > +
> > > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > > + dsc->drm->bits_per_pixel, 8);
> > > + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> > > +
> > > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > > + dsc->bytes_in_slice = bytes_in_slice;
> > > + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> > > + dsc->pkt_per_line = slice_per_intf / slice_count;
> > > +}
> >
> > I've seen the same calculations duplicated twice in dsi code. Since the
> > msm_display_dsc_config struct is available in a header, perhaps a single
> > - easily reviewable and maintainable - calculation function should be
> > available there too?
>
> Let me try check if we can make it common..
I rechecked and we can actually remove this as we do this caln in timing
and update the dsc structure there. So this fn is dropped now
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder
@ 2022-03-24 15:41 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 15:41 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 23-03-22, 20:10, Vinod Koul wrote:
> On 17-02-22, 23:32, Marijn Suijten wrote:
> > On 2022-02-10 16:04:17, Vinod Koul wrote:
> > > +
> > > + slice_count = dsc->drm->slice_count;
> > > + slice_per_intf = DIV_ROUND_UP(width, dsc->drm->slice_width);
> > > +
> > > + /*
> > > + * If slice_count is greater than slice_per_intf then default to 1.
> > > + * This can happen during partial update.
> > > + */
> > > + if (slice_count > slice_per_intf)
> > > + slice_count = 1;
> > > +
> > > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > > + dsc->drm->bits_per_pixel, 8);
> > > + total_bytes_per_intf = bytes_in_slice * slice_per_intf;
> > > +
> > > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > > + dsc->bytes_in_slice = bytes_in_slice;
> > > + dsc->bytes_per_pkt = bytes_in_slice * slice_count;
> > > + dsc->pkt_per_line = slice_per_intf / slice_count;
> > > +}
> >
> > I've seen the same calculations duplicated twice in dsi code. Since the
> > msm_display_dsc_config struct is available in a header, perhaps a single
> > - easily reviewable and maintainable - calculation function should be
> > available there too?
>
> Let me try check if we can make it common..
I rechecked and we can actually remove this as we do this caln in timing
and update the dsc structure there. So this fn is dropped now
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
2022-02-21 2:11 ` Dmitry Baryshkov
@ 2022-03-24 15:45 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 15:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Abhinav Kumar, linux-kernel,
dri-devel, freedreno
On 21-02-22, 05:11, Dmitry Baryshkov wrote:
> On 10/02/2022 13:34, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> > 2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > index 49b551ad1bff..c1c85df58c4b 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> > +
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> > +
> > #endif /* DSI_XML */
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index 438c80750682..3d8d5a1daaa3 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> > }
> > +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> > + int pic_width, int pic_height)
> > +{
> > + if (!dsc || !pic_width || !pic_height) {
> > + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> > + return -EINVAL;
> > + }
> > +
> > + dsc->drm->pic_width = pic_width;
> > + dsc->drm->pic_height = pic_height;
> > +
> > + return 0;
> > +}
> > +
> > static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > {
> > struct drm_display_mode *mode = msm_host->mode;
> > @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > hdisplay /= 2;
> > }
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > +
> > + /* update dsc params with timing params */
> > + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> > + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> > +
> > + /* we do the calculations for dsc parameters here so that
> > + * panel can use these parameters
> > + */
> > + dsi_populate_dsc_params(dsc);
> > +
> > + /* Divide the display by 3 but keep back/font porch and
> > + * pulse width same
> > + */
> > + h_total -= hdisplay;
> > + hdisplay /= 3;
> > + h_total += hdisplay;
> > + ha_end = ha_start + hdisplay;
> > + }
> > +
> > if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, intf_width, slice_per_intf;
> > + u32 total_bytes_per_intf;
> > +
> > + /* first calculate dsc parameters and then program
> > + * compress mode registers
> > + */
> > + intf_width = hdisplay;
> > + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> > +
> > + dsc->drm->slice_count = 1;
> > + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> > + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> > + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> > +
> > + reg = dsc->bytes_per_pkt << 16;
> > + reg |= (0x0b << 8); /* dtype of compressed image */
> > +
> > + /* pkt_per_line:
> > + * 0 == 1 pkt
> > + * 1 == 2 pkt
> > + * 2 == 4 pkt
> > + * 3 pkt is not supported
> > + * above translates to ffs() - 1
> > + */
> > + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + reg |= dsc->eol_byte_num << 4;
> > + reg |= 1;
> > +
> > + dsi_write(msm_host,
> > + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> > + }
> > +
> > dsi_write(msm_host, REG_DSI_ACTIVE_H,
> > DSI_ACTIVE_H_START(ha_start) |
> > DSI_ACTIVE_H_END(ha_end));
> > @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> > DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> > } else { /* command mode */
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, reg_ctrl, reg_ctrl2;
> > + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> > +
> > + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> > + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> > +
> > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > + dsc->drm->bits_per_pixel, 8);
> > + dsc->drm->slice_chunk_size = bytes_in_slice;
> > + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
>
> Should we use dsc->bytes_in_slice or just bytes_in_slice here?
This should be dsc->bytes_in_slice, fixed up now. Thanks for pointing
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration
@ 2022-03-24 15:45 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 15:45 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, freedreno
On 21-02-22, 05:11, Dmitry Baryshkov wrote:
> On 10/02/2022 13:34, Vinod Koul wrote:
> > When DSC is enabled, we need to configure DSI registers accordingly and
> > configure the respective stream compression registers.
> >
> > Add support to calculate the register setting based on DSC params and
> > timing information and configure these registers.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/dsi/dsi.xml.h | 10 +++
> > drivers/gpu/drm/msm/dsi/dsi_host.c | 109 ++++++++++++++++++++++++++++-
> > 2 files changed, 118 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > index 49b551ad1bff..c1c85df58c4b 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h
> > @@ -706,4 +706,14 @@ static inline uint32_t DSI_VERSION_MAJOR(uint32_t val)
> > #define REG_DSI_CPHY_MODE_CTRL 0x000002d4
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL 0x0000029c
> > +
> > +#define REG_DSI_VIDEO_COMPRESSION_MODE_CTRL2 0x000002a0
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL 0x000002a4
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2 0x000002a8
> > +
> > +#define REG_DSI_COMMAND_COMPRESSION_MODE_CTRL3 0x000002ac
> > +
> > #endif /* DSI_XML */
> > diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > index 438c80750682..3d8d5a1daaa3 100644
> > --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> > +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> > @@ -908,6 +908,20 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
> > dsi_write(msm_host, REG_DSI_CPHY_MODE_CTRL, BIT(0));
> > }
> > +static int dsi_dsc_update_pic_dim(struct msm_display_dsc_config *dsc,
> > + int pic_width, int pic_height)
> > +{
> > + if (!dsc || !pic_width || !pic_height) {
> > + pr_err("DSI: invalid input: pic_width: %d pic_height: %d\n", pic_width, pic_height);
> > + return -EINVAL;
> > + }
> > +
> > + dsc->drm->pic_width = pic_width;
> > + dsc->drm->pic_height = pic_height;
> > +
> > + return 0;
> > +}
> > +
> > static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > {
> > struct drm_display_mode *mode = msm_host->mode;
> > @@ -940,7 +954,68 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > hdisplay /= 2;
> > }
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > +
> > + /* update dsc params with timing params */
> > + dsi_dsc_update_pic_dim(dsc, mode->hdisplay, mode->vdisplay);
> > + DBG("Mode Width- %d x Height %d\n", dsc->drm->pic_width, dsc->drm->pic_height);
> > +
> > + /* we do the calculations for dsc parameters here so that
> > + * panel can use these parameters
> > + */
> > + dsi_populate_dsc_params(dsc);
> > +
> > + /* Divide the display by 3 but keep back/font porch and
> > + * pulse width same
> > + */
> > + h_total -= hdisplay;
> > + hdisplay /= 3;
> > + h_total += hdisplay;
> > + ha_end = ha_start + hdisplay;
> > + }
> > +
> > if (msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) {
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, intf_width, slice_per_intf;
> > + u32 total_bytes_per_intf;
> > +
> > + /* first calculate dsc parameters and then program
> > + * compress mode registers
> > + */
> > + intf_width = hdisplay;
> > + slice_per_intf = DIV_ROUND_UP(intf_width, dsc->drm->slice_width);
> > +
> > + dsc->drm->slice_count = 1;
> > + dsc->bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width * 8, 8);
> > + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
> > + dsc->bytes_per_pkt = dsc->bytes_in_slice * dsc->drm->slice_count;
> > + dsc->pkt_per_line = slice_per_intf / dsc->drm->slice_count;
> > +
> > + reg = dsc->bytes_per_pkt << 16;
> > + reg |= (0x0b << 8); /* dtype of compressed image */
> > +
> > + /* pkt_per_line:
> > + * 0 == 1 pkt
> > + * 1 == 2 pkt
> > + * 2 == 4 pkt
> > + * 3 pkt is not supported
> > + * above translates to ffs() - 1
> > + */
> > + reg |= (ffs(dsc->pkt_per_line) - 1) << 6;
> > +
> > + dsc->eol_byte_num = total_bytes_per_intf % 3;
> > + reg |= dsc->eol_byte_num << 4;
> > + reg |= 1;
> > +
> > + dsi_write(msm_host,
> > + REG_DSI_VIDEO_COMPRESSION_MODE_CTRL, reg);
> > + }
> > +
> > dsi_write(msm_host, REG_DSI_ACTIVE_H,
> > DSI_ACTIVE_H_START(ha_start) |
> > DSI_ACTIVE_H_END(ha_end));
> > @@ -959,8 +1034,40 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi)
> > DSI_ACTIVE_VSYNC_VPOS_START(vs_start) |
> > DSI_ACTIVE_VSYNC_VPOS_END(vs_end));
> > } else { /* command mode */
> > + if (msm_host->dsc) {
> > + struct msm_display_dsc_config *dsc = msm_host->dsc;
> > + u32 reg, reg_ctrl, reg_ctrl2;
> > + u32 slice_per_intf, bytes_in_slice, total_bytes_per_intf;
> > +
> > + reg_ctrl = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL);
> > + reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2);
> > +
> > + slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->drm->slice_width);
> > + bytes_in_slice = DIV_ROUND_UP(dsc->drm->slice_width *
> > + dsc->drm->bits_per_pixel, 8);
> > + dsc->drm->slice_chunk_size = bytes_in_slice;
> > + total_bytes_per_intf = dsc->bytes_in_slice * slice_per_intf;
>
> Should we use dsc->bytes_in_slice or just bytes_in_slice here?
This should be dsc->bytes_in_slice, fixed up now. Thanks for pointing
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
2022-02-17 22:20 ` Marijn Suijten
@ 2022-03-24 16:24 ` Vinod Koul
-1 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 16:24 UTC (permalink / raw)
To: Marijn Suijten
Cc: Rob Clark, linux-arm-msm, Bjorn Andersson, David Airlie,
Daniel Vetter, Jonathan Marek, Dmitry Baryshkov, Abhinav Kumar,
linux-kernel, dri-devel, freedreno
On 17-02-22, 23:20, Marijn Suijten wrote:
> On 2022-02-10 16:04:16, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> > 2 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > index 02da9ecf71f1..49659165cea8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > @@ -25,6 +25,8 @@
> > #define CTL_MERGE_3D_ACTIVE 0x0E4
> > #define CTL_INTF_ACTIVE 0x0F4
> > #define CTL_MERGE_3D_FLUSH 0x100
> > +#define CTL_DSC_ACTIVE 0x0E8
> > +#define CTL_DSC_FLUSH 0x104
> > #define CTL_INTF_FLUSH 0x110
> > #define CTL_INTF_MASTER 0x134
> > #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> > @@ -34,6 +36,7 @@
> >
> > #define DPU_REG_RESET_TIMEOUT_US 2000
> > #define MERGE_3D_IDX 23
> > +#define DSC_IDX 22
>
> This define does not seem used in any of these patches. Is that
> intended?
This should used in the below case you pointed, updated now
> > static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > index 806c171e5df2..9847c9c46d6f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> > * @merge_3d: 3d merge block used
> > * @intf_mode_sel: Interface mode, cmd / vid
> > * @stream_sel: Stream selection for multi-stream interfaces
> > + * @dsc: DSC BIT masks
>
> Bit masks of what? Enabled DSCs? A more verbose doc-comment is desired
> here, matching the rest of the fields :) - something like "DSC block(s)
> used" similar to merge_3d? Or copy the docs from `dsc_mask`, which is
> the value that is written into this field.
Updated
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
* Re: [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl
@ 2022-03-24 16:24 ` Vinod Koul
0 siblings, 0 replies; 127+ messages in thread
From: Vinod Koul @ 2022-03-24 16:24 UTC (permalink / raw)
To: Marijn Suijten
Cc: Jonathan Marek, David Airlie, linux-arm-msm, linux-kernel,
Abhinav Kumar, Bjorn Andersson, dri-devel, Dmitry Baryshkov,
freedreno
On 17-02-22, 23:20, Marijn Suijten wrote:
> On 2022-02-10 16:04:16, Vinod Koul wrote:
> > Later gens of hardware have DSC bits moved to hw_ctl, so configure these
> > bits so that DSC would work there as well
> >
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 11 ++++++++++-
> > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 ++
> > 2 files changed, 12 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > index 02da9ecf71f1..49659165cea8 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c
> > @@ -25,6 +25,8 @@
> > #define CTL_MERGE_3D_ACTIVE 0x0E4
> > #define CTL_INTF_ACTIVE 0x0F4
> > #define CTL_MERGE_3D_FLUSH 0x100
> > +#define CTL_DSC_ACTIVE 0x0E8
> > +#define CTL_DSC_FLUSH 0x104
> > #define CTL_INTF_FLUSH 0x110
> > #define CTL_INTF_MASTER 0x134
> > #define CTL_FETCH_PIPE_ACTIVE 0x0FC
> > @@ -34,6 +36,7 @@
> >
> > #define DPU_REG_RESET_TIMEOUT_US 2000
> > #define MERGE_3D_IDX 23
> > +#define DSC_IDX 22
>
> This define does not seem used in any of these patches. Is that
> intended?
This should used in the below case you pointed, updated now
> > static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > index 806c171e5df2..9847c9c46d6f 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h
> > @@ -40,6 +40,7 @@ struct dpu_hw_stage_cfg {
> > * @merge_3d: 3d merge block used
> > * @intf_mode_sel: Interface mode, cmd / vid
> > * @stream_sel: Stream selection for multi-stream interfaces
> > + * @dsc: DSC BIT masks
>
> Bit masks of what? Enabled DSCs? A more verbose doc-comment is desired
> here, matching the rest of the fields :) - something like "DSC block(s)
> used" similar to merge_3d? Or copy the docs from `dsc_mask`, which is
> the value that is written into this field.
Updated
--
~Vinod
^ permalink raw reply [flat|nested] 127+ messages in thread
end of thread, other threads:[~2022-03-24 16:25 UTC | newest]
Thread overview: 127+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-10 10:34 [REPOST PATCH v4 00/13] drm/msm: Add Display Stream Compression Support Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 01/13] drm/msm/dsi: add support for dsc data Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 11:07 ` Dmitry Baryshkov
2022-02-10 11:07 ` Dmitry Baryshkov
2022-02-17 20:06 ` Abhinav Kumar
2022-02-17 20:06 ` Abhinav Kumar
2022-02-21 2:17 ` Dmitry Baryshkov
2022-02-21 2:17 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 02/13] drm/msm/dsi: Pass DSC params to drm_panel Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 10:43 ` Dmitry Baryshkov
2022-02-10 10:43 ` Dmitry Baryshkov
2022-02-17 0:27 ` Abhinav Kumar
2022-02-17 0:27 ` Abhinav Kumar
2022-02-21 12:37 ` Dmitry Baryshkov
2022-02-21 12:37 ` Dmitry Baryshkov
2022-03-03 19:08 ` Abhinav Kumar
2022-03-03 19:08 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 03/13] drm/msm/disp/dpu1: Add support for DSC Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-16 18:57 ` Abhinav Kumar
2022-02-16 18:57 ` Abhinav Kumar
2022-02-16 19:46 ` Dmitry Baryshkov
2022-02-17 4:20 ` Vinod Koul
2022-02-17 4:20 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 04/13] drm/msm/disp/dpu1: Add support for DSC in pingpong block Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-16 19:49 ` Abhinav Kumar
2022-02-16 19:49 ` Abhinav Kumar
2022-02-17 4:21 ` Vinod Koul
2022-02-17 4:21 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 05/13] drm/msm/disp/dpu1: Add DSC for SDM845 to hw_catalog Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-16 19:42 ` [Freedreno] " Abhinav Kumar
2022-02-16 19:42 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 06/13] drm/msm/disp/dpu1: Add DSC support in hw_ctl Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-16 19:52 ` [Freedreno] " Abhinav Kumar
2022-02-16 19:52 ` Abhinav Kumar
2022-02-17 22:20 ` Marijn Suijten
2022-02-17 22:20 ` Marijn Suijten
2022-03-24 16:24 ` Vinod Koul
2022-03-24 16:24 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 07/13] drm/msm/disp/dpu1: Add support for DSC in encoder Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 11:13 ` Dmitry Baryshkov
2022-02-10 11:13 ` Dmitry Baryshkov
2022-02-16 19:54 ` [Freedreno] " Abhinav Kumar
2022-02-16 19:54 ` Abhinav Kumar
2022-02-17 6:08 ` Vinod Koul
2022-02-17 6:08 ` Vinod Koul
2022-02-17 22:32 ` Marijn Suijten
2022-02-17 22:32 ` Marijn Suijten
2022-03-23 14:40 ` Vinod Koul
2022-03-23 14:40 ` Vinod Koul
2022-03-24 15:41 ` Vinod Koul
2022-03-24 15:41 ` Vinod Koul
2022-02-21 1:41 ` Dmitry Baryshkov
2022-02-21 1:41 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 08/13] drm/msm/disp/dpu1: Don't use DSC with mode_3d Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 10:55 ` Dmitry Baryshkov
2022-02-10 10:55 ` Dmitry Baryshkov
2022-02-17 3:11 ` Abhinav Kumar
2022-02-17 3:11 ` Abhinav Kumar
2022-02-17 6:10 ` Vinod Koul
2022-02-17 6:10 ` Vinod Koul
2022-02-17 6:33 ` Abhinav Kumar
2022-02-17 6:33 ` Abhinav Kumar
2022-02-17 7:12 ` Dmitry Baryshkov
2022-02-17 7:12 ` Dmitry Baryshkov
2022-02-18 20:46 ` Abhinav Kumar
2022-02-18 20:46 ` Abhinav Kumar
2022-02-18 21:21 ` Dmitry Baryshkov
2022-02-18 21:21 ` Dmitry Baryshkov
2022-02-18 21:29 ` [Freedreno] " Abhinav Kumar
2022-02-18 21:29 ` Abhinav Kumar
2022-02-18 21:36 ` Dmitry Baryshkov
2022-02-18 21:36 ` Dmitry Baryshkov
2022-02-10 10:34 ` [REPOST PATCH v4 09/13] drm/msm: Add missing structure documentation Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 10:39 ` Dmitry Baryshkov
2022-02-10 10:39 ` Dmitry Baryshkov
2022-02-17 3:12 ` Abhinav Kumar
2022-02-17 3:12 ` Abhinav Kumar
2022-02-17 22:34 ` Marijn Suijten
2022-02-17 22:34 ` Marijn Suijten
2022-02-10 10:34 ` [REPOST PATCH v4 10/13] drm/msm/disp/dpu1: Add support for DSC in topology Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-10 10:47 ` Dmitry Baryshkov
2022-02-10 10:47 ` Dmitry Baryshkov
2022-02-17 21:44 ` Marijn Suijten
2022-02-17 21:44 ` Marijn Suijten
2022-03-23 11:38 ` [Freedreno] " Vinod Koul
2022-03-23 11:38 ` Vinod Koul
2022-02-17 22:37 ` Marijn Suijten
2022-02-17 22:37 ` Marijn Suijten
2022-03-23 11:39 ` Vinod Koul
2022-03-23 11:39 ` Vinod Koul
2022-02-10 10:34 ` [REPOST PATCH v4 11/13] drm/msm/disp/dpu1: Add DSC support in RM Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-17 3:14 ` Abhinav Kumar
2022-02-17 3:14 ` Abhinav Kumar
2022-02-17 3:21 ` Abhinav Kumar
2022-02-17 3:21 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 12/13] drm/msm/dsi: add mode valid callback for dsi_mgr Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-17 3:17 ` Abhinav Kumar
2022-02-17 3:17 ` Abhinav Kumar
2022-02-10 10:34 ` [REPOST PATCH v4 13/13] drm/msm/dsi: Add support for DSC configuration Vinod Koul
2022-02-10 10:34 ` Vinod Koul
2022-02-17 3:44 ` [Freedreno] " Abhinav Kumar
2022-02-17 3:44 ` Abhinav Kumar
2022-02-17 6:19 ` Vinod Koul
2022-02-17 6:19 ` Vinod Koul
2022-02-17 9:27 ` Marijn Suijten
2022-02-17 9:27 ` Marijn Suijten
2022-02-17 10:51 ` [Freedreno] " Vinod Koul
2022-02-17 10:51 ` Vinod Koul
2022-02-17 14:38 ` Marijn Suijten
2022-02-17 14:38 ` Marijn Suijten
2022-02-21 2:11 ` Dmitry Baryshkov
2022-02-21 2:11 ` Dmitry Baryshkov
2022-03-24 15:45 ` Vinod Koul
2022-03-24 15:45 ` Vinod Koul
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