From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CC9D0C433EF for ; Wed, 9 Feb 2022 15:32:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235894AbiBIPcT (ORCPT ); Wed, 9 Feb 2022 10:32:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232445AbiBIPcR (ORCPT ); Wed, 9 Feb 2022 10:32:17 -0500 Received: from casper.infradead.org (casper.infradead.org [IPv6:2001:8b0:10b:1236::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7997EC0613C9 for ; Wed, 9 Feb 2022 07:32:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=In-Reply-To:Content-Type:MIME-Version: References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=oxuCF8ORO1xTrKAEPMmkYDhqQTzVRv2K+VOvw4OGVgg=; b=W4DMCJz66PiUooHtfrPEvL90ss Ax7woRvg9pjNDajTAHEBNC8lHyL6v6sV5o8il3R5c3LneycYlJNFxMA/XPWcr3DnodMHtt5fl12bp ih4Q4JrTtejvcGMD+sU4JSsAkGuIvJX/r4xT9TrqGYz86kSxs+VOv0Kn9Pe3aGdBLeR0ISSONsVWY KWIi7xoqWBQIJsul4NbsST9rDj/IE4DxX5dOlox254DxVRCH8up8vMe3noWmmkZnUDxwQf6G+uadr Kx2w5sZfHbFHA6GjS7RebqMprUIg3XAv5dRO+TqugC+wGgW4mUGI5sva1oAwjBrTwk4ccynURoJtP 1nBy5u8A==; Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.94.2 #2 (Red Hat Linux)) id 1nHoww-0084fT-NQ; Wed, 09 Feb 2022 15:32:06 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 390C230075A; Wed, 9 Feb 2022 16:32:04 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 25A8F21075BA2; Wed, 9 Feb 2022 16:32:04 +0100 (CET) Date: Wed, 9 Feb 2022 16:32:04 +0100 From: Peter Zijlstra To: Stephane Eranian Cc: linux-kernel@vger.kernel.org, kim.phillips@amd.com, acme@redhat.com, jolsa@redhat.com, songliubraving@fb.com Subject: Re: [PATCH v6 06/12] perf/x86/amd: add AMD branch sampling period adjustment Message-ID: References: <20220208211637.2221872-1-eranian@google.com> <20220208211637.2221872-7-eranian@google.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220208211637.2221872-7-eranian@google.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Feb 08, 2022 at 01:16:31PM -0800, Stephane Eranian wrote: > Add code to adjust the sampling event period when used with the Branch > Sampling feature (BRS). Given the depth of the BRS (16), the period is > reduced by that depth such that in the best case scenario, BRS saturates at > the desired sampling period. In practice, though, the processor may execute > more branches. Given a desired period P and a depth D, the kernel programs > the actual period at P - D. After P occurrences of the sampling event, the > counter overflows. It then may take X branches (skid) before the NMI is > caught and held by the hardware and BRS activates. Then, after D branches, > BRS saturates and the NMI is delivered. With no skid, the effective period > would be (P - D) + D = P. In practice, however, it will likely be (P - D) + > X + D. There is no way to eliminate X or predict X. > > Signed-off-by: Stephane Eranian > --- > arch/x86/events/core.c | 7 +++++++ > arch/x86/events/perf_event.h | 12 ++++++++++++ > 2 files changed, 19 insertions(+) > > diff --git a/arch/x86/events/core.c b/arch/x86/events/core.c > index c2a890caeb0a..ed285f640efe 100644 > --- a/arch/x86/events/core.c > +++ b/arch/x86/events/core.c > @@ -1374,6 +1374,13 @@ int x86_perf_event_set_period(struct perf_event *event) > x86_pmu.set_topdown_event_period) > return x86_pmu.set_topdown_event_period(event); > > + /* > + * decrease period by the depth of the BRS feature to get > + * the last N taken branches and approximate the desired period > + */ > + if (has_branch_stack(event)) > + period = amd_brs_adjust_period(period); > + > /* > * If we are way outside a reasonable range then just skip forward: > */ > diff --git a/arch/x86/events/perf_event.h b/arch/x86/events/perf_event.h > index 3485a4cf0241..25b037b571e4 100644 > --- a/arch/x86/events/perf_event.h > +++ b/arch/x86/events/perf_event.h > @@ -1263,6 +1263,14 @@ static inline bool amd_brs_active(void) > return cpuc->brs_active; > } > > +static inline s64 amd_brs_adjust_period(s64 period) > +{ > + if (period > x86_pmu.lbr_nr) > + return period - x86_pmu.lbr_nr; > + > + return period; > +} This makes no sense to me without also enforcing that the event is in fact that branch retired thing.