[PATCH v8 0/4] clk: ralink: make system controller a reset provider

[PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

Hi all,

This patch series add minimal change to provide mt7621 resets properly
defining them in the 'mediatek,mt7621-sysc' node which is the system
controller of the SoC and is already providing clocks to the rest of
the world.

There is shared architecture code for all ralink platforms in 'reset.c'
file located in 'arch/mips/ralink' but the correct thing to do to align
hardware with software seems to define and add related reset code to the
already mainlined clock driver.

After this changes, we can get rid of the useless reset controller node
in the device tree and use system controller node instead where the property
'#reset-cells' has been added. Binding documentation for this nodeq has
been updated with the new property accordly.

This series also provide a bindings include header where all related
reset bits for the MT7621 SoC are defined.

Also, please take a look to this review [0] to understand better motivation
for this series.

Regarding the way of merging this:
 - I'd like patches 1 and 4 which are related going through staging tree.
 - The other two (patches 2 and 3) can perfectly go through the clock tree.

Thanks in advance for your feedback.

Changes in v8:
 - PATCH 3/4: with .of_xlate set, the driver needs to check whether id < nr_resets
   on its own.

Changes in v7:
 - PATCH 3/4: make use of '.of_xlate' callback as per Philipp v6 review.

Changes in v6:
 - Rebased on the top of last changes of staging-testing to properly
   update dtsi file (PATCH 4/4).
 - Send a copy of this to reset provider maintainer Philipp as per Stephen's sugestion
   to get changes added through the clk tree (Philipp, thanks in advance for reviewing
   this).

Changes in v5:
 - Move platform driver init process into 'arch_initcall' to be sure the
   rest of the world can get the resets available when needed (since PCIe
   controller driver has been moved from staging into 'drivers/pci/controller'
   is probed earlier and reset was not available so it was returning 
   -EPROBE_DEFER on firt try. Moving into 'arch_initcall' avoids the 'a bit
   anoying' PCI first failed log trace.

Changes in v4:
 - I sent wrong patch 3 accidentaly so now include the good version, sorry.

Changes in v3:
 - Collect Rob's Acked-by for patches 1 and 2. 
 - Rebase on the top of staging-next since there were already many
   changes there and PATCH 4 of the series didn't apply cleanly.

Changes in v2:
 - Address review comments of Dan Carpenter [1]:
 - Avoid 'inline' in function definition.
 - Return proper error codes (-EINVAL) instead of '-1'.
 - Make use of 'devm_kzalloc' instead of 'kzalloc'.

[0]: https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20210926145931.14603-3-sergio.paracuellos@gmail.com/

Best regards,
   Sergio Paracuellos

Sergio Paracuellos (4):
  dt-bindings: reset: add dt binding header for Mediatek MT7621 resets
  dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property
  clk: ralink: make system controller node a reset provider
  staging: mt7621-dts: align resets with binding documentation

 .../bindings/clock/mediatek,mt7621-sysc.yaml  | 12 +++
 drivers/clk/ralink/clk-mt7621.c               | 92 ++++++++++++++++++-
 drivers/staging/mt7621-dts/mt7621.dtsi        | 21 ++---
 include/dt-bindings/reset/mt7621-reset.h      | 37 ++++++++
 4 files changed, 149 insertions(+), 13 deletions(-)
 create mode 100644 include/dt-bindings/reset/mt7621-reset.h

-- 
2.25.1

[PATCH v8 1/4] dt-bindings: reset: add dt binding header for Mediatek MT7621 resets

[Sergio Paracuellos]

Add dt binding header for resets lines in Mediatek MT7621 SoCs.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 include/dt-bindings/reset/mt7621-reset.h | 37 ++++++++++++++++++++++++
 1 file changed, 37 insertions(+)
 create mode 100644 include/dt-bindings/reset/mt7621-reset.h

diff --git a/include/dt-bindings/reset/mt7621-reset.h b/include/dt-bindings/reset/mt7621-reset.h
new file mode 100644
index 000000000000..7572c6b41453
--- /dev/null
+++ b/include/dt-bindings/reset/mt7621-reset.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (c) 2021 Sergio Paracuellos
+ * Author: Sergio Paracuellos <sergio.paracuellos@gmail.com>
+ */
+
+#ifndef DT_BINDING_MT7621_RESET_H
+#define DT_BINDING_MT7621_RESET_H
+
+#define MT7621_RST_SYS		0
+#define MT7621_RST_MCM		2
+#define MT7621_RST_HSDMA	5
+#define MT7621_RST_FE		6
+#define MT7621_RST_SPDIFTX	7
+#define MT7621_RST_TIMER	8
+#define MT7621_RST_INT		9
+#define MT7621_RST_MC		10
+#define MT7621_RST_PCM		11
+#define MT7621_RST_PIO		13
+#define MT7621_RST_GDMA		14
+#define MT7621_RST_NFI		15
+#define MT7621_RST_I2C		16
+#define MT7621_RST_I2S		17
+#define MT7621_RST_SPI		18
+#define MT7621_RST_UART1	19
+#define MT7621_RST_UART2	20
+#define MT7621_RST_UART3	21
+#define MT7621_RST_ETH		23
+#define MT7621_RST_PCIE0	24
+#define MT7621_RST_PCIE1	25
+#define MT7621_RST_PCIE2	26
+#define MT7621_RST_AUX_STCK	28
+#define MT7621_RST_CRYPTO	29
+#define MT7621_RST_SDXC		30
+#define MT7621_RST_PPE		31
+
+#endif /* DT_BINDING_MT7621_RESET_H */
-- 
2.25.1

[PATCH v8 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property

[Sergio Paracuellos]

Make system controller a reset provider for all the peripherals in the
MT7621 SoC adding '#reset-cells' property.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 .../bindings/clock/mediatek,mt7621-sysc.yaml         | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
index 915f84efd763..0c0b0ae5e2ac 100644
--- a/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
+++ b/Documentation/devicetree/bindings/clock/mediatek,mt7621-sysc.yaml
@@ -22,6 +22,11 @@ description: |
 
   The clocks are provided inside a system controller node.
 
+  This node is also a reset provider for all the peripherals.
+
+  Reset related bits are defined in:
+  [2]: <include/dt-bindings/reset/mt7621-reset.h>.
+
 properties:
   compatible:
     items:
@@ -37,6 +42,12 @@ properties:
       clocks.
     const: 1
 
+  "#reset-cells":
+    description:
+      The first cell indicates the reset bit within the register, see
+      [2] for available resets.
+    const: 1
+
   ralink,memctl:
     $ref: /schemas/types.yaml#/definitions/phandle
     description:
@@ -61,6 +72,7 @@ examples:
       compatible = "mediatek,mt7621-sysc", "syscon";
       reg = <0x0 0x100>;
       #clock-cells = <1>;
+      #reset-cells = <1>;
       ralink,memctl = <&memc>;
       clock-output-names = "xtal", "cpu", "bus",
                            "50m", "125m", "150m",
-- 
2.25.1

[PATCH v8 3/4] clk: ralink: make system controller node a reset provider

[Sergio Paracuellos]

MT7621 system controller node is already providing the clocks for the whole
system but must also serve as a reset provider. Hence, add reset controller
related code to the clock driver itself. To get resets properly ready for
the rest of the world we need to move platform driver initialization process
to 'arch_initcall'.

CC: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++-
 1 file changed, 91 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
index a2c045390f00..99256659dd96 100644
--- a/drivers/clk/ralink/clk-mt7621.c
+++ b/drivers/clk/ralink/clk-mt7621.c
@@ -11,14 +11,17 @@
 #include <linux/mfd/syscon.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/reset-controller.h>
 #include <linux/slab.h>
 #include <dt-bindings/clock/mt7621-clk.h>
+#include <dt-bindings/reset/mt7621-reset.h>
 
 /* Configuration registers */
 #define SYSC_REG_SYSTEM_CONFIG0         0x10
 #define SYSC_REG_SYSTEM_CONFIG1         0x14
 #define SYSC_REG_CLKCFG0		0x2c
 #define SYSC_REG_CLKCFG1		0x30
+#define SYSC_REG_RESET_CTRL		0x34
 #define SYSC_REG_CUR_CLK_STS		0x44
 #define MEMC_REG_CPU_PLL		0x648
 
@@ -398,6 +401,82 @@ static void __init mt7621_clk_init(struct device_node *node)
 }
 CLK_OF_DECLARE_DRIVER(mt7621_clk, "mediatek,mt7621-sysc", mt7621_clk_init);
 
+struct mt7621_rst {
+	struct reset_controller_dev rcdev;
+	struct regmap *sysc;
+};
+
+static struct mt7621_rst *to_mt7621_rst(struct reset_controller_dev *dev)
+{
+	return container_of(dev, struct mt7621_rst, rcdev);
+}
+
+static int mt7621_assert_device(struct reset_controller_dev *rcdev,
+				unsigned long id)
+{
+	struct mt7621_rst *data = to_mt7621_rst(rcdev);
+	struct regmap *sysc = data->sysc;
+
+	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), BIT(id));
+}
+
+static int mt7621_deassert_device(struct reset_controller_dev *rcdev,
+				  unsigned long id)
+{
+	struct mt7621_rst *data = to_mt7621_rst(rcdev);
+	struct regmap *sysc = data->sysc;
+
+	return regmap_update_bits(sysc, SYSC_REG_RESET_CTRL, BIT(id), 0);
+}
+
+static int mt7621_reset_device(struct reset_controller_dev *rcdev,
+			       unsigned long id)
+{
+	int ret;
+
+	ret = mt7621_assert_device(rcdev, id);
+	if (ret < 0)
+		return ret;
+
+	return mt7621_deassert_device(rcdev, id);
+}
+
+static int mt7621_rst_xlate(struct reset_controller_dev *rcdev,
+			    const struct of_phandle_args *reset_spec)
+{
+	unsigned long id = reset_spec->args[0];
+
+	if (id == MT7621_RST_SYS || id >= rcdev->nr_resets)
+		return -EINVAL;
+
+	return id;
+}
+
+static const struct reset_control_ops reset_ops = {
+	.reset = mt7621_reset_device,
+	.assert = mt7621_assert_device,
+	.deassert = mt7621_deassert_device
+};
+
+static int mt7621_reset_init(struct device *dev, struct regmap *sysc)
+{
+	struct mt7621_rst *rst_data;
+
+	rst_data = devm_kzalloc(dev, sizeof(*rst_data), GFP_KERNEL);
+	if (!rst_data)
+		return -ENOMEM;
+
+	rst_data->sysc = sysc;
+	rst_data->rcdev.ops = &reset_ops;
+	rst_data->rcdev.owner = THIS_MODULE;
+	rst_data->rcdev.nr_resets = 32;
+	rst_data->rcdev.of_reset_n_cells = 1;
+	rst_data->rcdev.of_xlate = mt7621_rst_xlate;
+	rst_data->rcdev.of_node = dev_of_node(dev);
+
+	return devm_reset_controller_register(dev, &rst_data->rcdev);
+}
+
 static int mt7621_clk_probe(struct platform_device *pdev)
 {
 	struct device_node *np = pdev->dev.of_node;
@@ -424,6 +503,12 @@ static int mt7621_clk_probe(struct platform_device *pdev)
 		return ret;
 	}
 
+	ret = mt7621_reset_init(dev, priv->sysc);
+	if (ret) {
+		dev_err(dev, "Could not init reset controller\n");
+		return ret;
+	}
+
 	count = ARRAY_SIZE(mt7621_clks_base) +
 		ARRAY_SIZE(mt7621_fixed_clks) + ARRAY_SIZE(mt7621_gates);
 	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, count),
@@ -485,4 +570,9 @@ static struct platform_driver mt7621_clk_driver = {
 		.of_match_table = mt7621_clk_of_match,
 	},
 };
-builtin_platform_driver(mt7621_clk_driver);
+
+static int __init mt7621_clk_reset_init(void)
+{
+	return platform_driver_register(&mt7621_clk_driver);
+}
+arch_initcall(mt7621_clk_reset_init);
-- 
2.25.1

[PATCH v8 4/4] staging: mt7621-dts: align resets with binding documentation

[Sergio Paracuellos]

Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
to be used as a reset provider. Align reset related bits and system controller
node with binding documentation along the dtsi file.

Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
 drivers/staging/mt7621-dts/mt7621.dtsi | 21 +++++++++------------
 1 file changed, 9 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 644a65d1a6a1..d72673c91dc2 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -2,6 +2,7 @@
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/clock/mt7621-clk.h>
+#include <dt-bindings/reset/mt7621-reset.h>
 
 / {
 	#address-cells = <1>;
@@ -67,6 +68,7 @@ sysc: syscon@0 {
 			compatible = "mediatek,mt7621-sysc", "syscon";
 			reg = <0x0 0x100>;
 			#clock-cells = <1>;
+			#reset-cells = <1>;
 			ralink,memctl = <&memc>;
 			clock-output-names = "xtal", "cpu", "bus",
 					     "50m", "125m", "150m",
@@ -96,7 +98,7 @@ i2c: i2c@900 {
 
 			clocks = <&sysc MT7621_CLK_I2C>;
 			clock-names = "i2c";
-			resets = <&rstctrl 16>;
+			resets = <&sysc MT7621_RST_I2C>;
 			reset-names = "i2c";
 
 			#address-cells = <1>;
@@ -137,7 +139,7 @@ spi0: spi@b00 {
 			clocks = <&sysc MT7621_CLK_SPI>;
 			clock-names = "spi";
 
-			resets = <&rstctrl 18>;
+			resets = <&sysc MT7621_RST_SPI>;
 			reset-names = "spi";
 
 			#address-cells = <1>;
@@ -234,11 +236,6 @@ pinmux {
 		};
 	};
 
-	rstctrl: rstctrl {
-		compatible = "ralink,rt2880-reset";
-		#reset-cells = <1>;
-	};
-
 	sdhci: sdhci@1e130000 {
 		status = "disabled";
 
@@ -317,7 +314,7 @@ ethernet: ethernet@1e100000 {
 		#address-cells = <1>;
 		#size-cells = <0>;
 
-		resets = <&rstctrl 6 &rstctrl 23>;
+		resets = <&sysc MT7621_RST_FE &sysc MT7621_RST_ETH>;
 		reset-names = "fe", "eth";
 
 		interrupt-parent = <&gic>;
@@ -362,7 +359,7 @@ switch0: switch0@0 {
 				#size-cells = <0>;
 				reg = <0>;
 				mediatek,mcm;
-				resets = <&rstctrl 2>;
+				resets = <&sysc MT7621_RST_MCM>;
 				reset-names = "mcm";
 				interrupt-controller;
 				#interrupt-cells = <1>;
@@ -448,7 +445,7 @@ pcie@0,0 {
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rstctrl 24>;
+			resets = <&sysc MT7621_RST_PCIE0>;
 			clocks = <&sysc MT7621_CLK_PCIE0>;
 			phys = <&pcie0_phy 1>;
 			phy-names = "pcie-phy0";
@@ -463,7 +460,7 @@ pcie@1,0 {
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rstctrl 25>;
+			resets = <&sysc MT7621_RST_PCIE1>;
 			clocks = <&sysc MT7621_CLK_PCIE1>;
 			phys = <&pcie0_phy 1>;
 			phy-names = "pcie-phy1";
@@ -478,7 +475,7 @@ pcie@2,0 {
 			#interrupt-cells = <1>;
 			interrupt-map-mask = <0 0 0 0>;
 			interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-			resets = <&rstctrl 26>;
+			resets = <&sysc MT7621_RST_PCIE2>;
 			clocks = <&sysc MT7621_CLK_PCIE2>;
 			phys = <&pcie2_phy 0>;
 			phy-names = "pcie-phy2";
-- 
2.25.1

Re: [PATCH v8 3/4] clk: ralink: make system controller node a reset provider

[Philipp Zabel]

On Mon, 2022-01-10 at 12:49 +0100, Sergio Paracuellos wrote:
> MT7621 system controller node is already providing the clocks for the whole
> system but must also serve as a reset provider. Hence, add reset controller
> related code to the clock driver itself. To get resets properly ready for
> the rest of the world we need to move platform driver initialization process
> to 'arch_initcall'.
> 
> CC: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

Re: [PATCH v8 4/4] staging: mt7621-dts: align resets with binding documentation

[Philipp Zabel]

On Mon, 2022-01-10 at 12:49 +0100, Sergio Paracuellos wrote:
> Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
> to be used as a reset provider. Align reset related bits and system controller
> node with binding documentation along the dtsi file.
> 
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>

Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>

regards
Philipp

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Arınç ÜNAL]

This series fixes the SPI & MDIO probing issues we were having with our 
mt7621 board.

Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>

Cheers.
Arınç

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

On Wed, Jan 19, 2022 at 2:27 PM Arınç ÜNAL <arinc.unal@arinc9.com> wrote:
>
> This series fixes the SPI & MDIO probing issues we were having with our
> mt7621 board.
>
> Tested-by: Arınç ÜNAL <arinc.unal@arinc9.com>

Thanks for testing this!

Best regards,
    Sergio Paracuellos
>
> Cheers.
> Arınç
>

Re: [PATCH v8 2/4] dt-bindings: clock: mediatek,mt7621-sysc: add '#reset-cells' property

[Stephen Boyd]

Quoting Sergio Paracuellos (2022-01-10 03:49:28)
> Make system controller a reset provider for all the peripherals in the
> MT7621 SoC adding '#reset-cells' property.
> 
> Acked-by: Rob Herring <robh@kernel.org>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---

Applied to clk-next

Re: [PATCH v8 3/4] clk: ralink: make system controller node a reset provider

[Stephen Boyd]

Quoting Sergio Paracuellos (2022-01-10 03:49:29)
> MT7621 system controller node is already providing the clocks for the whole
> system but must also serve as a reset provider. Hence, add reset controller
> related code to the clock driver itself. To get resets properly ready for
> the rest of the world we need to move platform driver initialization process
> to 'arch_initcall'.
> 
> CC: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---

Applied to clk-next

Re: [PATCH v8 3/4] clk: ralink: make system controller node a reset provider

[Stephen Boyd]

Quoting Sergio Paracuellos (2022-01-10 03:49:29)
> MT7621 system controller node is already providing the clocks for the whole
> system but must also serve as a reset provider. Hence, add reset controller
> related code to the clock driver itself. To get resets properly ready for
> the rest of the world we need to move platform driver initialization process
> to 'arch_initcall'.
> 
> CC: Philipp Zabel <p.zabel@pengutronix.de>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
>  drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++-
>  1 file changed, 91 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
> index a2c045390f00..99256659dd96 100644
> --- a/drivers/clk/ralink/clk-mt7621.c
> +++ b/drivers/clk/ralink/clk-mt7621.c
> @@ -11,14 +11,17 @@
>  #include <linux/mfd/syscon.h>
>  #include <linux/platform_device.h>
>  #include <linux/regmap.h>
> +#include <linux/reset-controller.h>
>  #include <linux/slab.h>
>  #include <dt-bindings/clock/mt7621-clk.h>
> +#include <dt-bindings/reset/mt7621-reset.h>

I can't take this patch without taking the first patch. I suppose if
Greg is OK I can take the staging patch #4 through clk tree too? Let me
know.

Re: [PATCH v8 3/4] clk: ralink: make system controller node a reset provider

[Sergio Paracuellos]

On Tue, Jan 25, 2022 at 2:14 AM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Sergio Paracuellos (2022-01-10 03:49:29)
> > MT7621 system controller node is already providing the clocks for the whole
> > system but must also serve as a reset provider. Hence, add reset controller
> > related code to the clock driver itself. To get resets properly ready for
> > the rest of the world we need to move platform driver initialization process
> > to 'arch_initcall'.
> >
> > CC: Philipp Zabel <p.zabel@pengutronix.de>
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> > ---
> >  drivers/clk/ralink/clk-mt7621.c | 92 ++++++++++++++++++++++++++++++++-
> >  1 file changed, 91 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/clk/ralink/clk-mt7621.c b/drivers/clk/ralink/clk-mt7621.c
> > index a2c045390f00..99256659dd96 100644
> > --- a/drivers/clk/ralink/clk-mt7621.c
> > +++ b/drivers/clk/ralink/clk-mt7621.c
> > @@ -11,14 +11,17 @@
> >  #include <linux/mfd/syscon.h>
> >  #include <linux/platform_device.h>
> >  #include <linux/regmap.h>
> > +#include <linux/reset-controller.h>
> >  #include <linux/slab.h>
> >  #include <dt-bindings/clock/mt7621-clk.h>
> > +#include <dt-bindings/reset/mt7621-reset.h>
>
> I can't take this patch without taking the first patch. I suppose if
> Greg is OK I can take the staging patch #4 through clk tree too? Let me
> know.

Greg, can you Ack patch 4 of the series to get all applied through CLK tree?

Thanks!

Best regards,
    Sergio Paracuellos

Re: [PATCH v8 4/4] staging: mt7621-dts: align resets with binding documentation

[Sergio Paracuellos]

Hi Greg,

On Mon, Jan 10, 2022 at 12:54 PM Philipp Zabel <p.zabel@pengutronix.de> wrote:
>
> On Mon, 2022-01-10 at 12:49 +0100, Sergio Paracuellos wrote:
> > Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
> > to be used as a reset provider. Align reset related bits and system controller
> > node with binding documentation along the dtsi file.
> >
> > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
>
> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
>
> regards
> Philipp

Can I get your Acked-by on this patch to apply this series through the clk tree?

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Greg KH]

On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> Hi all,
> 
> This patch series add minimal change to provide mt7621 resets properly
> defining them in the 'mediatek,mt7621-sysc' node which is the system
> controller of the SoC and is already providing clocks to the rest of
> the world.
> 
> There is shared architecture code for all ralink platforms in 'reset.c'
> file located in 'arch/mips/ralink' but the correct thing to do to align
> hardware with software seems to define and add related reset code to the
> already mainlined clock driver.
> 
> After this changes, we can get rid of the useless reset controller node
> in the device tree and use system controller node instead where the property
> '#reset-cells' has been added. Binding documentation for this nodeq has
> been updated with the new property accordly.
> 
> This series also provide a bindings include header where all related
> reset bits for the MT7621 SoC are defined.
> 
> Also, please take a look to this review [0] to understand better motivation
> for this series.
> 
> Regarding the way of merging this:
>  - I'd like patches 1 and 4 which are related going through staging tree.

Patches 1 and 4 now in the staging tree, thanks.

greg k-h

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > Hi all,
> >
> > This patch series add minimal change to provide mt7621 resets properly
> > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > controller of the SoC and is already providing clocks to the rest of
> > the world.
> >
> > There is shared architecture code for all ralink platforms in 'reset.c'
> > file located in 'arch/mips/ralink' but the correct thing to do to align
> > hardware with software seems to define and add related reset code to the
> > already mainlined clock driver.
> >
> > After this changes, we can get rid of the useless reset controller node
> > in the device tree and use system controller node instead where the property
> > '#reset-cells' has been added. Binding documentation for this nodeq has
> > been updated with the new property accordly.
> >
> > This series also provide a bindings include header where all related
> > reset bits for the MT7621 SoC are defined.
> >
> > Also, please take a look to this review [0] to understand better motivation
> > for this series.
> >
> > Regarding the way of merging this:
> >  - I'd like patches 1 and 4 which are related going through staging tree.
>
> Patches 1 and 4 now in the staging tree, thanks.

Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
also a dependency... Can we get all of them through the same tree,
then? I am ok with both CLK or staging trees.

Thanks,
    Sergio Paracuellos
>
> greg k-h
>

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Greg KH]

On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > Hi all,
> > >
> > > This patch series add minimal change to provide mt7621 resets properly
> > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > controller of the SoC and is already providing clocks to the rest of
> > > the world.
> > >
> > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > hardware with software seems to define and add related reset code to the
> > > already mainlined clock driver.
> > >
> > > After this changes, we can get rid of the useless reset controller node
> > > in the device tree and use system controller node instead where the property
> > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > been updated with the new property accordly.
> > >
> > > This series also provide a bindings include header where all related
> > > reset bits for the MT7621 SoC are defined.
> > >
> > > Also, please take a look to this review [0] to understand better motivation
> > > for this series.
> > >
> > > Regarding the way of merging this:
> > >  - I'd like patches 1 and 4 which are related going through staging tree.
> >
> > Patches 1 and 4 now in the staging tree, thanks.
> 
> Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> also a dependency... Can we get all of them through the same tree,
> then? I am ok with both CLK or staging trees.

That's fine with me if they all go through the CLK tree, but there will
be a merge issue that I already fixed up in my tree.  If you want me to
drop them, just let me know.

thanks,

greg k-h

Re: [PATCH v8 4/4] staging: mt7621-dts: align resets with binding documentation

[Greg KH]

On Wed, Jan 26, 2022 at 12:46:43PM +0100, Sergio Paracuellos wrote:
> Hi Greg,
> 
> On Mon, Jan 10, 2022 at 12:54 PM Philipp Zabel <p.zabel@pengutronix.de> wrote:
> >
> > On Mon, 2022-01-10 at 12:49 +0100, Sergio Paracuellos wrote:
> > > Binding documentation for compatible 'mediatek,mt7621-sysc' has been updated
> > > to be used as a reset provider. Align reset related bits and system controller
> > > node with binding documentation along the dtsi file.
> > >
> > > Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> >
> > Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
> >
> > regards
> > Philipp
> 
> Can I get your Acked-by on this patch to apply this series through the clk tree?

Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > >
> > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > Hi all,
> > > >
> > > > This patch series add minimal change to provide mt7621 resets properly
> > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > controller of the SoC and is already providing clocks to the rest of
> > > > the world.
> > > >
> > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > hardware with software seems to define and add related reset code to the
> > > > already mainlined clock driver.
> > > >
> > > > After this changes, we can get rid of the useless reset controller node
> > > > in the device tree and use system controller node instead where the property
> > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > been updated with the new property accordly.
> > > >
> > > > This series also provide a bindings include header where all related
> > > > reset bits for the MT7621 SoC are defined.
> > > >
> > > > Also, please take a look to this review [0] to understand better motivation
> > > > for this series.
> > > >
> > > > Regarding the way of merging this:
> > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > >
> > > Patches 1 and 4 now in the staging tree, thanks.
> >
> > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > also a dependency... Can we get all of them through the same tree,
> > then? I am ok with both CLK or staging trees.
>
> That's fine with me if they all go through the CLK tree, but there will
> be a merge issue that I already fixed up in my tree.  If you want me to
> drop them, just let me know.

Stephen, what do you prefer? Is it better all going through staging-tree then?

Best regards,
    Sergio Paracuellos
>
> thanks,
>
> greg k-h

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Stephen Boyd]

Quoting Sergio Paracuellos (2022-01-26 04:45:31)
> On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> >
> > On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > >
> > > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > > Hi all,
> > > > >
> > > > > This patch series add minimal change to provide mt7621 resets properly
> > > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > > controller of the SoC and is already providing clocks to the rest of
> > > > > the world.
> > > > >
> > > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > > hardware with software seems to define and add related reset code to the
> > > > > already mainlined clock driver.
> > > > >
> > > > > After this changes, we can get rid of the useless reset controller node
> > > > > in the device tree and use system controller node instead where the property
> > > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > > been updated with the new property accordly.
> > > > >
> > > > > This series also provide a bindings include header where all related
> > > > > reset bits for the MT7621 SoC are defined.
> > > > >
> > > > > Also, please take a look to this review [0] to understand better motivation
> > > > > for this series.
> > > > >
> > > > > Regarding the way of merging this:
> > > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > > >
> > > > Patches 1 and 4 now in the staging tree, thanks.
> > >
> > > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > > also a dependency... Can we get all of them through the same tree,
> > > then? I am ok with both CLK or staging trees.
> >
> > That's fine with me if they all go through the CLK tree, but there will
> > be a merge issue that I already fixed up in my tree.  If you want me to
> > drop them, just let me know.
> 
> Stephen, what do you prefer? Is it better all going through staging-tree then?
> 

Sure take them through staging tree.

Acked-by: Stephen Boyd <sboyd@kernel.org>

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

On Sat, Feb 5, 2022 at 3:55 AM Stephen Boyd <sboyd@kernel.org> wrote:
>
> Quoting Sergio Paracuellos (2022-01-26 04:45:31)
> > On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > >
> > > On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > > > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > >
> > > > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > > > Hi all,
> > > > > >
> > > > > > This patch series add minimal change to provide mt7621 resets properly
> > > > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > > > controller of the SoC and is already providing clocks to the rest of
> > > > > > the world.
> > > > > >
> > > > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > > > hardware with software seems to define and add related reset code to the
> > > > > > already mainlined clock driver.
> > > > > >
> > > > > > After this changes, we can get rid of the useless reset controller node
> > > > > > in the device tree and use system controller node instead where the property
> > > > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > > > been updated with the new property accordly.
> > > > > >
> > > > > > This series also provide a bindings include header where all related
> > > > > > reset bits for the MT7621 SoC are defined.
> > > > > >
> > > > > > Also, please take a look to this review [0] to understand better motivation
> > > > > > for this series.
> > > > > >
> > > > > > Regarding the way of merging this:
> > > > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > > > >
> > > > > Patches 1 and 4 now in the staging tree, thanks.
> > > >
> > > > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > > > also a dependency... Can we get all of them through the same tree,
> > > > then? I am ok with both CLK or staging trees.
> > >
> > > That's fine with me if they all go through the CLK tree, but there will
> > > be a merge issue that I already fixed up in my tree.  If you want me to
> > > drop them, just let me know.
> >
> > Stephen, what do you prefer? Is it better all going through staging-tree then?
> >
>
> Sure take them through staging tree.
>
> Acked-by: Stephen Boyd <sboyd@kernel.org>

Thanks, Stephen.

Greg, can you please take remaining patches 2 and 3 through your tree, then?

Thanks in advance for your time.

Best regards,
    Sergio Paracuellos

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

Hi Greg,

On Sat, Feb 5, 2022 at 8:31 AM Sergio Paracuellos
<sergio.paracuellos@gmail.com> wrote:
>
> On Sat, Feb 5, 2022 at 3:55 AM Stephen Boyd <sboyd@kernel.org> wrote:
> >
> > Quoting Sergio Paracuellos (2022-01-26 04:45:31)
> > > On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > >
> > > > On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > > > > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > > >
> > > > > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > > > > Hi all,
> > > > > > >
> > > > > > > This patch series add minimal change to provide mt7621 resets properly
> > > > > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > > > > controller of the SoC and is already providing clocks to the rest of
> > > > > > > the world.
> > > > > > >
> > > > > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > > > > hardware with software seems to define and add related reset code to the
> > > > > > > already mainlined clock driver.
> > > > > > >
> > > > > > > After this changes, we can get rid of the useless reset controller node
> > > > > > > in the device tree and use system controller node instead where the property
> > > > > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > > > > been updated with the new property accordly.
> > > > > > >
> > > > > > > This series also provide a bindings include header where all related
> > > > > > > reset bits for the MT7621 SoC are defined.
> > > > > > >
> > > > > > > Also, please take a look to this review [0] to understand better motivation
> > > > > > > for this series.
> > > > > > >
> > > > > > > Regarding the way of merging this:
> > > > > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > > > > >
> > > > > > Patches 1 and 4 now in the staging tree, thanks.
> > > > >
> > > > > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > > > > also a dependency... Can we get all of them through the same tree,
> > > > > then? I am ok with both CLK or staging trees.
> > > >
> > > > That's fine with me if they all go through the CLK tree, but there will
> > > > be a merge issue that I already fixed up in my tree.  If you want me to
> > > > drop them, just let me know.
> > >
> > > Stephen, what do you prefer? Is it better all going through staging-tree then?
> > >
> >
> > Sure take them through staging tree.
> >
> > Acked-by: Stephen Boyd <sboyd@kernel.org>
>
> Thanks, Stephen.
>
> Greg, can you please take remaining patches 2 and 3 through your tree, then?
>
> Thanks in advance for your time.

Please, let me know if you prefer me to resend the remaining two
patches with tags added to make this easier for you.

Best regards,
    Sergio Paracuellos

>
> Best regards,
>     Sergio Paracuellos

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Greg KH]

On Thu, Feb 10, 2022 at 07:44:33AM +0100, Sergio Paracuellos wrote:
> Hi Greg,
> 
> On Sat, Feb 5, 2022 at 8:31 AM Sergio Paracuellos
> <sergio.paracuellos@gmail.com> wrote:
> >
> > On Sat, Feb 5, 2022 at 3:55 AM Stephen Boyd <sboyd@kernel.org> wrote:
> > >
> > > Quoting Sergio Paracuellos (2022-01-26 04:45:31)
> > > > On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > >
> > > > > On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > > > > > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > > > >
> > > > > > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > > > > > Hi all,
> > > > > > > >
> > > > > > > > This patch series add minimal change to provide mt7621 resets properly
> > > > > > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > > > > > controller of the SoC and is already providing clocks to the rest of
> > > > > > > > the world.
> > > > > > > >
> > > > > > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > > > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > > > > > hardware with software seems to define and add related reset code to the
> > > > > > > > already mainlined clock driver.
> > > > > > > >
> > > > > > > > After this changes, we can get rid of the useless reset controller node
> > > > > > > > in the device tree and use system controller node instead where the property
> > > > > > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > > > > > been updated with the new property accordly.
> > > > > > > >
> > > > > > > > This series also provide a bindings include header where all related
> > > > > > > > reset bits for the MT7621 SoC are defined.
> > > > > > > >
> > > > > > > > Also, please take a look to this review [0] to understand better motivation
> > > > > > > > for this series.
> > > > > > > >
> > > > > > > > Regarding the way of merging this:
> > > > > > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > > > > > >
> > > > > > > Patches 1 and 4 now in the staging tree, thanks.
> > > > > >
> > > > > > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > > > > > also a dependency... Can we get all of them through the same tree,
> > > > > > then? I am ok with both CLK or staging trees.
> > > > >
> > > > > That's fine with me if they all go through the CLK tree, but there will
> > > > > be a merge issue that I already fixed up in my tree.  If you want me to
> > > > > drop them, just let me know.
> > > >
> > > > Stephen, what do you prefer? Is it better all going through staging-tree then?
> > > >
> > >
> > > Sure take them through staging tree.
> > >
> > > Acked-by: Stephen Boyd <sboyd@kernel.org>
> >
> > Thanks, Stephen.
> >
> > Greg, can you please take remaining patches 2 and 3 through your tree, then?
> >
> > Thanks in advance for your time.
> 
> Please, let me know if you prefer me to resend the remaining two
> patches with tags added to make this easier for you.

Please do so, as I can't seem to dig up the remaining ones...

thanks,

greg k-h

Re: [PATCH v8 0/4] clk: ralink: make system controller a reset provider

[Sergio Paracuellos]

On Thu, Feb 10, 2022 at 7:55 AM Greg KH <gregkh@linuxfoundation.org> wrote:
>
> On Thu, Feb 10, 2022 at 07:44:33AM +0100, Sergio Paracuellos wrote:
> > Hi Greg,
> >
> > On Sat, Feb 5, 2022 at 8:31 AM Sergio Paracuellos
> > <sergio.paracuellos@gmail.com> wrote:
> > >
> > > On Sat, Feb 5, 2022 at 3:55 AM Stephen Boyd <sboyd@kernel.org> wrote:
> > > >
> > > > Quoting Sergio Paracuellos (2022-01-26 04:45:31)
> > > > > On Wed, Jan 26, 2022 at 1:14 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > > >
> > > > > > On Wed, Jan 26, 2022 at 01:08:52PM +0100, Sergio Paracuellos wrote:
> > > > > > > On Wed, Jan 26, 2022 at 1:06 PM Greg KH <gregkh@linuxfoundation.org> wrote:
> > > > > > > >
> > > > > > > > On Mon, Jan 10, 2022 at 12:49:26PM +0100, Sergio Paracuellos wrote:
> > > > > > > > > Hi all,
> > > > > > > > >
> > > > > > > > > This patch series add minimal change to provide mt7621 resets properly
> > > > > > > > > defining them in the 'mediatek,mt7621-sysc' node which is the system
> > > > > > > > > controller of the SoC and is already providing clocks to the rest of
> > > > > > > > > the world.
> > > > > > > > >
> > > > > > > > > There is shared architecture code for all ralink platforms in 'reset.c'
> > > > > > > > > file located in 'arch/mips/ralink' but the correct thing to do to align
> > > > > > > > > hardware with software seems to define and add related reset code to the
> > > > > > > > > already mainlined clock driver.
> > > > > > > > >
> > > > > > > > > After this changes, we can get rid of the useless reset controller node
> > > > > > > > > in the device tree and use system controller node instead where the property
> > > > > > > > > '#reset-cells' has been added. Binding documentation for this nodeq has
> > > > > > > > > been updated with the new property accordly.
> > > > > > > > >
> > > > > > > > > This series also provide a bindings include header where all related
> > > > > > > > > reset bits for the MT7621 SoC are defined.
> > > > > > > > >
> > > > > > > > > Also, please take a look to this review [0] to understand better motivation
> > > > > > > > > for this series.
> > > > > > > > >
> > > > > > > > > Regarding the way of merging this:
> > > > > > > > >  - I'd like patches 1 and 4 which are related going through staging tree.
> > > > > > > >
> > > > > > > > Patches 1 and 4 now in the staging tree, thanks.
> > > > > > >
> > > > > > > Stephen wanted all to go through the CLK tree since PATCH 3 and 1 were
> > > > > > > also a dependency... Can we get all of them through the same tree,
> > > > > > > then? I am ok with both CLK or staging trees.
> > > > > >
> > > > > > That's fine with me if they all go through the CLK tree, but there will
> > > > > > be a merge issue that I already fixed up in my tree.  If you want me to
> > > > > > drop them, just let me know.
> > > > >
> > > > > Stephen, what do you prefer? Is it better all going through staging-tree then?
> > > > >
> > > >
> > > > Sure take them through staging tree.
> > > >
> > > > Acked-by: Stephen Boyd <sboyd@kernel.org>
> > >
> > > Thanks, Stephen.
> > >
> > > Greg, can you please take remaining patches 2 and 3 through your tree, then?
> > >
> > > Thanks in advance for your time.
> >
> > Please, let me know if you prefer me to resend the remaining two
> > patches with tags added to make this easier for you.
>
> Please do so, as I can't seem to dig up the remaining ones...

Ok, done. Please check:
https://lore.kernel.org/linux-staging/20220210094859.927868-1-sergio.paracuellos@gmail.com/T/#t

Best regards,
    Sergio Paracuellos

>
> thanks,
>
> greg k-h