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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?e8eSHCKVV/67KFUw563JUHUw6jcuIGQKNcNE7I1rpf2eggBKKPCHHejVayqz?= =?us-ascii?Q?2gM5uh8Ub8ophZ7mu4/Uf7D0P3musFIV+VZVsmzb8hlLJFS0203XA0aVVxRW?= =?us-ascii?Q?P6atRv2OCCTaY1OjdJwWmwqQedgUMArs+4msNjgNfTFhGUoDGCRXcocILGsZ?= =?us-ascii?Q?Ac13F5nRpEgf5Q0q0LEkosrrPLUrzbV23s9Q0P/Chexsu4/i3dYlU4AqOSXL?= =?us-ascii?Q?AIuLJ/d3m0tgtwnpn1LtJkEXUlnP4t/MKyvk3ssgE+HKYgvhErASzl4Ibhq2?= =?us-ascii?Q?t3rw5RVQGITMlocJ3YB1iukeyOOYYwDu0iJ2H9qv7Of1+dnrX1zc2eVQBKgE?= =?us-ascii?Q?Vx/uAp160lc43DXZ/olCz0CIVP2iTil00twQ/12KGcCr0QyEZt6GhBrqqknw?= =?us-ascii?Q?WA1zKsxPJ3UAkaPehraE/NuQjELbC/yQQ1L0bYoDXvCFL03MMYXdfX306jcf?= =?us-ascii?Q?e+f6G/cUgBQGmeSNfaD7BGPLNL2KYIqXc9qFdkQBkFFPiT+tmO/3xbOM04zj?= =?us-ascii?Q?gCULj2xsH2dTyTUNS+mpcjYL50deeZPZSsTwSeDNi5QlB9elLxsweDN5GzEP?= =?us-ascii?Q?Xf1QbTUd0aFun8AgoNnjY2POp1G3CvN6Qo8OYYqZ+dZ1I/sqJyVuY+MFL1tI?= =?us-ascii?Q?8iDheNHxLPQsGRdmtqVud1TjN4gFH9+091ULzGkwSYQaYMqCpcY3okFD0Ilr?= =?us-ascii?Q?5LBBCSUdbh/j/8s1A9a/52eEUh0JYiZ/Estqqml3tBR+xiKVSPU9ftcGGn2t?= =?us-ascii?Q?cMeN6RyL4HD3y4c/WoAu1cbj+JQgG2yO5qw540obysP9nwA5VSDKB2lsWWaO?= =?us-ascii?Q?0DF/+frjDBhtpS3oZRe62GrxoXMjDq2zVsznMmaeDrXMMqzuid9R4TxTAFNQ?= =?us-ascii?Q?BerKlIeJGemSthUa6W2zhMfKgmqnzH8I4BMJk4I1XytD9VYjPBoAlnncaQh5?= =?us-ascii?Q?6j1fWXTbjN98txye7AMY48GW1KOA5OgFCyRqJYiqZlZMo7hvZPdNeJ3Wcu25?= =?us-ascii?Q?NK3lvM68fti+0SfZxdToCmA5IDyIihuPzodd+xDIFOjVHB/nJnq89ukLSUl8?= =?us-ascii?Q?525FyT3CqoO2gtXXT34lV1M+Hog7C/Zr8Vjk8x0YUSCNi5TcMqZZ16sMr2Cd?= =?us-ascii?Q?X6c73EmjhLq6zauqUypfs2ErdPyt0KWE8hCzQGWgmwPp9AuY64v/gXFK7UW1?= =?us-ascii?Q?TQdVyKJuJwqdWomloLIKOAhsuK7rG75/PT5Vwla535+Xxmu1Jz0rtnieeZEr?= =?us-ascii?Q?C1M6zHcQXDyD4sOgnjnhPV5FmK9dwQGgLDizIdYbQi06kCcoC9vCMweSDbw2?= =?us-ascii?Q?FawHSacX1Gx/faojdqYEeNPi8q41G9CdvTB5j4vW4Tm95ZoJJGqSbgngGOBD?= =?us-ascii?Q?Mwx1fQwCpoEp7Je3aeLeus/zuIf0vQfBGUunQEu1MXxsWuCduDFPW03JrBOr?= =?us-ascii?Q?W78mP4T7T5E4CSxEIlNHItMNsU4lQm1PwYGA34qu6fyU1VDtBi3UzYwC8Iz9?= =?us-ascii?Q?NdWCi64U2rlOec05dJ10HWoXXvkKWilfb0Xw6Ank7EeBQp9ugQEuzXC+U7OS?= =?us-ascii?Q?3PSk2QrZE0cR9ocswh1QAIXG73J79dgecizGgYDTQ66FW8oaPPXIClA5b7cU?= =?us-ascii?Q?wQIhg8p4wmqMqyhf6jSd1gc=3D?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a254c922-3192-4b8f-5fc9-08d9ecdf2b54 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB4679.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Feb 2022 21:49:10.0635 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: UT5Bcq4n7STvj+GFlYo/PL4z2TY0fILvFTrgd7BSQzgioliMmE+xC4vQX/ZrLJLaIPompZPSA7MU7mVwQeWCzg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB7PR04MB4172 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 22-01-26 20:27:49, Shawn Guo wrote: > On Thu, Dec 16, 2021 at 08:48:06PM +0200, Abel Vesa wrote: > > From: Jacky Bai > > > > The i.MX8DXL is a device targeting the automotive and industrial > > market segments. The flexibility of the architecture allows for > > use in a wide variety of general embedded applications. The chip > > is designed to achieve both high performance and low power consumption. > > The chip relies on the power efficient dual (2x) Cortex-A35 cluster. > > > > Add the reserved memory node property for dsp reserved memory, > > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the > > Not sure what "ion" is. > Nevermind, the commit message was not updated after the imx ion was dropped from NXP's internal tree. I'll update the commit message in the next version. > > cm4 rproc support. > > > > Signed-off-by: Jacky Bai > > Signed-off-by: Abel Vesa > > --- > > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ > > 1 file changed, 245 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > new file mode 100644 > > index 000000000000..f16f88882c39 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > @@ -0,0 +1,245 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019-2021 NXP > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/ { > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + ethernet0 = &fec1; > > + ethernet1 = &eqos; > > + gpio0 = &lsio_gpio0; > > + gpio1 = &lsio_gpio1; > > + gpio2 = &lsio_gpio2; > > + gpio3 = &lsio_gpio3; > > + gpio4 = &lsio_gpio4; > > + gpio5 = &lsio_gpio5; > > + gpio6 = &lsio_gpio6; > > + gpio7 = &lsio_gpio7; > > + i2c2 = &i2c2; > > + i2c3 = &i2c3; > > + mmc0 = &usdhc1; > > + mmc1 = &usdhc2; > > + mu1 = &lsio_mu1; > > + serial0 = &lpuart0; > > + serial1 = &lpuart1; > > + serial2 = &lpuart2; > > + serial3 = &lpuart3; > > + }; > > + > > + cpus: cpus { > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + /* We have 1 clusters with 2 Cortex-A35 cores */ > > s/clusters/cluster > Fixed in the next version. > > + A35_0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x0>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > > + #cooling-cells = <2>; > > + operating-points-v2 = <&a35_opp_table>; > > + }; > > + > > + A35_1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x1>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > > + #cooling-cells = <2>; > > + operating-points-v2 = <&a35_opp_table>; > > + }; > > + > > + A35_L2: l2-cache0 { > > + compatible = "cache"; > > + }; > > + }; > > + > > + a35_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-900000000 { > > + opp-hz = /bits/ 64 <900000000>; > > + opp-microvolt = <1000000>; > > + clock-latency-ns = <150000>; > > + }; > > + > > + opp-1200000000 { > > + opp-hz = /bits/ 64 <1200000000>; > > + opp-microvolt = <1100000>; > > + clock-latency-ns = <150000>; > > + opp-suspend; > > + }; > > + }; > > + > > + reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + dsp_reserved: dsp@92400000 { > > + reg = <0 0x92400000 0 0x2000000>; > > + no-map; > > + }; > > + }; > > + > > + gic: interrupt-controller@51a00000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupts = ; > > + }; > > + > > + pmu { > > + compatible = "arm,armv8-pmuv3"; > > + interrupts = ; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + scu { > > + compatible = "fsl,imx-scu"; > > + mbox-names = "tx0", > > + "rx0", > > + "gip3"; > > + mboxes = <&lsio_mu1 0 0 > > + &lsio_mu1 1 0 > > + &lsio_mu1 3 3>; > > + > > + pd: imx8dxl-pd { > > + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; > > + #power-domain-cells = <1>; > > + }; > > + > > + clk: clock-controller { > > + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; > > + #clock-cells = <2>; > > + clocks = <&xtal32k &xtal24m>; > > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > > + }; > > + > > + iomuxc: pinctrl { > > + compatible = "fsl,imx8dxl-iomuxc"; > > + }; > > + > > + ocotp: imx8qx-ocotp { > > + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + fec_mac0: mac@2c4 { > > + reg = <0x2c4 6>; > > + }; > > + > > + fec_mac1: mac@2c6 { > > + reg = <0x2c6 6>; > > + }; > > + }; > > + > > + watchdog { > > + compatible = "fsl,imx-sc-wdt"; > > + timeout-sec = <60>; > > + }; > > + > > + tsens: thermal-sensor { > > + compatible = "fsl,imx-sc-thermal"; > > + #thermal-sensor-cells = <1>; > > + }; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = , /* Physical Secure */ > > + , /* Physical Non-Secure */ > > + , /* Virtual */ > > + ; /* Hypervisor */ > > + }; > > + > > + thermal_zones: thermal-zones { > > + cpu-thermal0 { > > + polling-delay-passive = <250>; > > + polling-delay = <2000>; > > + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; > > + > > + trips { > > + cpu_alert0: trip0 { > > + temperature = <107000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > Have a newline between nodes. > Fixed in the next version. > > + cpu_crit0: trip1 { > > + temperature = <127000>; > > + hysteresis = <2000>; > > + type = "critical"; > > + }; > > + }; > > + cooling-maps { > > + map0 { > > + trip = <&cpu_alert0>; > > + cooling-device = > > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > + }; > > + }; > > + }; > > + }; > > + > > + clk_dummy: clock-dummy { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <0>; > > + clock-output-names = "clk_dummy"; > > + }; > > Why do we need this? > The following comment is found in imx8dxl-ss-conn.dtsi: /* * usbotg1 and usbotg2 share one clcok * scfw disable clock access and keep it always on * in case other core (M4) use one of these. */ So I guess it is basically a hack to allow both usbotg instances to have a shared clock, while the clock is handled by the SCU. Also, the venndor tree seems to be making use of this dummy clock in a lot of dts nodes. Even on QXP and QM. > Shawn > > > + > > + xtal32k: clock-xtal32k { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <32768>; > > + clock-output-names = "xtal_32KHz"; > > + }; > > + > > + xtal24m: clock-xtal24m { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + clock-output-names = "xtal_24MHz"; > > + }; > > + > > + sc_pwrkey: sc-powerkey { > > + compatible = "fsl,imx8-pwrkey"; > > + linux,keycode = ; > > + wakeup-source; > > + }; > > + > > + /* sorted in register address */ > > + #include "imx8-ss-adma.dtsi" > > + #include "imx8-ss-conn.dtsi" > > + #include "imx8-ss-ddr.dtsi" > > + #include "imx8-ss-lsio.dtsi" > > +}; > > + > > +#include "imx8dxl-ss-adma.dtsi" > > +#include "imx8dxl-ss-conn.dtsi" > > +#include "imx8dxl-ss-lsio.dtsi" > > +#include "imx8dxl-ss-ddr.dtsi" > > -- > > 2.31.1 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CFAB1C433F5 for ; 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Thu, 10 Feb 2022 21:49:10 +0000 Received: from AM6PR04MB4679.eurprd04.prod.outlook.com ([fe80::28f3:36a7:fc3c:b9aa]) by AM6PR04MB4679.eurprd04.prod.outlook.com ([fe80::28f3:36a7:fc3c:b9aa%5]) with mapi id 15.20.4975.011; Thu, 10 Feb 2022 21:49:10 +0000 Date: Thu, 10 Feb 2022 23:49:07 +0200 From: Abel Vesa To: Shawn Guo Cc: Rob Herring , Dong Aisheng , Sascha Hauer , Greg Kroah-Hartman , Fabio Estevam , Pengutronix Kernel Team , linux-i2c@vger.kernel.org, linux-serial@vger.kernel.org, NXP Linux Team , Linux Kernel Mailing List , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, Jacky Bai Subject: Re: [RESEND v4 02/10] arm64: dts: freescale: Add the top level dtsi support for imx8dxl Message-ID: References: <1639680494-23183-1-git-send-email-abel.vesa@nxp.com> <1639680494-23183-3-git-send-email-abel.vesa@nxp.com> <20220126122748.GP4686@dragon> Content-Disposition: inline In-Reply-To: <20220126122748.GP4686@dragon> X-ClientProxiedBy: VI1PR02CA0055.eurprd02.prod.outlook.com (2603:10a6:802:14::26) To AM6PR04MB4679.eurprd04.prod.outlook.com (2603:10a6:20b:15::32) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: a254c922-3192-4b8f-5fc9-08d9ecdf2b54 X-MS-TrafficTypeDiagnostic: DB7PR04MB4172:EE_ X-Microsoft-Antispam-PRVS: X-MS-Oob-TLC-OOBClassifiers: OLM:2150; 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charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 22-01-26 20:27:49, Shawn Guo wrote: > On Thu, Dec 16, 2021 at 08:48:06PM +0200, Abel Vesa wrote: > > From: Jacky Bai > > > > The i.MX8DXL is a device targeting the automotive and industrial > > market segments. The flexibility of the architecture allows for > > use in a wide variety of general embedded applications. The chip > > is designed to achieve both high performance and low power consumption. > > The chip relies on the power efficient dual (2x) Cortex-A35 cluster. > > > > Add the reserved memory node property for dsp reserved memory, > > the wakeup-irq property for SCU node, the imx ion, the rpmsg and the > > Not sure what "ion" is. > Nevermind, the commit message was not updated after the imx ion was dropped from NXP's internal tree. I'll update the commit message in the next version. > > cm4 rproc support. > > > > Signed-off-by: Jacky Bai > > Signed-off-by: Abel Vesa > > --- > > arch/arm64/boot/dts/freescale/imx8dxl.dtsi | 245 +++++++++++++++++++++ > > 1 file changed, 245 insertions(+) > > create mode 100644 arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > new file mode 100644 > > index 000000000000..f16f88882c39 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi > > @@ -0,0 +1,245 @@ > > +// SPDX-License-Identifier: GPL-2.0+ > > +/* > > + * Copyright 2019-2021 NXP > > + */ > > + > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > +#include > > + > > +/ { > > + interrupt-parent = <&gic>; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + > > + aliases { > > + ethernet0 = &fec1; > > + ethernet1 = &eqos; > > + gpio0 = &lsio_gpio0; > > + gpio1 = &lsio_gpio1; > > + gpio2 = &lsio_gpio2; > > + gpio3 = &lsio_gpio3; > > + gpio4 = &lsio_gpio4; > > + gpio5 = &lsio_gpio5; > > + gpio6 = &lsio_gpio6; > > + gpio7 = &lsio_gpio7; > > + i2c2 = &i2c2; > > + i2c3 = &i2c3; > > + mmc0 = &usdhc1; > > + mmc1 = &usdhc2; > > + mu1 = &lsio_mu1; > > + serial0 = &lpuart0; > > + serial1 = &lpuart1; > > + serial2 = &lpuart2; > > + serial3 = &lpuart3; > > + }; > > + > > + cpus: cpus { > > + #address-cells = <2>; > > + #size-cells = <0>; > > + > > + /* We have 1 clusters with 2 Cortex-A35 cores */ > > s/clusters/cluster > Fixed in the next version. > > + A35_0: cpu@0 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x0>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > > + #cooling-cells = <2>; > > + operating-points-v2 = <&a35_opp_table>; > > + }; > > + > > + A35_1: cpu@1 { > > + device_type = "cpu"; > > + compatible = "arm,cortex-a35"; > > + reg = <0x0 0x1>; > > + enable-method = "psci"; > > + next-level-cache = <&A35_L2>; > > + clocks = <&clk IMX_SC_R_A35 IMX_SC_PM_CLK_CPU>; > > + #cooling-cells = <2>; > > + operating-points-v2 = <&a35_opp_table>; > > + }; > > + > > + A35_L2: l2-cache0 { > > + compatible = "cache"; > > + }; > > + }; > > + > > + a35_opp_table: opp-table { > > + compatible = "operating-points-v2"; > > + opp-shared; > > + > > + opp-900000000 { > > + opp-hz = /bits/ 64 <900000000>; > > + opp-microvolt = <1000000>; > > + clock-latency-ns = <150000>; > > + }; > > + > > + opp-1200000000 { > > + opp-hz = /bits/ 64 <1200000000>; > > + opp-microvolt = <1100000>; > > + clock-latency-ns = <150000>; > > + opp-suspend; > > + }; > > + }; > > + > > + reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + dsp_reserved: dsp@92400000 { > > + reg = <0 0x92400000 0 0x2000000>; > > + no-map; > > + }; > > + }; > > + > > + gic: interrupt-controller@51a00000 { > > + compatible = "arm,gic-v3"; > > + reg = <0x0 0x51a00000 0 0x10000>, /* GIC Dist */ > > + <0x0 0x51b00000 0 0xc0000>; /* GICR (RD_base + SGI_base) */ > > + #interrupt-cells = <3>; > > + interrupt-controller; > > + interrupts = ; > > + }; > > + > > + pmu { > > + compatible = "arm,armv8-pmuv3"; > > + interrupts = ; > > + }; > > + > > + psci { > > + compatible = "arm,psci-1.0"; > > + method = "smc"; > > + }; > > + > > + scu { > > + compatible = "fsl,imx-scu"; > > + mbox-names = "tx0", > > + "rx0", > > + "gip3"; > > + mboxes = <&lsio_mu1 0 0 > > + &lsio_mu1 1 0 > > + &lsio_mu1 3 3>; > > + > > + pd: imx8dxl-pd { > > + compatible = "fsl,imx8dxl-scu-pd", "fsl,scu-pd"; > > + #power-domain-cells = <1>; > > + }; > > + > > + clk: clock-controller { > > + compatible = "fsl,imx8dxl-clk", "fsl,scu-clk"; > > + #clock-cells = <2>; > > + clocks = <&xtal32k &xtal24m>; > > + clock-names = "xtal_32KHz", "xtal_24Mhz"; > > + }; > > + > > + iomuxc: pinctrl { > > + compatible = "fsl,imx8dxl-iomuxc"; > > + }; > > + > > + ocotp: imx8qx-ocotp { > > + compatible = "fsl,imx8dxl-scu-ocotp", "fsl,imx8qxp-scu-ocotp"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + > > + fec_mac0: mac@2c4 { > > + reg = <0x2c4 6>; > > + }; > > + > > + fec_mac1: mac@2c6 { > > + reg = <0x2c6 6>; > > + }; > > + }; > > + > > + watchdog { > > + compatible = "fsl,imx-sc-wdt"; > > + timeout-sec = <60>; > > + }; > > + > > + tsens: thermal-sensor { > > + compatible = "fsl,imx-sc-thermal"; > > + #thermal-sensor-cells = <1>; > > + }; > > + }; > > + > > + timer { > > + compatible = "arm,armv8-timer"; > > + interrupts = , /* Physical Secure */ > > + , /* Physical Non-Secure */ > > + , /* Virtual */ > > + ; /* Hypervisor */ > > + }; > > + > > + thermal_zones: thermal-zones { > > + cpu-thermal0 { > > + polling-delay-passive = <250>; > > + polling-delay = <2000>; > > + thermal-sensors = <&tsens IMX_SC_R_SYSTEM>; > > + > > + trips { > > + cpu_alert0: trip0 { > > + temperature = <107000>; > > + hysteresis = <2000>; > > + type = "passive"; > > + }; > > Have a newline between nodes. > Fixed in the next version. > > + cpu_crit0: trip1 { > > + temperature = <127000>; > > + hysteresis = <2000>; > > + type = "critical"; > > + }; > > + }; > > + cooling-maps { > > + map0 { > > + trip = <&cpu_alert0>; > > + cooling-device = > > + <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, > > + <&A35_1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; > > + }; > > + }; > > + }; > > + }; > > + > > + clk_dummy: clock-dummy { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <0>; > > + clock-output-names = "clk_dummy"; > > + }; > > Why do we need this? > The following comment is found in imx8dxl-ss-conn.dtsi: /* * usbotg1 and usbotg2 share one clcok * scfw disable clock access and keep it always on * in case other core (M4) use one of these. */ So I guess it is basically a hack to allow both usbotg instances to have a shared clock, while the clock is handled by the SCU. Also, the venndor tree seems to be making use of this dummy clock in a lot of dts nodes. Even on QXP and QM. > Shawn > > > + > > + xtal32k: clock-xtal32k { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <32768>; > > + clock-output-names = "xtal_32KHz"; > > + }; > > + > > + xtal24m: clock-xtal24m { > > + compatible = "fixed-clock"; > > + #clock-cells = <0>; > > + clock-frequency = <24000000>; > > + clock-output-names = "xtal_24MHz"; > > + }; > > + > > + sc_pwrkey: sc-powerkey { > > + compatible = "fsl,imx8-pwrkey"; > > + linux,keycode = ; > > + wakeup-source; > > + }; > > + > > + /* sorted in register address */ > > + #include "imx8-ss-adma.dtsi" > > + #include "imx8-ss-conn.dtsi" > > + #include "imx8-ss-ddr.dtsi" > > + #include "imx8-ss-lsio.dtsi" > > +}; > > + > > +#include "imx8dxl-ss-adma.dtsi" > > +#include "imx8dxl-ss-conn.dtsi" > > +#include "imx8dxl-ss-lsio.dtsi" > > +#include "imx8dxl-ss-ddr.dtsi" > > -- > > 2.31.1 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel