From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 079BFC433FE for ; Fri, 11 Feb 2022 16:14:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1350814AbiBKQOT (ORCPT ); Fri, 11 Feb 2022 11:14:19 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:43494 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1350602AbiBKQOQ (ORCPT ); Fri, 11 Feb 2022 11:14:16 -0500 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9DF2D4F; Fri, 11 Feb 2022 08:14:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644596055; x=1676132055; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=2sObmrIIJ6u7JgxEqMuhXgNJQeFbV1/jHHnxLE325BM=; b=Ho2Z1vLaSXw9C3ZYUNKHXqJ949xAeGMTE5ncjC6IO5sRzALyGeeNaGBa 9M8FL6SQmLdhRgLXrg8LSrWh7jlrcbMMBlpppKiSmEBQmI8eIBvDTL4PG jkrGDS35uv1yF8Me5sfSd9GTC/MvJQwD5I0QFH6WgqcDFrSxpYFhHBSLU hpNXwzhWn5Ylim4qjpNHfCMkRl4HRlu0W40f48seWA40EkZPmrv85ttKR 7+NsFcznypY5cG2plQar28tFA5zytFpsSIrWYqzG/9jxtwRsrdp1PEG/W 71crS0SqP11Jedr3xCbjyYR1/r6ZZv/PgJoHZ7m984VBWAJTOeybg+axd w==; X-IronPort-AV: E=McAfee;i="6200,9189,10254"; a="230400142" X-IronPort-AV: E=Sophos;i="5.88,361,1635231600"; d="scan'208";a="230400142" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2022 08:14:15 -0800 X-IronPort-AV: E=Sophos;i="5.88,361,1635231600"; d="scan'208";a="483479902" Received: from smile.fi.intel.com ([10.237.72.61]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 11 Feb 2022 08:14:10 -0800 Received: from andy by smile.fi.intel.com with local (Exim 4.95) (envelope-from ) id 1nIYXo-003V6e-FM; Fri, 11 Feb 2022 18:13:12 +0200 Date: Fri, 11 Feb 2022 18:13:12 +0200 From: Andy Shevchenko To: Javier Martinez Canillas Cc: linux-kernel@vger.kernel.org, Daniel Vetter , linux-fbdev@vger.kernel.org, Sam Ravnborg , Maxime Ripard , dri-devel@lists.freedesktop.org, Noralf =?iso-8859-1?Q?Tr=F8nnes?= , Geert Uytterhoeven , Thomas Zimmermann , Daniel Vetter , David Airlie , Lee Jones , Maarten Lankhorst , Maxime Ripard , Thierry Reding , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , linux-pwm@vger.kernel.org Subject: Re: [PATCH v5 3/6] drm: Add driver for Solomon SSD130x OLED displays Message-ID: References: <20220211143358.3112958-1-javierm@redhat.com> <20220211143358.3112958-4-javierm@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220211143358.3112958-4-javierm@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, Feb 11, 2022 at 03:33:55PM +0100, Javier Martinez Canillas wrote: > This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon > OLED display controllers. > > It's only the core part of the driver and a bus specific driver is needed > for each transport interface supported by the display controllers. ... > +#define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0) > +#define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val)) > +#define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4) > +#define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val)) > +#define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0) > +#define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val)) > +#define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4) > +#define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val)) > +#define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4) BIT(4) > +#define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (!val)) > +#define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5) BIT(5) > +#define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val)) I would put GENMASK() directly into FIELD(), but it's up to you (and I haven't checked the use of *_MASK anyway). ... > +static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count) > +{ > + int ret; > + > + ret = regmap_bulk_write(ssd130x->regmap, SSD130X_DATA, values, count); > + if (ret) > + return ret; > + > + return 0; return regmap_bulk_write(...); > +} ... > +/* > + * Helper to write command (SSD130X_COMMAND). The fist variadic argument > + * is the command to write and the following are the command options. > + * > + * Note that the ssd130x protocol requires each command and option to be > + * written as a SSD130X_COMMAND device register value. That is why a call > + * to regmap_write(..., SSD130X_COMMAND, ...) is done for each argument. > + */ Thanks! > +static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count, > + /* u8 cmd, u8 option, ... */...) > +{ > + va_list ap; > + u8 value; > + int ret; > + > + va_start(ap, count); > + > + do { > + value = va_arg(ap, int); > + ret = regmap_write(ssd130x->regmap, SSD130X_COMMAND, (u8)value); Wondering if you really need this casting. value is u8 by definition. > + if (ret) > + goto out_end; > + } while (--count); > + > +out_end: > + va_end(ap); > + > + return ret; > +} ... > + ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver, > + struct ssd130x_device, drm); > + if (IS_ERR(ssd130x)) { > + dev_err_probe(dev, PTR_ERR(ssd130x), > + "Failed to allocate DRM device\n"); > + return ssd130x; This... > + } ... > + bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x, > + &ssd130xfb_bl_ops, NULL); > + if (IS_ERR(bl)) > + return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl), > + "Unable to register backlight device\n")); Can be consistent with this then. -- With Best Regards, Andy Shevchenko From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CF896C433F5 for ; Fri, 11 Feb 2022 16:14:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 05A5510EAA2; Fri, 11 Feb 2022 16:14:17 +0000 (UTC) Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4BF6110E361 for ; Fri, 11 Feb 2022 16:14:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1644596055; x=1676132055; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; 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Fri, 11 Feb 2022 18:13:12 +0200 Date: Fri, 11 Feb 2022 18:13:12 +0200 From: Andy Shevchenko To: Javier Martinez Canillas Subject: Re: [PATCH v5 3/6] drm: Add driver for Solomon SSD130x OLED displays Message-ID: References: <20220211143358.3112958-1-javierm@redhat.com> <20220211143358.3112958-4-javierm@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220211143358.3112958-4-javierm@redhat.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-pwm@vger.kernel.org, linux-fbdev@vger.kernel.org, David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Noralf =?iso-8859-1?Q?Tr=F8nnes?= , Geert Uytterhoeven , Maxime Ripard , Thomas Zimmermann , Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Thierry Reding , Lee Jones , Sam Ravnborg Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Feb 11, 2022 at 03:33:55PM +0100, Javier Martinez Canillas wrote: > This adds a DRM driver for SSD1305, SSD1306, SSD1307 and SSD1309 Solomon > OLED display controllers. > > It's only the core part of the driver and a bus specific driver is needed > for each transport interface supported by the display controllers. ... > +#define SSD130X_SET_CLOCK_DIV_MASK GENMASK(3, 0) > +#define SSD130X_SET_CLOCK_DIV_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_DIV_MASK, (val)) > +#define SSD130X_SET_CLOCK_FREQ_MASK GENMASK(7, 4) > +#define SSD130X_SET_CLOCK_FREQ_SET(val) FIELD_PREP(SSD130X_SET_CLOCK_FREQ_MASK, (val)) > +#define SSD130X_SET_PRECHARGE_PERIOD1_MASK GENMASK(3, 0) > +#define SSD130X_SET_PRECHARGE_PERIOD1_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD1_MASK, (val)) > +#define SSD130X_SET_PRECHARGE_PERIOD2_MASK GENMASK(7, 4) > +#define SSD130X_SET_PRECHARGE_PERIOD2_SET(val) FIELD_PREP(SSD130X_SET_PRECHARGE_PERIOD2_MASK, (val)) > +#define SSD130X_SET_COM_PINS_CONFIG1_MASK GENMASK(4, 4) BIT(4) > +#define SSD130X_SET_COM_PINS_CONFIG1_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG1_MASK, (!val)) > +#define SSD130X_SET_COM_PINS_CONFIG2_MASK GENMASK(5, 5) BIT(5) > +#define SSD130X_SET_COM_PINS_CONFIG2_SET(val) FIELD_PREP(SSD130X_SET_COM_PINS_CONFIG2_MASK, (val)) I would put GENMASK() directly into FIELD(), but it's up to you (and I haven't checked the use of *_MASK anyway). ... > +static int ssd130x_write_data(struct ssd130x_device *ssd130x, u8 *values, int count) > +{ > + int ret; > + > + ret = regmap_bulk_write(ssd130x->regmap, SSD130X_DATA, values, count); > + if (ret) > + return ret; > + > + return 0; return regmap_bulk_write(...); > +} ... > +/* > + * Helper to write command (SSD130X_COMMAND). The fist variadic argument > + * is the command to write and the following are the command options. > + * > + * Note that the ssd130x protocol requires each command and option to be > + * written as a SSD130X_COMMAND device register value. That is why a call > + * to regmap_write(..., SSD130X_COMMAND, ...) is done for each argument. > + */ Thanks! > +static int ssd130x_write_cmd(struct ssd130x_device *ssd130x, int count, > + /* u8 cmd, u8 option, ... */...) > +{ > + va_list ap; > + u8 value; > + int ret; > + > + va_start(ap, count); > + > + do { > + value = va_arg(ap, int); > + ret = regmap_write(ssd130x->regmap, SSD130X_COMMAND, (u8)value); Wondering if you really need this casting. value is u8 by definition. > + if (ret) > + goto out_end; > + } while (--count); > + > +out_end: > + va_end(ap); > + > + return ret; > +} ... > + ssd130x = devm_drm_dev_alloc(dev, &ssd130x_drm_driver, > + struct ssd130x_device, drm); > + if (IS_ERR(ssd130x)) { > + dev_err_probe(dev, PTR_ERR(ssd130x), > + "Failed to allocate DRM device\n"); > + return ssd130x; This... > + } ... > + bl = devm_backlight_device_register(dev, dev_name(dev), dev, ssd130x, > + &ssd130xfb_bl_ops, NULL); > + if (IS_ERR(bl)) > + return ERR_PTR(dev_err_probe(dev, PTR_ERR(bl), > + "Unable to register backlight device\n")); Can be consistent with this then. -- With Best Regards, Andy Shevchenko