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[86.27.177.88]) by smtp.gmail.com with ESMTPSA id 7sm15721841wrb.43.2022.02.15.08.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 08:54:02 -0800 (PST) Date: Tue, 15 Feb 2022 16:54:00 +0000 From: Lee Jones To: Andy Shevchenko Cc: Wolfram Sang , Jean Delvare , Heiner Kallweit , Hans de Goede , Linus Walleij , Tan Jui Nee , Kate Hsuan , Jonathan Yong , linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org, linux-i2c@vger.kernel.org, linux-gpio@vger.kernel.org, platform-driver-x86@vger.kernel.org, Borislav Petkov , Mauro Carvalho Chehab , Tony Luck , James Morse , Robert Richter , Jean Delvare , Peter Tyser , Mika Westerberg , Andy Shevchenko , Mark Gross , Henning Schild Subject: Re: [PATCH v4 5/8] mfd: lpc_ich: Add support for pinctrl in non-ACPI system Message-ID: References: <20220131151346.45792-1-andriy.shevchenko@linux.intel.com> <20220131151346.45792-6-andriy.shevchenko@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20220131151346.45792-6-andriy.shevchenko@linux.intel.com> Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org On Mon, 31 Jan 2022, Andy Shevchenko wrote: > From: Tan Jui Nee > > Add support for non-ACPI systems, such as system that uses > Advanced Boot Loader (ABL) whereby a platform device has to be created > in order to bind with pin control and GPIO. > > At the moment, Intel Apollo Lake In-Vehicle Infotainment (IVI) system > requires a driver to hide and unhide P2SB to lookup P2SB BAR and pass > the PCI BAR address to GPIO. > > Signed-off-by: Tan Jui Nee > Co-developed-by: Andy Shevchenko > Signed-off-by: Andy Shevchenko > Acked-by: Hans de Goede > Acked-by: Linus Walleij > --- > drivers/mfd/lpc_ich.c | 101 +++++++++++++++++++++++++++++++++++++++++- > 1 file changed, 100 insertions(+), 1 deletion(-) > > diff --git a/drivers/mfd/lpc_ich.c b/drivers/mfd/lpc_ich.c > index 95dca5434917..e1bca5325ce7 100644 > --- a/drivers/mfd/lpc_ich.c > +++ b/drivers/mfd/lpc_ich.c > @@ -8,7 +8,8 @@ > * Configuration Registers. > * > * This driver is derived from lpc_sch. > - > + * > + * Copyright (c) 2017, 2021-2022 Intel Corporation > * Copyright (c) 2011 Extreme Engineering Solution, Inc. > * Author: Aaron Sierra > * > @@ -42,6 +43,7 @@ > #include > #include > #include > +#include > #include > #include > #include > @@ -140,6 +142,70 @@ static struct mfd_cell lpc_ich_gpio_cell = { > .ignore_resource_conflicts = true, > }; > > +#define APL_GPIO_NORTH 0 > +#define APL_GPIO_NORTHWEST 1 > +#define APL_GPIO_WEST 2 > +#define APL_GPIO_SOUTHWEST 3 > +#define APL_GPIO_NR_DEVICES 4 > + > +/* Offset data for Apollo Lake GPIO controllers */ > +#define APL_GPIO_NORTH_OFFSET 0xc50000 > +#define APL_GPIO_NORTHWEST_OFFSET 0xc40000 > +#define APL_GPIO_WEST_OFFSET 0xc70000 > +#define APL_GPIO_SOUTHWEST_OFFSET 0xc00000 > + > +#define APL_GPIO_IRQ 14 > + > +static struct resource apl_gpio_resources[APL_GPIO_NR_DEVICES][2] = { > + [APL_GPIO_NORTH] = { > + DEFINE_RES_MEM(APL_GPIO_NORTH_OFFSET, 0x1000), Are these 0x1000's being over-written in lpc_ich_init_pinctrl()? If so, why pre-initialise? > + DEFINE_RES_IRQ(APL_GPIO_IRQ), > + }, > + [APL_GPIO_NORTHWEST] = { > + DEFINE_RES_MEM(APL_GPIO_NORTHWEST_OFFSET, 0x1000), > + DEFINE_RES_IRQ(APL_GPIO_IRQ), > + }, > + [APL_GPIO_WEST] = { > + DEFINE_RES_MEM(APL_GPIO_WEST_OFFSET, 0x1000), > + DEFINE_RES_IRQ(APL_GPIO_IRQ), > + }, > + [APL_GPIO_SOUTHWEST] = { > + DEFINE_RES_MEM(APL_GPIO_SOUTHWEST_OFFSET, 0x1000), > + DEFINE_RES_IRQ(APL_GPIO_IRQ), > + }, > +}; > + > +/* The order must be in sync with apl_pinctrl_soc_data */ Why does the order matter if you've pre-enumerated them all? > +static const struct mfd_cell apl_gpio_devices[APL_GPIO_NR_DEVICES] = { > + [APL_GPIO_NORTH] = { > + .name = "apollolake-pinctrl", > + .id = APL_GPIO_NORTH, > + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTH]), > + .resources = apl_gpio_resources[APL_GPIO_NORTH], > + .ignore_resource_conflicts = true, > + }, > + [APL_GPIO_NORTHWEST] = { > + .name = "apollolake-pinctrl", > + .id = APL_GPIO_NORTHWEST, > + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_NORTHWEST]), > + .resources = apl_gpio_resources[APL_GPIO_NORTHWEST], > + .ignore_resource_conflicts = true, > + }, > + [APL_GPIO_WEST] = { > + .name = "apollolake-pinctrl", > + .id = APL_GPIO_WEST, > + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_WEST]), > + .resources = apl_gpio_resources[APL_GPIO_WEST], > + .ignore_resource_conflicts = true, > + }, > + [APL_GPIO_SOUTHWEST] = { > + .name = "apollolake-pinctrl", > + .id = APL_GPIO_SOUTHWEST, > + .num_resources = ARRAY_SIZE(apl_gpio_resources[APL_GPIO_SOUTHWEST]), > + .resources = apl_gpio_resources[APL_GPIO_SOUTHWEST], > + .ignore_resource_conflicts = true, > + }, > +}; > > static struct mfd_cell lpc_ich_spi_cell = { > .name = "intel-spi", > @@ -1083,6 +1149,33 @@ static int lpc_ich_init_wdt(struct pci_dev *dev) > return ret; > } > > +static int lpc_ich_init_pinctrl(struct pci_dev *dev) > +{ > + struct resource base; > + unsigned int i; > + int ret; > + > + /* Check, if GPIO has been exported as an ACPI device */ > + if (acpi_dev_present("INT3452", NULL, -1)) > + return -EEXIST; > + > + ret = p2sb_bar(dev->bus, 0, &base); > + if (ret) > + return ret; > + > + for (i = 0; i < ARRAY_SIZE(apl_gpio_devices); i++) { > + struct resource *mem = &apl_gpio_resources[i][0]; > + > + /* Fill MEM resource */ > + mem->start += base.start; > + mem->end += base.start; > + mem->flags = base.flags; > + } > + > + return mfd_add_devices(&dev->dev, 0, apl_gpio_devices, > + ARRAY_SIZE(apl_gpio_devices), NULL, 0, NULL); > +} > + > static void lpc_ich_test_spi_write(struct pci_dev *dev, unsigned int devfn, > struct intel_spi_boardinfo *info) > { > @@ -1199,6 +1292,12 @@ static int lpc_ich_probe(struct pci_dev *dev, > cell_added = true; > } > > + if (priv->chipset == LPC_APL) { > + ret = lpc_ich_init_pinctrl(dev); > + if (!ret) > + cell_added = true; > + } > + > if (lpc_chipset_info[priv->chipset].spi_type) { > ret = lpc_ich_init_spi(dev); > if (!ret) -- Lee Jones [李琼斯] Principal Technical Lead - Developer Services Linaro.org │ Open source software for Arm SoCs Follow Linaro: Facebook | Twitter | Blog