* [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Hi all,
third and hopefully last revision of this patchset. The dt-binding
patches are dropped, as Shawn already picked them up. I fixed up all
the review comments received by Laurent and Marek.
Regards,
Lucas
Lucas Stach (7):
soc: imx: gpcv2: add PGC control register indirection
soc: imx: gpcv2: add support for i.MX8MP power domains
soc: imx: add i.MX8MP HSIO blk-ctrl
dt-bindings: usb: dwc3-imx8mp: add power domain property
arm64: dts: imx8mp: add HSIO power-domains
arm64: dts: imx8mp: add GPU power domains
arm64: dts: imx8mp: add GPU nodes
.../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
5 files changed, 994 insertions(+), 18 deletions(-)
create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
2.30.2
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Hi all,
third and hopefully last revision of this patchset. The dt-binding
patches are dropped, as Shawn already picked them up. I fixed up all
the review comments received by Laurent and Marek.
Regards,
Lucas
Lucas Stach (7):
soc: imx: gpcv2: add PGC control register indirection
soc: imx: gpcv2: add support for i.MX8MP power domains
soc: imx: add i.MX8MP HSIO blk-ctrl
dt-bindings: usb: dwc3-imx8mp: add power domain property
arm64: dts: imx8mp: add HSIO power-domains
arm64: dts: imx8mp: add GPU power domains
arm64: dts: imx8mp: add GPU nodes
.../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
5 files changed, 994 insertions(+), 18 deletions(-)
create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH v3 1/7] soc: imx: gpcv2: add PGC control register indirection
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The PGC control registers in the shared (not per-PGC) region of the
GPC address space have different offsets on i.MX8MP to make space for
additional interrupt control registers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 3e59d479d001..01f46b078df3 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -184,9 +184,17 @@
#define GPC_PGC_CTRL_PCR BIT(0)
+struct imx_pgc_regs {
+ u16 map;
+ u16 pup;
+ u16 pdn;
+ u16 hsk;
+};
+
struct imx_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
+ const struct imx_pgc_regs *regs;
struct regulator *regulator;
struct reset_control *reset;
struct clk_bulk_data *clks;
@@ -210,6 +218,7 @@ struct imx_pgc_domain_data {
const struct imx_pgc_domain *domains;
size_t domains_num;
const struct regmap_access_table *reg_access_table;
+ const struct imx_pgc_regs *pgc_regs;
};
static inline struct imx_pgc_domain *
@@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
if (domain->bits.pxx) {
/* request the domain to power up */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ regmap_update_bits(domain->regmap, domain->regs->pup,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PUP_REQ, reg_val,
+ domain->regs->pup, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
/* request the ADB400 to power up */
if (domain->bits.hskreq) {
- regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ regmap_update_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq, domain->bits.hskreq);
/*
- * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
+ * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
* (reg_val & domain->bits.hskack), 0,
* USEC_PER_MSEC);
* Technically we need the commented code to wait handshake. But that needs
@@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
/* request the ADB400 to power down */
if (domain->bits.hskreq) {
- regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
+ regmap_clear_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq);
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
reg_val,
!(reg_val & domain->bits.hskack),
0, USEC_PER_MSEC);
@@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
}
/* request the domain to power down */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ regmap_update_bits(domain->regmap, domain->regs->pdn,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PDN_REQ, reg_val,
+ domain->regs->pdn, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = {
.n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
};
+static const struct imx_pgc_regs imx7_pgc_regs = {
+ .map = GPC_PGC_CPU_MAPPING,
+ .pup = GPC_PU_PGC_SW_PUP_REQ,
+ .pdn = GPC_PU_PGC_SW_PDN_REQ,
+ .hsk = GPC_PU_PWRHSK,
+};
+
static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
.domains = imx7_pgc_domains,
.domains_num = ARRAY_SIZE(imx7_pgc_domains),
.reg_access_table = &imx7_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8m_pgc_domains[] = {
@@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.domains = imx8m_pgc_domains,
.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
.reg_access_table = &imx8m_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
@@ -803,6 +821,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
.domains = imx8mm_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
.reg_access_table = &imx8mm_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
@@ -894,6 +913,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
.domains = imx8mn_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
.reg_access_table = &imx8mn_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static int imx_pgc_domain_probe(struct platform_device *pdev)
@@ -926,7 +946,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_runtime_enable(domain->dev);
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, domain->bits.map);
ret = pm_genpd_init(&domain->genpd, NULL, true);
@@ -952,7 +972,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
out_domain_unmap:
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@@ -967,7 +987,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@@ -1098,6 +1118,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
domain = pd_pdev->dev.platform_data;
domain->regmap = regmap;
+ domain->regs = domain_data->pgc_regs;
domain->genpd.power_on = imx_pgc_power_up;
domain->genpd.power_off = imx_pgc_power_down;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 1/7] soc: imx: gpcv2: add PGC control register indirection
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The PGC control registers in the shared (not per-PGC) region of the
GPC address space have different offsets on i.MX8MP to make space for
additional interrupt control registers.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++-----------
1 file changed, 32 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 3e59d479d001..01f46b078df3 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -184,9 +184,17 @@
#define GPC_PGC_CTRL_PCR BIT(0)
+struct imx_pgc_regs {
+ u16 map;
+ u16 pup;
+ u16 pdn;
+ u16 hsk;
+};
+
struct imx_pgc_domain {
struct generic_pm_domain genpd;
struct regmap *regmap;
+ const struct imx_pgc_regs *regs;
struct regulator *regulator;
struct reset_control *reset;
struct clk_bulk_data *clks;
@@ -210,6 +218,7 @@ struct imx_pgc_domain_data {
const struct imx_pgc_domain *domains;
size_t domains_num;
const struct regmap_access_table *reg_access_table;
+ const struct imx_pgc_regs *pgc_regs;
};
static inline struct imx_pgc_domain *
@@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
if (domain->bits.pxx) {
/* request the domain to power up */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
+ regmap_update_bits(domain->regmap, domain->regs->pup,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PUP_REQ, reg_val,
+ domain->regs->pup, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
/* request the ADB400 to power up */
if (domain->bits.hskreq) {
- regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
+ regmap_update_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq, domain->bits.hskreq);
/*
- * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
+ * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
* (reg_val & domain->bits.hskack), 0,
* USEC_PER_MSEC);
* Technically we need the commented code to wait handshake. But that needs
@@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
/* request the ADB400 to power down */
if (domain->bits.hskreq) {
- regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
+ regmap_clear_bits(domain->regmap, domain->regs->hsk,
domain->bits.hskreq);
- ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
+ ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
reg_val,
!(reg_val & domain->bits.hskack),
0, USEC_PER_MSEC);
@@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
}
/* request the domain to power down */
- regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
+ regmap_update_bits(domain->regmap, domain->regs->pdn,
domain->bits.pxx, domain->bits.pxx);
/*
* As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
* for PUP_REQ/PDN_REQ bit to be cleared
*/
ret = regmap_read_poll_timeout(domain->regmap,
- GPC_PU_PGC_SW_PDN_REQ, reg_val,
+ domain->regs->pdn, reg_val,
!(reg_val & domain->bits.pxx),
0, USEC_PER_MSEC);
if (ret) {
@@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = {
.n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
};
+static const struct imx_pgc_regs imx7_pgc_regs = {
+ .map = GPC_PGC_CPU_MAPPING,
+ .pup = GPC_PU_PGC_SW_PUP_REQ,
+ .pdn = GPC_PU_PGC_SW_PDN_REQ,
+ .hsk = GPC_PU_PWRHSK,
+};
+
static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
.domains = imx7_pgc_domains,
.domains_num = ARRAY_SIZE(imx7_pgc_domains),
.reg_access_table = &imx7_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8m_pgc_domains[] = {
@@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
.domains = imx8m_pgc_domains,
.domains_num = ARRAY_SIZE(imx8m_pgc_domains),
.reg_access_table = &imx8m_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
@@ -803,6 +821,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
.domains = imx8mm_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
.reg_access_table = &imx8mm_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
@@ -894,6 +913,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
.domains = imx8mn_pgc_domains,
.domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
.reg_access_table = &imx8mn_access_table,
+ .pgc_regs = &imx7_pgc_regs,
};
static int imx_pgc_domain_probe(struct platform_device *pdev)
@@ -926,7 +946,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_runtime_enable(domain->dev);
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, domain->bits.map);
ret = pm_genpd_init(&domain->genpd, NULL, true);
@@ -952,7 +972,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
out_domain_unmap:
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@@ -967,7 +987,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
pm_genpd_remove(&domain->genpd);
if (domain->bits.map)
- regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
+ regmap_update_bits(domain->regmap, domain->regs->map,
domain->bits.map, 0);
pm_runtime_disable(domain->dev);
@@ -1098,6 +1118,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
domain = pd_pdev->dev.platform_data;
domain->regmap = regmap;
+ domain->regs = domain_data->pgc_regs;
domain->genpd.power_on = imx_pgc_power_up;
domain->genpd.power_off = imx_pgc_power_down;
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 2/7] soc: imx: gpcv2: add support for i.MX8MP power domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
This adds driver support for all the GPC power domains found on
the i.MX8MP SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 386 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 01f46b078df3..0bc3c00426e9 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -21,10 +21,12 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
#define GPC_LPCR_A_CORE_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
+#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
@@ -65,6 +67,29 @@
#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
+#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
+#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
+#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
+#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
+#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
+#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
+#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
+#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
+#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
+#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
+#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
+#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
+#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
+#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
+#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
+#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
+#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
+#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
+#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
+
+#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
+#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -107,8 +132,30 @@
#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
+#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
+#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
+#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
+#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
+#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
+#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
+#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
+#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
+#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
+#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
+#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
+#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
+#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
+#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
+#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
+#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
+#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
+#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
+#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
+#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
+#define IMX8MP_GPC_PU_PWRHSK 0x190
#define GPC_PU_PWRHSK 0x1fc
#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
@@ -118,7 +165,6 @@
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
-
#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
@@ -137,6 +183,21 @@
#define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
+#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
+#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
+#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
+#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
+#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
+#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
+#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
+#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
+#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
+#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
+#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
+#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
+#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
+#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -179,6 +240,28 @@
#define IMX8MN_PGC_GPUMIX 23
#define IMX8MN_PGC_DISPMIX 26
+#define IMX8MP_PGC_NOC 9
+#define IMX8MP_PGC_MIPI1 12
+#define IMX8MP_PGC_PCIE 13
+#define IMX8MP_PGC_USB1 14
+#define IMX8MP_PGC_USB2 15
+#define IMX8MP_PGC_MLMIX 16
+#define IMX8MP_PGC_AUDIOMIX 17
+#define IMX8MP_PGC_GPU2D 18
+#define IMX8MP_PGC_GPUMIX 19
+#define IMX8MP_PGC_VPUMIX 20
+#define IMX8MP_PGC_GPU3D 21
+#define IMX8MP_PGC_MEDIAMIX 22
+#define IMX8MP_PGC_VPU_G1 23
+#define IMX8MP_PGC_VPU_G2 24
+#define IMX8MP_PGC_VPU_VC8000E 25
+#define IMX8MP_PGC_HDMIMIX 26
+#define IMX8MP_PGC_HDMI 27
+#define IMX8MP_PGC_MIPI2 28
+#define IMX8MP_PGC_HSIOMIX 29
+#define IMX8MP_PGC_MEDIA_ISP_DWP 30
+#define IMX8MP_PGC_DDRMIX 31
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -212,6 +295,9 @@ struct imx_pgc_domain {
const int voltage;
const bool keep_clocks;
struct device *dev;
+
+ unsigned int pgc_sw_pup_reg;
+ unsigned int pgc_sw_pdn_reg;
};
struct imx_pgc_domain_data {
@@ -824,6 +910,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
.pgc_regs = &imx7_pgc_regs,
};
+static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
+ [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
+ .genpd = {
+ .name = "mipi-phy1",
+ },
+ .bits = {
+ .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
+ .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MIPI1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
+ .genpd = {
+ .name = "pcie-phy1",
+ },
+ .bits = {
+ .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
+ .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_PCIE),
+ },
+
+ [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
+ .map = IMX8MP_USB1_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_USB1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
+ .map = IMX8MP_USB2_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_USB2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MLMIX] = {
+ .genpd = {
+ .name = "mlmix",
+ },
+ .bits = {
+ .pxx = IMX8MP_MLMIX_Pxx_REQ,
+ .map = IMX8MP_MLMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_MLMIX_PWRDNREQN,
+ .hskack = IMX8MP_MLMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MLMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
+ .genpd = {
+ .name = "audiomix",
+ },
+ .bits = {
+ .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
+ .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
+ .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPU2D] = {
+ .genpd = {
+ .name = "gpu2d",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_2D_Pxx_REQ,
+ .map = IMX8MP_GPU2D_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPU2D),
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPUMIX] = {
+ .genpd = {
+ .name = "gpumix",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
+ .map = IMX8MP_GPUMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
+ .hskack = IMX8MP_GPUMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPUMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPUMIX] = {
+ .genpd = {
+ .name = "vpumix",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
+ .map = IMX8MP_VPUMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
+ .hskack = IMX8MP_VPUMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPUMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPU3D] = {
+ .genpd = {
+ .name = "gpu3d",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_3D_Pxx_REQ,
+ .map = IMX8MP_GPU3D_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPU3D),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
+ .genpd = {
+ .name = "mediamix",
+ },
+ .bits = {
+ .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
+ .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
+ .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_G1] = {
+ .genpd = {
+ .name = "vpu-g1",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_G1_Pxx_REQ,
+ .map = IMX8MP_VPU_G1_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_G1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_G2] = {
+ .genpd = {
+ .name = "vpu-g2",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_G2_Pxx_REQ,
+ .map = IMX8MP_VPU_G2_A53_DOMAIN
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_G2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
+ .genpd = {
+ .name = "vpu-h1",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
+ .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
+ },
+
+ [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
+ .genpd = {
+ .name = "hdmimix",
+ },
+ .bits = {
+ .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
+ .map = IMX8MP_HDMIMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
+ .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HDMIMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
+ .genpd = {
+ .name = "hdmi-phy",
+ },
+ .bits = {
+ .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
+ .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HDMI),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
+ .genpd = {
+ .name = "mipi-phy2",
+ },
+ .bits = {
+ .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
+ .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MIPI2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
+ .genpd = {
+ .name = "hsiomix",
+ },
+ .bits = {
+ .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
+ .map = IMX8MP_HSIOMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
+ .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HSIOMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
+ .genpd = {
+ .name = "mediamix-isp-dwp",
+ },
+ .bits = {
+ .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
+ .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
+ },
+};
+
+static const struct regmap_range imx8mp_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ IMX8MP_GPC_PGC_CPU_MAPPING),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
+ GPC_PGC_SR(IMX8MP_PGC_NOC)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
+ GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
+ GPC_PGC_SR(IMX8MP_PGC_PCIE)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
+ GPC_PGC_SR(IMX8MP_PGC_USB1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
+ GPC_PGC_SR(IMX8MP_PGC_USB2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
+ GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
+ GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
+ GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
+ GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
+ GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
+ GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
+ GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
+ GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
+ GPC_PGC_SR(IMX8MP_PGC_HDMI)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
+ GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
+ GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
+ GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
+ GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
+};
+
+static const struct regmap_access_table imx8mp_access_table = {
+ .yes_ranges = imx8mp_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
+};
+
+static const struct imx_pgc_regs imx8mp_pgc_regs = {
+ .map = IMX8MP_GPC_PGC_CPU_MAPPING,
+ .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
+ .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
+ .hsk = IMX8MP_GPC_PU_PWRHSK,
+};
+static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
+ .domains = imx8mp_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
+ .reg_access_table = &imx8mp_access_table,
+ .pgc_regs = &imx8mp_pgc_regs,
+};
+
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
.genpd = {
@@ -1119,6 +1502,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
domain = pd_pdev->dev.platform_data;
domain->regmap = regmap;
domain->regs = domain_data->pgc_regs;
+
domain->genpd.power_on = imx_pgc_power_up;
domain->genpd.power_off = imx_pgc_power_down;
@@ -1140,6 +1524,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
+ { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
{ }
};
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 2/7] soc: imx: gpcv2: add support for i.MX8MP power domains
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
This adds driver support for all the GPC power domains found on
the i.MX8MP SoC.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++-
1 file changed, 386 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
index 01f46b078df3..0bc3c00426e9 100644
--- a/drivers/soc/imx/gpcv2.c
+++ b/drivers/soc/imx/gpcv2.c
@@ -21,10 +21,12 @@
#include <dt-bindings/power/imx8mq-power.h>
#include <dt-bindings/power/imx8mm-power.h>
#include <dt-bindings/power/imx8mn-power.h>
+#include <dt-bindings/power/imx8mp-power.h>
#define GPC_LPCR_A_CORE_BSC 0x000
#define GPC_PGC_CPU_MAPPING 0x0ec
+#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
#define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
#define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
@@ -65,6 +67,29 @@
#define IMX8MN_OTG1_A53_DOMAIN BIT(4)
#define IMX8MN_MIPI_A53_DOMAIN BIT(2)
+#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
+#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
+#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
+#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
+#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
+#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
+#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
+#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
+#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
+#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
+#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
+#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
+#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
+#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
+#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
+#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
+#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
+#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
+#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
+
+#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
+#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
+
#define GPC_PU_PGC_SW_PUP_REQ 0x0f8
#define GPC_PU_PGC_SW_PDN_REQ 0x104
@@ -107,8 +132,30 @@
#define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
#define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
+#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
+#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
+#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
+#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
+#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
+#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
+#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
+#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
+#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
+#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
+#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
+#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
+#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
+#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
+#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
+#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
+#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
+#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
+#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
+#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
+
#define GPC_M4_PU_PDN_FLG 0x1bc
+#define IMX8MP_GPC_PU_PWRHSK 0x190
#define GPC_PU_PWRHSK 0x1fc
#define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
@@ -118,7 +165,6 @@
#define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
#define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
-
#define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
#define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
#define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
@@ -137,6 +183,21 @@
#define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
#define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
+#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
+#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
+#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
+#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
+#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
+#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
+#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
+#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
+#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
+#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
+#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
+#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
+#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
+#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
+
/*
* The PGC offset values in Reference Manual
* (Rev. 1, 01/2018 and the older ones) GPC chapter's
@@ -179,6 +240,28 @@
#define IMX8MN_PGC_GPUMIX 23
#define IMX8MN_PGC_DISPMIX 26
+#define IMX8MP_PGC_NOC 9
+#define IMX8MP_PGC_MIPI1 12
+#define IMX8MP_PGC_PCIE 13
+#define IMX8MP_PGC_USB1 14
+#define IMX8MP_PGC_USB2 15
+#define IMX8MP_PGC_MLMIX 16
+#define IMX8MP_PGC_AUDIOMIX 17
+#define IMX8MP_PGC_GPU2D 18
+#define IMX8MP_PGC_GPUMIX 19
+#define IMX8MP_PGC_VPUMIX 20
+#define IMX8MP_PGC_GPU3D 21
+#define IMX8MP_PGC_MEDIAMIX 22
+#define IMX8MP_PGC_VPU_G1 23
+#define IMX8MP_PGC_VPU_G2 24
+#define IMX8MP_PGC_VPU_VC8000E 25
+#define IMX8MP_PGC_HDMIMIX 26
+#define IMX8MP_PGC_HDMI 27
+#define IMX8MP_PGC_MIPI2 28
+#define IMX8MP_PGC_HSIOMIX 29
+#define IMX8MP_PGC_MEDIA_ISP_DWP 30
+#define IMX8MP_PGC_DDRMIX 31
+
#define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
#define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
@@ -212,6 +295,9 @@ struct imx_pgc_domain {
const int voltage;
const bool keep_clocks;
struct device *dev;
+
+ unsigned int pgc_sw_pup_reg;
+ unsigned int pgc_sw_pdn_reg;
};
struct imx_pgc_domain_data {
@@ -824,6 +910,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
.pgc_regs = &imx7_pgc_regs,
};
+static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
+ [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
+ .genpd = {
+ .name = "mipi-phy1",
+ },
+ .bits = {
+ .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
+ .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MIPI1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
+ .genpd = {
+ .name = "pcie-phy1",
+ },
+ .bits = {
+ .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
+ .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_PCIE),
+ },
+
+ [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
+ .genpd = {
+ .name = "usb-otg1",
+ },
+ .bits = {
+ .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
+ .map = IMX8MP_USB1_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_USB1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
+ .genpd = {
+ .name = "usb-otg2",
+ },
+ .bits = {
+ .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
+ .map = IMX8MP_USB2_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_USB2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MLMIX] = {
+ .genpd = {
+ .name = "mlmix",
+ },
+ .bits = {
+ .pxx = IMX8MP_MLMIX_Pxx_REQ,
+ .map = IMX8MP_MLMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_MLMIX_PWRDNREQN,
+ .hskack = IMX8MP_MLMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MLMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
+ .genpd = {
+ .name = "audiomix",
+ },
+ .bits = {
+ .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
+ .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
+ .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPU2D] = {
+ .genpd = {
+ .name = "gpu2d",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_2D_Pxx_REQ,
+ .map = IMX8MP_GPU2D_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPU2D),
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPUMIX] = {
+ .genpd = {
+ .name = "gpumix",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
+ .map = IMX8MP_GPUMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
+ .hskack = IMX8MP_GPUMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPUMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPUMIX] = {
+ .genpd = {
+ .name = "vpumix",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
+ .map = IMX8MP_VPUMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
+ .hskack = IMX8MP_VPUMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPUMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_GPU3D] = {
+ .genpd = {
+ .name = "gpu3d",
+ },
+ .bits = {
+ .pxx = IMX8MP_GPU_3D_Pxx_REQ,
+ .map = IMX8MP_GPU3D_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_GPU3D),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
+ .genpd = {
+ .name = "mediamix",
+ },
+ .bits = {
+ .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
+ .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
+ .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_G1] = {
+ .genpd = {
+ .name = "vpu-g1",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_G1_Pxx_REQ,
+ .map = IMX8MP_VPU_G1_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_G1),
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_G2] = {
+ .genpd = {
+ .name = "vpu-g2",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_G2_Pxx_REQ,
+ .map = IMX8MP_VPU_G2_A53_DOMAIN
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_G2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
+ .genpd = {
+ .name = "vpu-h1",
+ },
+ .bits = {
+ .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
+ .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
+ },
+
+ [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
+ .genpd = {
+ .name = "hdmimix",
+ },
+ .bits = {
+ .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
+ .map = IMX8MP_HDMIMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
+ .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HDMIMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
+ .genpd = {
+ .name = "hdmi-phy",
+ },
+ .bits = {
+ .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
+ .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HDMI),
+ },
+
+ [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
+ .genpd = {
+ .name = "mipi-phy2",
+ },
+ .bits = {
+ .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
+ .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MIPI2),
+ },
+
+ [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
+ .genpd = {
+ .name = "hsiomix",
+ },
+ .bits = {
+ .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
+ .map = IMX8MP_HSIOMIX_A53_DOMAIN,
+ .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
+ .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
+ },
+ .pgc = BIT(IMX8MP_PGC_HSIOMIX),
+ .keep_clocks = true,
+ },
+
+ [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
+ .genpd = {
+ .name = "mediamix-isp-dwp",
+ },
+ .bits = {
+ .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
+ .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
+ },
+ .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
+ },
+};
+
+static const struct regmap_range imx8mp_yes_ranges[] = {
+ regmap_reg_range(GPC_LPCR_A_CORE_BSC,
+ IMX8MP_GPC_PGC_CPU_MAPPING),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
+ GPC_PGC_SR(IMX8MP_PGC_NOC)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
+ GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
+ GPC_PGC_SR(IMX8MP_PGC_PCIE)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
+ GPC_PGC_SR(IMX8MP_PGC_USB1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
+ GPC_PGC_SR(IMX8MP_PGC_USB2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
+ GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
+ GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
+ GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
+ GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
+ GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
+ GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
+ GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
+ GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
+ GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
+ GPC_PGC_SR(IMX8MP_PGC_HDMI)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
+ GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
+ GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
+ GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
+ regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
+ GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
+};
+
+static const struct regmap_access_table imx8mp_access_table = {
+ .yes_ranges = imx8mp_yes_ranges,
+ .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
+};
+
+static const struct imx_pgc_regs imx8mp_pgc_regs = {
+ .map = IMX8MP_GPC_PGC_CPU_MAPPING,
+ .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
+ .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
+ .hsk = IMX8MP_GPC_PU_PWRHSK,
+};
+static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
+ .domains = imx8mp_pgc_domains,
+ .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
+ .reg_access_table = &imx8mp_access_table,
+ .pgc_regs = &imx8mp_pgc_regs,
+};
+
static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
[IMX8MN_POWER_DOMAIN_HSIOMIX] = {
.genpd = {
@@ -1119,6 +1502,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
domain = pd_pdev->dev.platform_data;
domain->regmap = regmap;
domain->regs = domain_data->pgc_regs;
+
domain->genpd.power_on = imx_pgc_power_up;
domain->genpd.power_off = imx_pgc_power_down;
@@ -1140,6 +1524,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
{ .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
{ .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
{ .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
+ { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
{ .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
{ }
};
--
2.30.2
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^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 3/7] soc: imx: add i.MX8MP HSIO blk-ctrl
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
structure of the blk-ctrls in the previous SoCs. Add a new file for those
with currently only the HSIO blk-ctrl being supported. Others will be added
later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++++++++++++++
2 files changed, 447 insertions(+)
create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 8a707077914c..63cd29f6d4d2 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
new file mode 100644
index 000000000000..e832c007b063
--- /dev/null
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/power/imx8mp-power.h>
+
+#define GPR_REG0 0x0
+#define PCIE_CLOCK_MODULE_EN BIT(0)
+#define USB_CLOCK_MODULE_EN BIT(1)
+
+struct imx8mp_hsio_blk_ctrl_domain;
+
+struct imx8mp_hsio_blk_ctrl {
+ struct device *dev;
+ struct notifier_block power_nb;
+ struct device *bus_power_dev;
+ struct regmap *regmap;
+ struct imx8mp_hsio_blk_ctrl_domain *domains;
+ struct genpd_onecell_data onecell_data;
+};
+
+struct imx8mp_hsio_blk_ctrl_domain_data {
+ const char *name;
+ const char *clk_name;
+ const char *gpc_name;
+};
+
+struct imx8mp_hsio_blk_ctrl_domain {
+ struct generic_pm_domain genpd;
+ struct clk *clk;
+ struct device *power_dev;
+ struct imx8mp_hsio_blk_ctrl *bc;
+ int id;
+};
+
+static inline struct imx8mp_hsio_blk_ctrl_domain *
+to_imx8mp_hsio_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+ return container_of(genpd, struct imx8mp_hsio_blk_ctrl_domain, genpd);
+}
+
+static int imx8mp_hsio_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+ struct imx8mp_hsio_blk_ctrl_domain *domain =
+ to_imx8mp_hsio_blk_ctrl_domain(genpd);
+ struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
+ int ret;
+
+ /* make sure bus domain is awake */
+ ret = pm_runtime_resume_and_get(bc->bus_power_dev);
+ if (ret < 0) {
+ dev_err(bc->dev, "failed to power up bus domain\n");
+ return ret;
+ }
+
+ /* enable upstream and blk-ctrl clocks */
+ ret = clk_prepare_enable(domain->clk);
+ if (ret) {
+ dev_err(bc->dev, "failed to enable clocks\n");
+ goto bus_put;
+ }
+
+ switch (domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ break;
+ default:
+ break;
+ }
+
+ /* power up upstream GPC domain */
+ ret = pm_runtime_resume_and_get(domain->power_dev);
+ if (ret < 0) {
+ dev_err(bc->dev, "failed to power up peripheral domain\n");
+ goto clk_disable;
+ }
+
+ return 0;
+
+clk_disable:
+ clk_disable_unprepare(domain->clk);
+bus_put:
+ pm_runtime_put(bc->bus_power_dev);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+ struct imx8mp_hsio_blk_ctrl_domain *domain =
+ to_imx8mp_hsio_blk_ctrl_domain(genpd);
+ struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
+
+ /* disable clocks */
+ switch (domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
+ regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ break;
+ default:
+ break;
+ }
+
+ clk_disable_unprepare(domain->clk);
+
+ /* power down upstream GPC domain */
+ pm_runtime_put(domain->power_dev);
+
+ /* allow bus domain to suspend */
+ pm_runtime_put(bc->bus_power_dev);
+
+ return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+ struct genpd_onecell_data *onecell_data = data;
+ unsigned int index = args->args[0];
+
+ if (args->args_count != 1 ||
+ index >= onecell_data->num_domains)
+ return ERR_PTR(-EINVAL);
+
+ return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static const struct imx8mp_hsio_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
+ [IMX8MP_HSIOBLK_PD_USB] = {
+ .name = "hsioblk-usb",
+ .clk_name = "usb",
+ .gpc_name = "usb",
+ },
+ [IMX8MP_HSIOBLK_PD_USB_PHY1] = {
+ .name = "hsioblk-usb-phy1",
+ .gpc_name = "usb-phy1",
+ },
+ [IMX8MP_HSIOBLK_PD_USB_PHY2] = {
+ .name = "hsioblk-usb-phy2",
+ .gpc_name = "usb-phy2",
+ },
+ [IMX8MP_HSIOBLK_PD_PCIE] = {
+ .name = "hsioblk-pcie",
+ .clk_name = "pcie",
+ .gpc_name = "pcie",
+ },
+ [IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
+ .name = "hsioblk-pcie-phy",
+ .gpc_name = "pcie-phy",
+ },
+};
+
+static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = container_of(nb, struct imx8mp_hsio_blk_ctrl,
+ power_nb);
+ struct clk *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clk;
+ int ret;
+
+ switch (action) {
+ case GENPD_NOTIFY_ON:
+ /*
+ * enable USB clock for a moment for the power-on ADB handshake
+ * to proceed
+ */
+ ret = clk_prepare_enable(usb_clk);
+ if (ret)
+ return NOTIFY_BAD;
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+
+ udelay(5);
+
+ regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ clk_disable_unprepare(usb_clk);
+ break;
+ case GENPD_NOTIFY_PRE_OFF:
+ /* enable USB clock for the power-down ADB handshake to work */
+ ret = clk_prepare_enable(usb_clk);
+ if (ret)
+ return NOTIFY_BAD;
+
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case GENPD_NOTIFY_OFF:
+ clk_disable_unprepare(usb_clk);
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static int imx8mp_hsio_blk_ctrl_probe(struct platform_device *pdev)
+{
+ int num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data);
+ struct device *dev = &pdev->dev;
+ struct imx8mp_hsio_blk_ctrl *bc;
+ void __iomem *base;
+ int i, ret;
+
+ static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x24,
+ };
+
+ bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+ if (!bc)
+ return -ENOMEM;
+
+ bc->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
+ if (IS_ERR(bc->regmap))
+ return dev_err_probe(dev, PTR_ERR(bc->regmap),
+ "failed to init regmap\n");
+
+ bc->domains = devm_kcalloc(dev, num_domains,
+ sizeof(struct imx8mp_hsio_blk_ctrl_domain),
+ GFP_KERNEL);
+ if (!bc->domains)
+ return -ENOMEM;
+
+ bc->onecell_data.num_domains = num_domains;
+ bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+ bc->onecell_data.domains =
+ devm_kcalloc(dev, num_domains,
+ sizeof(struct generic_pm_domain *), GFP_KERNEL);
+ if (!bc->onecell_data.domains)
+ return -ENOMEM;
+
+ bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+ if (IS_ERR(bc->bus_power_dev))
+ return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+ "failed to attach bus power domain\n");
+
+ for (i = 0; i < num_domains; i++) {
+ const struct imx8mp_hsio_blk_ctrl_domain_data *data =
+ &imx8mp_hsio_domain_data[i];
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ if (data->clk_name) {
+ domain->clk = devm_clk_get(dev, data->clk_name);
+ if (IS_ERR(domain->clk)) {
+ ret = PTR_ERR(domain->clk);
+ dev_err_probe(dev, ret,
+ "failed to get clock %s\n",
+ data->clk_name);
+ goto cleanup_pds;
+ }
+ }
+
+ domain->power_dev =
+ dev_pm_domain_attach_by_name(dev, data->gpc_name);
+ if (IS_ERR(domain->power_dev)) {
+ dev_err_probe(dev, PTR_ERR(domain->power_dev),
+ "failed to attach power domain %s\n",
+ data->gpc_name);
+ ret = PTR_ERR(domain->power_dev);
+ goto cleanup_pds;
+ }
+
+ domain->genpd.name = data->name;
+ domain->genpd.power_on = imx8mp_hsio_blk_ctrl_power_on;
+ domain->genpd.power_off = imx8mp_hsio_blk_ctrl_power_off;
+ domain->bc = bc;
+ domain->id = i;
+
+ ret = pm_genpd_init(&domain->genpd, NULL, true);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to init power domain\n");
+ dev_pm_domain_detach(domain->power_dev, true);
+ goto cleanup_pds;
+ }
+
+ /*
+ * We use runtime PM to trigger power on/off of the upstream GPC
+ * domain, as a strict hierarchical parent/child power domain
+ * setup doesn't allow us to meet the sequencing requirements.
+ * This means we have nested locking of genpd locks, without the
+ * nesting being visible at the genpd level, so we need a
+ * separate lock class to make lockdep aware of the fact that
+ * this are separate domain locks that can be nested without a
+ * self-deadlock.
+ */
+ lockdep_set_class(&domain->genpd.mlock,
+ &blk_ctrl_genpd_lock_class);
+
+ bc->onecell_data.domains[i] = &domain->genpd;
+ }
+
+ ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to add power domain provider\n");
+ goto cleanup_pds;
+ }
+
+ bc->power_nb.notifier_call = imx8mp_hsio_power_notifier;
+ ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to add power notifier\n");
+ goto cleanup_provider;
+ }
+
+ dev_set_drvdata(dev, bc);
+
+ return 0;
+
+cleanup_provider:
+ of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+ for (i--; i >= 0; i--) {
+ pm_genpd_remove(&bc->domains[i].genpd);
+ dev_pm_domain_detach(bc->domains[i].power_dev, true);
+ }
+
+ dev_pm_domain_detach(bc->bus_power_dev, true);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_remove(struct platform_device *pdev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ of_genpd_del_provider(pdev->dev.of_node);
+
+ for (i = 0; bc->onecell_data.num_domains; i++) {
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ pm_genpd_remove(&domain->genpd);
+ dev_pm_domain_detach(domain->power_dev, true);
+ }
+
+ dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+ dev_pm_domain_detach(bc->bus_power_dev, true);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8mp_hsio_blk_ctrl_suspend(struct device *dev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
+ int ret, i;
+
+ /*
+ * This may look strange, but is done so the generic PM_SLEEP code
+ * can power down our domains and more importantly power them up again
+ * after resume, without tripping over our usage of runtime PM to
+ * control the upstream GPC domains. Things happen in the right order
+ * in the system suspend/resume paths due to the device parent/child
+ * hierarchy.
+ */
+ ret = pm_runtime_get_sync(bc->bus_power_dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(bc->bus_power_dev);
+ return ret;
+ }
+
+ for (i = 0; i < bc->onecell_data.num_domains; i++) {
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ ret = pm_runtime_get_sync(domain->power_dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(domain->power_dev);
+ goto out_fail;
+ }
+ }
+
+ return 0;
+
+out_fail:
+ for (i--; i >= 0; i--)
+ pm_runtime_put(bc->domains[i].power_dev);
+
+ pm_runtime_put(bc->bus_power_dev);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_resume(struct device *dev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < bc->onecell_data.num_domains; i++)
+ pm_runtime_put(bc->domains[i].power_dev);
+
+ pm_runtime_put(bc->bus_power_dev);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8mp_hsio_blk_ctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(imx8mp_hsio_blk_ctrl_suspend,
+ imx8mp_hsio_blk_ctrl_resume)
+};
+
+static const struct of_device_id imx8mp_hsio_blk_ctrl_of_match[] = {
+ {
+ .compatible = "fsl,imx8mp-hsio-blk-ctrl",
+ }, {
+ /* Sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8mp_hsio_blk_ctrl_driver = {
+ .probe = imx8mp_hsio_blk_ctrl_probe,
+ .remove = imx8mp_hsio_blk_ctrl_remove,
+ .driver = {
+ .name = "imx8mp-hsio-blk-ctrl",
+ .pm = &imx8mp_hsio_blk_ctrl_pm_ops,
+ .of_match_table = imx8mp_hsio_blk_ctrl_of_match,
+ },
+};
+module_platform_driver(imx8mp_hsio_blk_ctrl_driver);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 3/7] soc: imx: add i.MX8MP HSIO blk-ctrl
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The i.MX8MP added some blk-ctrl peripherals that don't follow the regular
structure of the blk-ctrls in the previous SoCs. Add a new file for those
with currently only the HSIO blk-ctrl being supported. Others will be added
later on.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
drivers/soc/imx/Makefile | 1 +
drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++++++++++++++
2 files changed, 447 insertions(+)
create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
diff --git a/drivers/soc/imx/Makefile b/drivers/soc/imx/Makefile
index 8a707077914c..63cd29f6d4d2 100644
--- a/drivers/soc/imx/Makefile
+++ b/drivers/soc/imx/Makefile
@@ -6,3 +6,4 @@ obj-$(CONFIG_HAVE_IMX_GPC) += gpc.o
obj-$(CONFIG_IMX_GPCV2_PM_DOMAINS) += gpcv2.o
obj-$(CONFIG_SOC_IMX8M) += soc-imx8m.o
obj-$(CONFIG_SOC_IMX8M) += imx8m-blk-ctrl.o
+obj-$(CONFIG_SOC_IMX8M) += imx8mp-blk-ctrl.o
diff --git a/drivers/soc/imx/imx8mp-blk-ctrl.c b/drivers/soc/imx/imx8mp-blk-ctrl.c
new file mode 100644
index 000000000000..e832c007b063
--- /dev/null
+++ b/drivers/soc/imx/imx8mp-blk-ctrl.c
@@ -0,0 +1,446 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+/*
+ * Copyright 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de>
+ */
+
+#include <linux/clk.h>
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_domain.h>
+#include <linux/pm_runtime.h>
+#include <linux/regmap.h>
+
+#include <dt-bindings/power/imx8mp-power.h>
+
+#define GPR_REG0 0x0
+#define PCIE_CLOCK_MODULE_EN BIT(0)
+#define USB_CLOCK_MODULE_EN BIT(1)
+
+struct imx8mp_hsio_blk_ctrl_domain;
+
+struct imx8mp_hsio_blk_ctrl {
+ struct device *dev;
+ struct notifier_block power_nb;
+ struct device *bus_power_dev;
+ struct regmap *regmap;
+ struct imx8mp_hsio_blk_ctrl_domain *domains;
+ struct genpd_onecell_data onecell_data;
+};
+
+struct imx8mp_hsio_blk_ctrl_domain_data {
+ const char *name;
+ const char *clk_name;
+ const char *gpc_name;
+};
+
+struct imx8mp_hsio_blk_ctrl_domain {
+ struct generic_pm_domain genpd;
+ struct clk *clk;
+ struct device *power_dev;
+ struct imx8mp_hsio_blk_ctrl *bc;
+ int id;
+};
+
+static inline struct imx8mp_hsio_blk_ctrl_domain *
+to_imx8mp_hsio_blk_ctrl_domain(struct generic_pm_domain *genpd)
+{
+ return container_of(genpd, struct imx8mp_hsio_blk_ctrl_domain, genpd);
+}
+
+static int imx8mp_hsio_blk_ctrl_power_on(struct generic_pm_domain *genpd)
+{
+ struct imx8mp_hsio_blk_ctrl_domain *domain =
+ to_imx8mp_hsio_blk_ctrl_domain(genpd);
+ struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
+ int ret;
+
+ /* make sure bus domain is awake */
+ ret = pm_runtime_resume_and_get(bc->bus_power_dev);
+ if (ret < 0) {
+ dev_err(bc->dev, "failed to power up bus domain\n");
+ return ret;
+ }
+
+ /* enable upstream and blk-ctrl clocks */
+ ret = clk_prepare_enable(domain->clk);
+ if (ret) {
+ dev_err(bc->dev, "failed to enable clocks\n");
+ goto bus_put;
+ }
+
+ switch (domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ regmap_set_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ break;
+ default:
+ break;
+ }
+
+ /* power up upstream GPC domain */
+ ret = pm_runtime_resume_and_get(domain->power_dev);
+ if (ret < 0) {
+ dev_err(bc->dev, "failed to power up peripheral domain\n");
+ goto clk_disable;
+ }
+
+ return 0;
+
+clk_disable:
+ clk_disable_unprepare(domain->clk);
+bus_put:
+ pm_runtime_put(bc->bus_power_dev);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_power_off(struct generic_pm_domain *genpd)
+{
+ struct imx8mp_hsio_blk_ctrl_domain *domain =
+ to_imx8mp_hsio_blk_ctrl_domain(genpd);
+ struct imx8mp_hsio_blk_ctrl *bc = domain->bc;
+
+ /* disable clocks */
+ switch (domain->id) {
+ case IMX8MP_HSIOBLK_PD_USB:
+ regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case IMX8MP_HSIOBLK_PD_PCIE:
+ regmap_clear_bits(bc->regmap, GPR_REG0, PCIE_CLOCK_MODULE_EN);
+ break;
+ default:
+ break;
+ }
+
+ clk_disable_unprepare(domain->clk);
+
+ /* power down upstream GPC domain */
+ pm_runtime_put(domain->power_dev);
+
+ /* allow bus domain to suspend */
+ pm_runtime_put(bc->bus_power_dev);
+
+ return 0;
+}
+
+static struct generic_pm_domain *
+imx8m_blk_ctrl_xlate(struct of_phandle_args *args, void *data)
+{
+ struct genpd_onecell_data *onecell_data = data;
+ unsigned int index = args->args[0];
+
+ if (args->args_count != 1 ||
+ index >= onecell_data->num_domains)
+ return ERR_PTR(-EINVAL);
+
+ return onecell_data->domains[index];
+}
+
+static struct lock_class_key blk_ctrl_genpd_lock_class;
+
+static const struct imx8mp_hsio_blk_ctrl_domain_data imx8mp_hsio_domain_data[] = {
+ [IMX8MP_HSIOBLK_PD_USB] = {
+ .name = "hsioblk-usb",
+ .clk_name = "usb",
+ .gpc_name = "usb",
+ },
+ [IMX8MP_HSIOBLK_PD_USB_PHY1] = {
+ .name = "hsioblk-usb-phy1",
+ .gpc_name = "usb-phy1",
+ },
+ [IMX8MP_HSIOBLK_PD_USB_PHY2] = {
+ .name = "hsioblk-usb-phy2",
+ .gpc_name = "usb-phy2",
+ },
+ [IMX8MP_HSIOBLK_PD_PCIE] = {
+ .name = "hsioblk-pcie",
+ .clk_name = "pcie",
+ .gpc_name = "pcie",
+ },
+ [IMX8MP_HSIOBLK_PD_PCIE_PHY] = {
+ .name = "hsioblk-pcie-phy",
+ .gpc_name = "pcie-phy",
+ },
+};
+
+static int imx8mp_hsio_power_notifier(struct notifier_block *nb,
+ unsigned long action, void *data)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = container_of(nb, struct imx8mp_hsio_blk_ctrl,
+ power_nb);
+ struct clk *usb_clk = bc->domains[IMX8MP_HSIOBLK_PD_USB].clk;
+ int ret;
+
+ switch (action) {
+ case GENPD_NOTIFY_ON:
+ /*
+ * enable USB clock for a moment for the power-on ADB handshake
+ * to proceed
+ */
+ ret = clk_prepare_enable(usb_clk);
+ if (ret)
+ return NOTIFY_BAD;
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+
+ udelay(5);
+
+ regmap_clear_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ clk_disable_unprepare(usb_clk);
+ break;
+ case GENPD_NOTIFY_PRE_OFF:
+ /* enable USB clock for the power-down ADB handshake to work */
+ ret = clk_prepare_enable(usb_clk);
+ if (ret)
+ return NOTIFY_BAD;
+
+ regmap_set_bits(bc->regmap, GPR_REG0, USB_CLOCK_MODULE_EN);
+ break;
+ case GENPD_NOTIFY_OFF:
+ clk_disable_unprepare(usb_clk);
+ break;
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static int imx8mp_hsio_blk_ctrl_probe(struct platform_device *pdev)
+{
+ int num_domains = ARRAY_SIZE(imx8mp_hsio_domain_data);
+ struct device *dev = &pdev->dev;
+ struct imx8mp_hsio_blk_ctrl *bc;
+ void __iomem *base;
+ int i, ret;
+
+ static const struct regmap_config regmap_config = {
+ .reg_bits = 32,
+ .val_bits = 32,
+ .reg_stride = 4,
+ .max_register = 0x24,
+ };
+
+ bc = devm_kzalloc(dev, sizeof(*bc), GFP_KERNEL);
+ if (!bc)
+ return -ENOMEM;
+
+ bc->dev = dev;
+
+ base = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(base))
+ return PTR_ERR(base);
+
+ bc->regmap = devm_regmap_init_mmio(dev, base, ®map_config);
+ if (IS_ERR(bc->regmap))
+ return dev_err_probe(dev, PTR_ERR(bc->regmap),
+ "failed to init regmap\n");
+
+ bc->domains = devm_kcalloc(dev, num_domains,
+ sizeof(struct imx8mp_hsio_blk_ctrl_domain),
+ GFP_KERNEL);
+ if (!bc->domains)
+ return -ENOMEM;
+
+ bc->onecell_data.num_domains = num_domains;
+ bc->onecell_data.xlate = imx8m_blk_ctrl_xlate;
+ bc->onecell_data.domains =
+ devm_kcalloc(dev, num_domains,
+ sizeof(struct generic_pm_domain *), GFP_KERNEL);
+ if (!bc->onecell_data.domains)
+ return -ENOMEM;
+
+ bc->bus_power_dev = genpd_dev_pm_attach_by_name(dev, "bus");
+ if (IS_ERR(bc->bus_power_dev))
+ return dev_err_probe(dev, PTR_ERR(bc->bus_power_dev),
+ "failed to attach bus power domain\n");
+
+ for (i = 0; i < num_domains; i++) {
+ const struct imx8mp_hsio_blk_ctrl_domain_data *data =
+ &imx8mp_hsio_domain_data[i];
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ if (data->clk_name) {
+ domain->clk = devm_clk_get(dev, data->clk_name);
+ if (IS_ERR(domain->clk)) {
+ ret = PTR_ERR(domain->clk);
+ dev_err_probe(dev, ret,
+ "failed to get clock %s\n",
+ data->clk_name);
+ goto cleanup_pds;
+ }
+ }
+
+ domain->power_dev =
+ dev_pm_domain_attach_by_name(dev, data->gpc_name);
+ if (IS_ERR(domain->power_dev)) {
+ dev_err_probe(dev, PTR_ERR(domain->power_dev),
+ "failed to attach power domain %s\n",
+ data->gpc_name);
+ ret = PTR_ERR(domain->power_dev);
+ goto cleanup_pds;
+ }
+
+ domain->genpd.name = data->name;
+ domain->genpd.power_on = imx8mp_hsio_blk_ctrl_power_on;
+ domain->genpd.power_off = imx8mp_hsio_blk_ctrl_power_off;
+ domain->bc = bc;
+ domain->id = i;
+
+ ret = pm_genpd_init(&domain->genpd, NULL, true);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to init power domain\n");
+ dev_pm_domain_detach(domain->power_dev, true);
+ goto cleanup_pds;
+ }
+
+ /*
+ * We use runtime PM to trigger power on/off of the upstream GPC
+ * domain, as a strict hierarchical parent/child power domain
+ * setup doesn't allow us to meet the sequencing requirements.
+ * This means we have nested locking of genpd locks, without the
+ * nesting being visible at the genpd level, so we need a
+ * separate lock class to make lockdep aware of the fact that
+ * this are separate domain locks that can be nested without a
+ * self-deadlock.
+ */
+ lockdep_set_class(&domain->genpd.mlock,
+ &blk_ctrl_genpd_lock_class);
+
+ bc->onecell_data.domains[i] = &domain->genpd;
+ }
+
+ ret = of_genpd_add_provider_onecell(dev->of_node, &bc->onecell_data);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to add power domain provider\n");
+ goto cleanup_pds;
+ }
+
+ bc->power_nb.notifier_call = imx8mp_hsio_power_notifier;
+ ret = dev_pm_genpd_add_notifier(bc->bus_power_dev, &bc->power_nb);
+ if (ret) {
+ dev_err_probe(dev, ret, "failed to add power notifier\n");
+ goto cleanup_provider;
+ }
+
+ dev_set_drvdata(dev, bc);
+
+ return 0;
+
+cleanup_provider:
+ of_genpd_del_provider(dev->of_node);
+cleanup_pds:
+ for (i--; i >= 0; i--) {
+ pm_genpd_remove(&bc->domains[i].genpd);
+ dev_pm_domain_detach(bc->domains[i].power_dev, true);
+ }
+
+ dev_pm_domain_detach(bc->bus_power_dev, true);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_remove(struct platform_device *pdev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(&pdev->dev);
+ int i;
+
+ of_genpd_del_provider(pdev->dev.of_node);
+
+ for (i = 0; bc->onecell_data.num_domains; i++) {
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ pm_genpd_remove(&domain->genpd);
+ dev_pm_domain_detach(domain->power_dev, true);
+ }
+
+ dev_pm_genpd_remove_notifier(bc->bus_power_dev);
+
+ dev_pm_domain_detach(bc->bus_power_dev, true);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int imx8mp_hsio_blk_ctrl_suspend(struct device *dev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
+ int ret, i;
+
+ /*
+ * This may look strange, but is done so the generic PM_SLEEP code
+ * can power down our domains and more importantly power them up again
+ * after resume, without tripping over our usage of runtime PM to
+ * control the upstream GPC domains. Things happen in the right order
+ * in the system suspend/resume paths due to the device parent/child
+ * hierarchy.
+ */
+ ret = pm_runtime_get_sync(bc->bus_power_dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(bc->bus_power_dev);
+ return ret;
+ }
+
+ for (i = 0; i < bc->onecell_data.num_domains; i++) {
+ struct imx8mp_hsio_blk_ctrl_domain *domain = &bc->domains[i];
+
+ ret = pm_runtime_get_sync(domain->power_dev);
+ if (ret < 0) {
+ pm_runtime_put_noidle(domain->power_dev);
+ goto out_fail;
+ }
+ }
+
+ return 0;
+
+out_fail:
+ for (i--; i >= 0; i--)
+ pm_runtime_put(bc->domains[i].power_dev);
+
+ pm_runtime_put(bc->bus_power_dev);
+
+ return ret;
+}
+
+static int imx8mp_hsio_blk_ctrl_resume(struct device *dev)
+{
+ struct imx8mp_hsio_blk_ctrl *bc = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < bc->onecell_data.num_domains; i++)
+ pm_runtime_put(bc->domains[i].power_dev);
+
+ pm_runtime_put(bc->bus_power_dev);
+
+ return 0;
+}
+#endif
+
+static const struct dev_pm_ops imx8mp_hsio_blk_ctrl_pm_ops = {
+ SET_SYSTEM_SLEEP_PM_OPS(imx8mp_hsio_blk_ctrl_suspend,
+ imx8mp_hsio_blk_ctrl_resume)
+};
+
+static const struct of_device_id imx8mp_hsio_blk_ctrl_of_match[] = {
+ {
+ .compatible = "fsl,imx8mp-hsio-blk-ctrl",
+ }, {
+ /* Sentinel */
+ }
+};
+MODULE_DEVICE_TABLE(of, imx8m_blk_ctrl_of_match);
+
+static struct platform_driver imx8mp_hsio_blk_ctrl_driver = {
+ .probe = imx8mp_hsio_blk_ctrl_probe,
+ .remove = imx8mp_hsio_blk_ctrl_remove,
+ .driver = {
+ .name = "imx8mp-hsio-blk-ctrl",
+ .pm = &imx8mp_hsio_blk_ctrl_pm_ops,
+ .of_match_table = imx8mp_hsio_blk_ctrl_of_match,
+ },
+};
+module_platform_driver(imx8mp_hsio_blk_ctrl_driver);
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The USB controllers in the i.MX8MP are located inside the HSIO
power domain. Add the power-domains property to the DT binding
to be able to describe the hardware properly.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
index 974032b1fda0..048a3e4c1b60 100644
--- a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -49,6 +49,9 @@ properties:
- const: hsio
- const: suspend
+ power-domains:
+ maxItems: 1
+
# Required child node:
patternProperties:
@@ -65,12 +68,14 @@ required:
- clocks
- clock-names
- interrupts
+ - power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
usb3_0: usb@32f10100 {
compatible = "fsl,imx8mp-dwc3";
@@ -79,6 +84,7 @@ examples:
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
The USB controllers in the i.MX8MP are located inside the HSIO
power domain. Add the power-domains property to the DT binding
to be able to describe the hardware properly.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
---
Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
index 974032b1fda0..048a3e4c1b60 100644
--- a/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
+++ b/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml
@@ -49,6 +49,9 @@ properties:
- const: hsio
- const: suspend
+ power-domains:
+ maxItems: 1
+
# Required child node:
patternProperties:
@@ -65,12 +68,14 @@ required:
- clocks
- clock-names
- interrupts
+ - power-domains
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/imx8mp-clock.h>
+ #include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
usb3_0: usb@32f10100 {
compatible = "fsl,imx8mp-dwc3";
@@ -79,6 +84,7 @@ examples:
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
This adds the GPC and HSIO blk-ctrl nodes providing power control for
the high-speed (USB and PCIe) IOs.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
1 file changed, 65 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6b840c05dd77..69e533add539 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -475,6 +476,44 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mp-gpc";
+ reg = <0x303a0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_pcie_phy: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
+ };
+
+ pgc_usb1_phy: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
+ };
+
+ pgc_usb2_phy: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
+ };
+
+ pgc_hsiomix: power-domains@17 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_HSIO_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
@@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
};
};
+ aips4 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x32c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ hsio_blk_ctrl: blk-ctrl@32f10000 {
+ compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
+ reg = <0x32f10000 0x24>;
+ clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "usb", "pcie";
+ power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
+ <&pgc_usb1_phy>, <&pgc_usb2_phy>,
+ <&pgc_hsiomix>, <&pgc_pcie_phy>;
+ power-domain-names = "bus", "usb", "usb-phy1",
+ "usb-phy2", "pcie", "pcie-phy";
+ #power-domain-cells = <1>;
+ };
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
@@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
#phy-cells = <0>;
status = "disabled";
};
@@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
- assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
@@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
#phy-cells = <0>;
};
@@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
- assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
This adds the GPC and HSIO blk-ctrl nodes providing power control for
the high-speed (USB and PCIe) IOs.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
1 file changed, 65 insertions(+), 6 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 6b840c05dd77..69e533add539 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/imx8mp-clock.h>
+#include <dt-bindings/power/imx8mp-power.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -475,6 +476,44 @@ src: reset-controller@30390000 {
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
#reset-cells = <1>;
};
+
+ gpc: gpc@303a0000 {
+ compatible = "fsl,imx8mp-gpc";
+ reg = <0x303a0000 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ pgc {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ pgc_pcie_phy: power-domain@1 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
+ };
+
+ pgc_usb1_phy: power-domain@2 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
+ };
+
+ pgc_usb2_phy: power-domain@3 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
+ };
+
+ pgc_hsiomix: power-domains@17 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
+ clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
+ <&clk IMX8MP_CLK_HSIO_ROOT>;
+ assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
+ assigned-clock-rates = <500000000>;
+ };
+ };
+ };
};
aips2: bus@30400000 {
@@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
};
};
+ aips4 {
+ compatible = "fsl,aips-bus", "simple-bus";
+ reg = <0x32c00000 0x400000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ hsio_blk_ctrl: blk-ctrl@32f10000 {
+ compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
+ reg = <0x32f10000 0x24>;
+ clocks = <&clk IMX8MP_CLK_USB_ROOT>,
+ <&clk IMX8MP_CLK_PCIE_ROOT>;
+ clock-names = "usb", "pcie";
+ power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
+ <&pgc_usb1_phy>, <&pgc_usb2_phy>,
+ <&pgc_hsiomix>, <&pgc_pcie_phy>;
+ power-domain-names = "bus", "usb", "usb-phy1",
+ "usb-phy2", "pcie", "pcie-phy";
+ #power-domain-cells = <1>;
+ };
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
@@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
#phy-cells = <0>;
status = "disabled";
};
@@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
- assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy0>, <&usb3_phy0>;
phy-names = "usb2-phy", "usb3-phy";
@@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
clock-names = "phy";
assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
#phy-cells = <0>;
};
@@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "hsio", "suspend";
interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
#address-cells = <1>;
#size-cells = <1>;
dma-ranges = <0x40000000 0x40000000 0xc0000000>;
@@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
<&clk IMX8MP_CLK_USB_CORE_REF>,
<&clk IMX8MP_CLK_USB_ROOT>;
clock-names = "bus_early", "ref", "suspend";
- assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
- assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
- assigned-clock-rates = <500000000>;
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb3_phy1>, <&usb3_phy1>;
phy-names = "usb2-phy", "usb3-phy";
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 6/7] arm64: dts: imx8mp: add GPU power domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Add the power domains for the GPUs, which do not require any interaction with
a blk-ctrl, but are simply two PU domains nested inside a MIX domain.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 69e533add539..9f2c335cc7a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -503,6 +503,33 @@ pgc_usb2_phy: power-domain@3 {
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_gpu2d: power-domain@6 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
+ power-domains = <&pgc_gpumix>;
+ };
+
+ pgc_gpumix: power-domain@7 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>, <400000000>;
+ };
+
+ pgc_gpu3d: power-domain@9 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+ power-domains = <&pgc_gpumix>;
+ };
+
pgc_hsiomix: power-domains@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 6/7] arm64: dts: imx8mp: add GPU power domains
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Add the power domains for the GPUs, which do not require any interaction with
a blk-ctrl, but are simply two PU domains nested inside a MIX domain.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 27 +++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 69e533add539..9f2c335cc7a1 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -503,6 +503,33 @@ pgc_usb2_phy: power-domain@3 {
reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
};
+ pgc_gpu2d: power-domain@6 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>;
+ power-domains = <&pgc_gpumix>;
+ };
+
+ pgc_gpumix: power-domain@7 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPUMIX>;
+ clocks = <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>, <400000000>;
+ };
+
+ pgc_gpu3d: power-domain@9 {
+ #power-domain-cells = <0>;
+ reg = <IMX8MP_POWER_DOMAIN_GPU3D>;
+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+ power-domains = <&pgc_gpumix>;
+ };
+
pgc_hsiomix: power-domains@17 {
#power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:17 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP.
etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
[drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9f2c335cc7a1..3ded7314c473 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -980,6 +980,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
};
};
+ gpu3d: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x8000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
+ <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ clock-names = "core", "shader", "bus", "reg";
+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>, <800000000>;
+ power-domains = <&pgc_gpu3d>;
+ };
+
+ gpu2d: gpu@38008000 {
+ compatible = "vivante,gc";
+ reg = <0x38008000 0x8000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
+ <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ clock-names = "core", "bus", "reg";
+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>;
+ power-domains = <&pgc_gpu2d>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes
@ 2022-02-28 20:17 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-02-28 20:17 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP.
etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
[drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
---
arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
index 9f2c335cc7a1..3ded7314c473 100644
--- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
@@ -980,6 +980,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
};
};
+ gpu3d: gpu@38000000 {
+ compatible = "vivante,gc";
+ reg = <0x38000000 0x8000>;
+ interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>,
+ <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ clock-names = "core", "shader", "bus", "reg";
+ assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
+ <&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
+ <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>, <800000000>;
+ power-domains = <&pgc_gpu3d>;
+ };
+
+ gpu2d: gpu@38008000 {
+ compatible = "vivante,gc";
+ reg = <0x38008000 0x8000>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
+ <&clk IMX8MP_CLK_GPU_ROOT>,
+ <&clk IMX8MP_CLK_GPU_AHB>;
+ clock-names = "core", "bus", "reg";
+ assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
+ assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
+ assigned-clock-rates = <800000000>;
+ power-domains = <&pgc_gpu2d>;
+ };
+
gic: interrupt-controller@38800000 {
compatible = "arm,gic-v3";
reg = <0x38800000 0x10000>,
--
2.30.2
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH v3 1/7] soc: imx: gpcv2: add PGC control register indirection
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:34 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 20:34 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:25PM +0100, Lucas Stach wrote:
> The PGC control registers in the shared (not per-PGC) region of the
> GPC address space have different offsets on i.MX8MP to make space for
> additional interrupt control registers.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 32 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 3e59d479d001..01f46b078df3 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -184,9 +184,17 @@
>
> #define GPC_PGC_CTRL_PCR BIT(0)
>
> +struct imx_pgc_regs {
> + u16 map;
> + u16 pup;
> + u16 pdn;
> + u16 hsk;
> +};
> +
> struct imx_pgc_domain {
> struct generic_pm_domain genpd;
> struct regmap *regmap;
> + const struct imx_pgc_regs *regs;
> struct regulator *regulator;
> struct reset_control *reset;
> struct clk_bulk_data *clks;
> @@ -210,6 +218,7 @@ struct imx_pgc_domain_data {
> const struct imx_pgc_domain *domains;
> size_t domains_num;
> const struct regmap_access_table *reg_access_table;
> + const struct imx_pgc_regs *pgc_regs;
> };
>
> static inline struct imx_pgc_domain *
> @@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>
> if (domain->bits.pxx) {
> /* request the domain to power up */
> - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
> + regmap_update_bits(domain->regmap, domain->regs->pup,
> domain->bits.pxx, domain->bits.pxx);
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> */
> ret = regmap_read_poll_timeout(domain->regmap,
> - GPC_PU_PGC_SW_PUP_REQ, reg_val,
> + domain->regs->pup, reg_val,
> !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> if (ret) {
> @@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>
> /* request the ADB400 to power up */
> if (domain->bits.hskreq) {
> - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + regmap_update_bits(domain->regmap, domain->regs->hsk,
> domain->bits.hskreq, domain->bits.hskreq);
>
> /*
> - * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
> + * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
> * (reg_val & domain->bits.hskack), 0,
> * USEC_PER_MSEC);
> * Technically we need the commented code to wait handshake. But that needs
> @@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
>
> /* request the ADB400 to power down */
> if (domain->bits.hskreq) {
> - regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
> + regmap_clear_bits(domain->regmap, domain->regs->hsk,
> domain->bits.hskreq);
>
> - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
> + ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
> reg_val,
> !(reg_val & domain->bits.hskack),
> 0, USEC_PER_MSEC);
> @@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
> }
>
> /* request the domain to power down */
> - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
> + regmap_update_bits(domain->regmap, domain->regs->pdn,
> domain->bits.pxx, domain->bits.pxx);
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> */
> ret = regmap_read_poll_timeout(domain->regmap,
> - GPC_PU_PGC_SW_PDN_REQ, reg_val,
> + domain->regs->pdn, reg_val,
> !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> if (ret) {
> @@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = {
> .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
> };
>
> +static const struct imx_pgc_regs imx7_pgc_regs = {
> + .map = GPC_PGC_CPU_MAPPING,
> + .pup = GPC_PU_PGC_SW_PUP_REQ,
> + .pdn = GPC_PU_PGC_SW_PDN_REQ,
> + .hsk = GPC_PU_PWRHSK,
> +};
> +
> static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
> .domains = imx7_pgc_domains,
> .domains_num = ARRAY_SIZE(imx7_pgc_domains),
> .reg_access_table = &imx7_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8m_pgc_domains[] = {
> @@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
> .domains = imx8m_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
> .reg_access_table = &imx8m_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
> @@ -803,6 +821,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> .domains = imx8mm_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
> .reg_access_table = &imx8mm_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
> @@ -894,6 +913,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
> .domains = imx8mn_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
> .reg_access_table = &imx8mn_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static int imx_pgc_domain_probe(struct platform_device *pdev)
> @@ -926,7 +946,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
> pm_runtime_enable(domain->dev);
>
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, domain->bits.map);
>
> ret = pm_genpd_init(&domain->genpd, NULL, true);
> @@ -952,7 +972,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
> pm_genpd_remove(&domain->genpd);
> out_domain_unmap:
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, 0);
> pm_runtime_disable(domain->dev);
>
> @@ -967,7 +987,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
> pm_genpd_remove(&domain->genpd);
>
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, 0);
>
> pm_runtime_disable(domain->dev);
> @@ -1098,6 +1118,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
>
> domain = pd_pdev->dev.platform_data;
> domain->regmap = regmap;
> + domain->regs = domain_data->pgc_regs;
> domain->genpd.power_on = imx_pgc_power_up;
> domain->genpd.power_off = imx_pgc_power_down;
>
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 1/7] soc: imx: gpcv2: add PGC control register indirection
@ 2022-02-28 20:34 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 20:34 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:25PM +0100, Lucas Stach wrote:
> The PGC control registers in the shared (not per-PGC) region of the
> GPC address space have different offsets on i.MX8MP to make space for
> additional interrupt control registers.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/soc/imx/gpcv2.c | 43 ++++++++++++++++++++++++++++++-----------
> 1 file changed, 32 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 3e59d479d001..01f46b078df3 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -184,9 +184,17 @@
>
> #define GPC_PGC_CTRL_PCR BIT(0)
>
> +struct imx_pgc_regs {
> + u16 map;
> + u16 pup;
> + u16 pdn;
> + u16 hsk;
> +};
> +
> struct imx_pgc_domain {
> struct generic_pm_domain genpd;
> struct regmap *regmap;
> + const struct imx_pgc_regs *regs;
> struct regulator *regulator;
> struct reset_control *reset;
> struct clk_bulk_data *clks;
> @@ -210,6 +218,7 @@ struct imx_pgc_domain_data {
> const struct imx_pgc_domain *domains;
> size_t domains_num;
> const struct regmap_access_table *reg_access_table;
> + const struct imx_pgc_regs *pgc_regs;
> };
>
> static inline struct imx_pgc_domain *
> @@ -249,14 +258,14 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>
> if (domain->bits.pxx) {
> /* request the domain to power up */
> - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PUP_REQ,
> + regmap_update_bits(domain->regmap, domain->regs->pup,
> domain->bits.pxx, domain->bits.pxx);
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> */
> ret = regmap_read_poll_timeout(domain->regmap,
> - GPC_PU_PGC_SW_PUP_REQ, reg_val,
> + domain->regs->pup, reg_val,
> !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> if (ret) {
> @@ -278,11 +287,11 @@ static int imx_pgc_power_up(struct generic_pm_domain *genpd)
>
> /* request the ADB400 to power up */
> if (domain->bits.hskreq) {
> - regmap_update_bits(domain->regmap, GPC_PU_PWRHSK,
> + regmap_update_bits(domain->regmap, domain->regs->hsk,
> domain->bits.hskreq, domain->bits.hskreq);
>
> /*
> - * ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK, reg_val,
> + * ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk, reg_val,
> * (reg_val & domain->bits.hskack), 0,
> * USEC_PER_MSEC);
> * Technically we need the commented code to wait handshake. But that needs
> @@ -329,10 +338,10 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
>
> /* request the ADB400 to power down */
> if (domain->bits.hskreq) {
> - regmap_clear_bits(domain->regmap, GPC_PU_PWRHSK,
> + regmap_clear_bits(domain->regmap, domain->regs->hsk,
> domain->bits.hskreq);
>
> - ret = regmap_read_poll_timeout(domain->regmap, GPC_PU_PWRHSK,
> + ret = regmap_read_poll_timeout(domain->regmap, domain->regs->hsk,
> reg_val,
> !(reg_val & domain->bits.hskack),
> 0, USEC_PER_MSEC);
> @@ -350,14 +359,14 @@ static int imx_pgc_power_down(struct generic_pm_domain *genpd)
> }
>
> /* request the domain to power down */
> - regmap_update_bits(domain->regmap, GPC_PU_PGC_SW_PDN_REQ,
> + regmap_update_bits(domain->regmap, domain->regs->pdn,
> domain->bits.pxx, domain->bits.pxx);
> /*
> * As per "5.5.9.4 Example Code 4" in IMX7DRM.pdf wait
> * for PUP_REQ/PDN_REQ bit to be cleared
> */
> ret = regmap_read_poll_timeout(domain->regmap,
> - GPC_PU_PGC_SW_PDN_REQ, reg_val,
> + domain->regs->pdn, reg_val,
> !(reg_val & domain->bits.pxx),
> 0, USEC_PER_MSEC);
> if (ret) {
> @@ -441,10 +450,18 @@ static const struct regmap_access_table imx7_access_table = {
> .n_yes_ranges = ARRAY_SIZE(imx7_yes_ranges),
> };
>
> +static const struct imx_pgc_regs imx7_pgc_regs = {
> + .map = GPC_PGC_CPU_MAPPING,
> + .pup = GPC_PU_PGC_SW_PUP_REQ,
> + .pdn = GPC_PU_PGC_SW_PDN_REQ,
> + .hsk = GPC_PU_PWRHSK,
> +};
> +
> static const struct imx_pgc_domain_data imx7_pgc_domain_data = {
> .domains = imx7_pgc_domains,
> .domains_num = ARRAY_SIZE(imx7_pgc_domains),
> .reg_access_table = &imx7_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8m_pgc_domains[] = {
> @@ -613,6 +630,7 @@ static const struct imx_pgc_domain_data imx8m_pgc_domain_data = {
> .domains = imx8m_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8m_pgc_domains),
> .reg_access_table = &imx8m_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8mm_pgc_domains[] = {
> @@ -803,6 +821,7 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> .domains = imx8mm_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8mm_pgc_domains),
> .reg_access_table = &imx8mm_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
> @@ -894,6 +913,7 @@ static const struct imx_pgc_domain_data imx8mn_pgc_domain_data = {
> .domains = imx8mn_pgc_domains,
> .domains_num = ARRAY_SIZE(imx8mn_pgc_domains),
> .reg_access_table = &imx8mn_access_table,
> + .pgc_regs = &imx7_pgc_regs,
> };
>
> static int imx_pgc_domain_probe(struct platform_device *pdev)
> @@ -926,7 +946,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
> pm_runtime_enable(domain->dev);
>
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, domain->bits.map);
>
> ret = pm_genpd_init(&domain->genpd, NULL, true);
> @@ -952,7 +972,7 @@ static int imx_pgc_domain_probe(struct platform_device *pdev)
> pm_genpd_remove(&domain->genpd);
> out_domain_unmap:
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, 0);
> pm_runtime_disable(domain->dev);
>
> @@ -967,7 +987,7 @@ static int imx_pgc_domain_remove(struct platform_device *pdev)
> pm_genpd_remove(&domain->genpd);
>
> if (domain->bits.map)
> - regmap_update_bits(domain->regmap, GPC_PGC_CPU_MAPPING,
> + regmap_update_bits(domain->regmap, domain->regs->map,
> domain->bits.map, 0);
>
> pm_runtime_disable(domain->dev);
> @@ -1098,6 +1118,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
>
> domain = pd_pdev->dev.platform_data;
> domain->regmap = regmap;
> + domain->regs = domain_data->pgc_regs;
> domain->genpd.power_on = imx_pgc_power_up;
> domain->genpd.power_off = imx_pgc_power_down;
>
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 2/7] soc: imx: gpcv2: add support for i.MX8MP power domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 20:37 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 20:37 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:26PM +0100, Lucas Stach wrote:
> This adds driver support for all the GPC power domains found on
> the i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 386 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 01f46b078df3..0bc3c00426e9 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -21,10 +21,12 @@
> #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/power/imx8mm-power.h>
> #include <dt-bindings/power/imx8mn-power.h>
> +#include <dt-bindings/power/imx8mp-power.h>
>
> #define GPC_LPCR_A_CORE_BSC 0x000
>
> #define GPC_PGC_CPU_MAPPING 0x0ec
> +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
>
> #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
> #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
> @@ -65,6 +67,29 @@
> #define IMX8MN_OTG1_A53_DOMAIN BIT(4)
> #define IMX8MN_MIPI_A53_DOMAIN BIT(2)
>
> +#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
> +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
> +#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
> +#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
> +#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
> +#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
> +#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
> +#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
> +#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
> +#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
> +#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
> +#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
> +#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
> +#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
> +#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
> +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
> +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
> +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
> +#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
> +
> +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
> +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
> +
> #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
> #define GPC_PU_PGC_SW_PDN_REQ 0x104
>
> @@ -107,8 +132,30 @@
> #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
> #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
>
> +#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
> +#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
> +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
> +#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
> +#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
> +#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
> +#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
> +#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
> +#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
> +#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
> +#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
> +#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
> +#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
> +#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
> +#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
> +#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
> +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
> +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
> +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
> +#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
> +
> #define GPC_M4_PU_PDN_FLG 0x1bc
>
> +#define IMX8MP_GPC_PU_PWRHSK 0x190
> #define GPC_PU_PWRHSK 0x1fc
>
> #define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
> @@ -118,7 +165,6 @@
> #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
> #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
>
> -
> #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
> #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
> #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
> @@ -137,6 +183,21 @@
> #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
> #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
>
> +#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
> +#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
> +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
> +#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
> +#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
> +#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
> +#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
> +#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
> +#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
> +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
> +#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
> +#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
> +#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
> +#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
> +
> /*
> * The PGC offset values in Reference Manual
> * (Rev. 1, 01/2018 and the older ones) GPC chapter's
> @@ -179,6 +240,28 @@
> #define IMX8MN_PGC_GPUMIX 23
> #define IMX8MN_PGC_DISPMIX 26
>
> +#define IMX8MP_PGC_NOC 9
> +#define IMX8MP_PGC_MIPI1 12
> +#define IMX8MP_PGC_PCIE 13
> +#define IMX8MP_PGC_USB1 14
> +#define IMX8MP_PGC_USB2 15
> +#define IMX8MP_PGC_MLMIX 16
> +#define IMX8MP_PGC_AUDIOMIX 17
> +#define IMX8MP_PGC_GPU2D 18
> +#define IMX8MP_PGC_GPUMIX 19
> +#define IMX8MP_PGC_VPUMIX 20
> +#define IMX8MP_PGC_GPU3D 21
> +#define IMX8MP_PGC_MEDIAMIX 22
> +#define IMX8MP_PGC_VPU_G1 23
> +#define IMX8MP_PGC_VPU_G2 24
> +#define IMX8MP_PGC_VPU_VC8000E 25
> +#define IMX8MP_PGC_HDMIMIX 26
> +#define IMX8MP_PGC_HDMI 27
> +#define IMX8MP_PGC_MIPI2 28
> +#define IMX8MP_PGC_HSIOMIX 29
> +#define IMX8MP_PGC_MEDIA_ISP_DWP 30
> +#define IMX8MP_PGC_DDRMIX 31
> +
> #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
> #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
>
> @@ -212,6 +295,9 @@ struct imx_pgc_domain {
> const int voltage;
> const bool keep_clocks;
> struct device *dev;
> +
> + unsigned int pgc_sw_pup_reg;
> + unsigned int pgc_sw_pdn_reg;
> };
>
> struct imx_pgc_domain_data {
> @@ -824,6 +910,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> .pgc_regs = &imx7_pgc_regs,
> };
>
> +static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
> + [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
> + .genpd = {
> + .name = "mipi-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
> + .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MIPI1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
> + .genpd = {
> + .name = "pcie-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
> + .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_PCIE),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
> + .genpd = {
> + .name = "usb-otg1",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
> + .map = IMX8MP_USB1_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
> + .genpd = {
> + .name = "usb-otg2",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
> + .map = IMX8MP_USB2_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MLMIX] = {
> + .genpd = {
> + .name = "mlmix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MLMIX_Pxx_REQ,
> + .map = IMX8MP_MLMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_MLMIX_PWRDNREQN,
> + .hskack = IMX8MP_MLMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MLMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
> + .genpd = {
> + .name = "audiomix",
> + },
> + .bits = {
> + .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
> + .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
> + .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU2D] = {
> + .genpd = {
> + .name = "gpu2d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_2D_Pxx_REQ,
> + .map = IMX8MP_GPU2D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU2D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPUMIX] = {
> + .genpd = {
> + .name = "gpumix",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
> + .map = IMX8MP_GPUMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
> + .hskack = IMX8MP_GPUMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPUMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPUMIX] = {
> + .genpd = {
> + .name = "vpumix",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
> + .map = IMX8MP_VPUMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
> + .hskack = IMX8MP_VPUMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPUMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU3D] = {
> + .genpd = {
> + .name = "gpu3d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_3D_Pxx_REQ,
> + .map = IMX8MP_GPU3D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU3D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
> + .genpd = {
> + .name = "mediamix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
> + .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
> + .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_G1] = {
> + .genpd = {
> + .name = "vpu-g1",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_G1_Pxx_REQ,
> + .map = IMX8MP_VPU_G1_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_G1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_G2] = {
> + .genpd = {
> + .name = "vpu-g2",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_G2_Pxx_REQ,
> + .map = IMX8MP_VPU_G2_A53_DOMAIN
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_G2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
> + .genpd = {
> + .name = "vpu-h1",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
> + .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
> + .genpd = {
> + .name = "hdmimix",
> + },
> + .bits = {
> + .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
> + .map = IMX8MP_HDMIMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
> + .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HDMIMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
> + .genpd = {
> + .name = "hdmi-phy",
> + },
> + .bits = {
> + .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
> + .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HDMI),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
> + .genpd = {
> + .name = "mipi-phy2",
> + },
> + .bits = {
> + .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
> + .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MIPI2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
> + .genpd = {
> + .name = "hsiomix",
> + },
> + .bits = {
> + .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
> + .map = IMX8MP_HSIOMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
> + .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HSIOMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
> + .genpd = {
> + .name = "mediamix-isp-dwp",
> + },
> + .bits = {
> + .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
> + .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
> + },
> +};
> +
> +static const struct regmap_range imx8mp_yes_ranges[] = {
> + regmap_reg_range(GPC_LPCR_A_CORE_BSC,
> + IMX8MP_GPC_PGC_CPU_MAPPING),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
> + GPC_PGC_SR(IMX8MP_PGC_NOC)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
> + GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
> + GPC_PGC_SR(IMX8MP_PGC_PCIE)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
> + GPC_PGC_SR(IMX8MP_PGC_USB1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
> + GPC_PGC_SR(IMX8MP_PGC_USB2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
> + GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
> + GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
> + GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
> + GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
> + GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
> + GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
> + GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
> + GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
> + GPC_PGC_SR(IMX8MP_PGC_HDMI)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
> + GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
> + GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
> + GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
> + GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
> +};
> +
> +static const struct regmap_access_table imx8mp_access_table = {
> + .yes_ranges = imx8mp_yes_ranges,
> + .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
> +};
> +
> +static const struct imx_pgc_regs imx8mp_pgc_regs = {
> + .map = IMX8MP_GPC_PGC_CPU_MAPPING,
> + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
> + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
> + .hsk = IMX8MP_GPC_PU_PWRHSK,
> +};
> +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
> + .domains = imx8mp_pgc_domains,
> + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
> + .reg_access_table = &imx8mp_access_table,
> + .pgc_regs = &imx8mp_pgc_regs,
> +};
> +
> static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
> [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
> .genpd = {
> @@ -1119,6 +1502,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
> domain = pd_pdev->dev.platform_data;
> domain->regmap = regmap;
> domain->regs = domain_data->pgc_regs;
> +
> domain->genpd.power_on = imx_pgc_power_up;
> domain->genpd.power_off = imx_pgc_power_down;
>
> @@ -1140,6 +1524,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
> { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
> { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
> + { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
> { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> { }
> };
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 2/7] soc: imx: gpcv2: add support for i.MX8MP power domains
@ 2022-02-28 20:37 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 20:37 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:26PM +0100, Lucas Stach wrote:
> This adds driver support for all the GPC power domains found on
> the i.MX8MP SoC.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> drivers/soc/imx/gpcv2.c | 387 +++++++++++++++++++++++++++++++++++++++-
> 1 file changed, 386 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/soc/imx/gpcv2.c b/drivers/soc/imx/gpcv2.c
> index 01f46b078df3..0bc3c00426e9 100644
> --- a/drivers/soc/imx/gpcv2.c
> +++ b/drivers/soc/imx/gpcv2.c
> @@ -21,10 +21,12 @@
> #include <dt-bindings/power/imx8mq-power.h>
> #include <dt-bindings/power/imx8mm-power.h>
> #include <dt-bindings/power/imx8mn-power.h>
> +#include <dt-bindings/power/imx8mp-power.h>
>
> #define GPC_LPCR_A_CORE_BSC 0x000
>
> #define GPC_PGC_CPU_MAPPING 0x0ec
> +#define IMX8MP_GPC_PGC_CPU_MAPPING 0x1cc
>
> #define IMX7_USB_HSIC_PHY_A_CORE_DOMAIN BIT(6)
> #define IMX7_USB_OTG2_PHY_A_CORE_DOMAIN BIT(5)
> @@ -65,6 +67,29 @@
> #define IMX8MN_OTG1_A53_DOMAIN BIT(4)
> #define IMX8MN_MIPI_A53_DOMAIN BIT(2)
>
> +#define IMX8MP_MEDIA_ISPDWP_A53_DOMAIN BIT(20)
> +#define IMX8MP_HSIOMIX_A53_DOMAIN BIT(19)
> +#define IMX8MP_MIPI_PHY2_A53_DOMAIN BIT(18)
> +#define IMX8MP_HDMI_PHY_A53_DOMAIN BIT(17)
> +#define IMX8MP_HDMIMIX_A53_DOMAIN BIT(16)
> +#define IMX8MP_VPU_VC8000E_A53_DOMAIN BIT(15)
> +#define IMX8MP_VPU_G2_A53_DOMAIN BIT(14)
> +#define IMX8MP_VPU_G1_A53_DOMAIN BIT(13)
> +#define IMX8MP_MEDIAMIX_A53_DOMAIN BIT(12)
> +#define IMX8MP_GPU3D_A53_DOMAIN BIT(11)
> +#define IMX8MP_VPUMIX_A53_DOMAIN BIT(10)
> +#define IMX8MP_GPUMIX_A53_DOMAIN BIT(9)
> +#define IMX8MP_GPU2D_A53_DOMAIN BIT(8)
> +#define IMX8MP_AUDIOMIX_A53_DOMAIN BIT(7)
> +#define IMX8MP_MLMIX_A53_DOMAIN BIT(6)
> +#define IMX8MP_USB2_PHY_A53_DOMAIN BIT(5)
> +#define IMX8MP_USB1_PHY_A53_DOMAIN BIT(4)
> +#define IMX8MP_PCIE_PHY_A53_DOMAIN BIT(3)
> +#define IMX8MP_MIPI_PHY1_A53_DOMAIN BIT(2)
> +
> +#define IMX8MP_GPC_PU_PGC_SW_PUP_REQ 0x0d8
> +#define IMX8MP_GPC_PU_PGC_SW_PDN_REQ 0x0e4
> +
> #define GPC_PU_PGC_SW_PUP_REQ 0x0f8
> #define GPC_PU_PGC_SW_PDN_REQ 0x104
>
> @@ -107,8 +132,30 @@
> #define IMX8MN_OTG1_SW_Pxx_REQ BIT(2)
> #define IMX8MN_MIPI_SW_Pxx_REQ BIT(0)
>
> +#define IMX8MP_DDRMIX_Pxx_REQ BIT(19)
> +#define IMX8MP_MEDIA_ISP_DWP_Pxx_REQ BIT(18)
> +#define IMX8MP_HSIOMIX_Pxx_REQ BIT(17)
> +#define IMX8MP_MIPI_PHY2_Pxx_REQ BIT(16)
> +#define IMX8MP_HDMI_PHY_Pxx_REQ BIT(15)
> +#define IMX8MP_HDMIMIX_Pxx_REQ BIT(14)
> +#define IMX8MP_VPU_VC8K_Pxx_REQ BIT(13)
> +#define IMX8MP_VPU_G2_Pxx_REQ BIT(12)
> +#define IMX8MP_VPU_G1_Pxx_REQ BIT(11)
> +#define IMX8MP_MEDIMIX_Pxx_REQ BIT(10)
> +#define IMX8MP_GPU_3D_Pxx_REQ BIT(9)
> +#define IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ BIT(8)
> +#define IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ BIT(7)
> +#define IMX8MP_GPU_2D_Pxx_REQ BIT(6)
> +#define IMX8MP_AUDIOMIX_Pxx_REQ BIT(5)
> +#define IMX8MP_MLMIX_Pxx_REQ BIT(4)
> +#define IMX8MP_USB2_PHY_Pxx_REQ BIT(3)
> +#define IMX8MP_USB1_PHY_Pxx_REQ BIT(2)
> +#define IMX8MP_PCIE_PHY_SW_Pxx_REQ BIT(1)
> +#define IMX8MP_MIPI_PHY1_SW_Pxx_REQ BIT(0)
> +
> #define GPC_M4_PU_PDN_FLG 0x1bc
>
> +#define IMX8MP_GPC_PU_PWRHSK 0x190
> #define GPC_PU_PWRHSK 0x1fc
>
> #define IMX8M_GPU_HSK_PWRDNACKN BIT(26)
> @@ -118,7 +165,6 @@
> #define IMX8M_VPU_HSK_PWRDNREQN BIT(5)
> #define IMX8M_DISP_HSK_PWRDNREQN BIT(4)
>
> -
> #define IMX8MM_GPUMIX_HSK_PWRDNACKN BIT(29)
> #define IMX8MM_GPU_HSK_PWRDNACKN (BIT(27) | BIT(28))
> #define IMX8MM_VPUMIX_HSK_PWRDNACKN BIT(26)
> @@ -137,6 +183,21 @@
> #define IMX8MN_DISPMIX_HSK_PWRDNREQN BIT(7)
> #define IMX8MN_HSIO_HSK_PWRDNREQN BIT(5)
>
> +#define IMX8MP_MEDIAMIX_PWRDNACKN BIT(30)
> +#define IMX8MP_HDMIMIX_PWRDNACKN BIT(29)
> +#define IMX8MP_HSIOMIX_PWRDNACKN BIT(28)
> +#define IMX8MP_VPUMIX_PWRDNACKN BIT(26)
> +#define IMX8MP_GPUMIX_PWRDNACKN BIT(25)
> +#define IMX8MP_MLMIX_PWRDNACKN (BIT(23) | BIT(24))
> +#define IMX8MP_AUDIOMIX_PWRDNACKN (BIT(20) | BIT(31))
> +#define IMX8MP_MEDIAMIX_PWRDNREQN BIT(14)
> +#define IMX8MP_HDMIMIX_PWRDNREQN BIT(13)
> +#define IMX8MP_HSIOMIX_PWRDNREQN BIT(12)
> +#define IMX8MP_VPUMIX_PWRDNREQN BIT(10)
> +#define IMX8MP_GPUMIX_PWRDNREQN BIT(9)
> +#define IMX8MP_MLMIX_PWRDNREQN (BIT(7) | BIT(8))
> +#define IMX8MP_AUDIOMIX_PWRDNREQN (BIT(4) | BIT(15))
> +
> /*
> * The PGC offset values in Reference Manual
> * (Rev. 1, 01/2018 and the older ones) GPC chapter's
> @@ -179,6 +240,28 @@
> #define IMX8MN_PGC_GPUMIX 23
> #define IMX8MN_PGC_DISPMIX 26
>
> +#define IMX8MP_PGC_NOC 9
> +#define IMX8MP_PGC_MIPI1 12
> +#define IMX8MP_PGC_PCIE 13
> +#define IMX8MP_PGC_USB1 14
> +#define IMX8MP_PGC_USB2 15
> +#define IMX8MP_PGC_MLMIX 16
> +#define IMX8MP_PGC_AUDIOMIX 17
> +#define IMX8MP_PGC_GPU2D 18
> +#define IMX8MP_PGC_GPUMIX 19
> +#define IMX8MP_PGC_VPUMIX 20
> +#define IMX8MP_PGC_GPU3D 21
> +#define IMX8MP_PGC_MEDIAMIX 22
> +#define IMX8MP_PGC_VPU_G1 23
> +#define IMX8MP_PGC_VPU_G2 24
> +#define IMX8MP_PGC_VPU_VC8000E 25
> +#define IMX8MP_PGC_HDMIMIX 26
> +#define IMX8MP_PGC_HDMI 27
> +#define IMX8MP_PGC_MIPI2 28
> +#define IMX8MP_PGC_HSIOMIX 29
> +#define IMX8MP_PGC_MEDIA_ISP_DWP 30
> +#define IMX8MP_PGC_DDRMIX 31
> +
> #define GPC_PGC_CTRL(n) (0x800 + (n) * 0x40)
> #define GPC_PGC_SR(n) (GPC_PGC_CTRL(n) + 0xc)
>
> @@ -212,6 +295,9 @@ struct imx_pgc_domain {
> const int voltage;
> const bool keep_clocks;
> struct device *dev;
> +
> + unsigned int pgc_sw_pup_reg;
> + unsigned int pgc_sw_pdn_reg;
> };
>
> struct imx_pgc_domain_data {
> @@ -824,6 +910,303 @@ static const struct imx_pgc_domain_data imx8mm_pgc_domain_data = {
> .pgc_regs = &imx7_pgc_regs,
> };
>
> +static const struct imx_pgc_domain imx8mp_pgc_domains[] = {
> + [IMX8MP_POWER_DOMAIN_MIPI_PHY1] = {
> + .genpd = {
> + .name = "mipi-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_MIPI_PHY1_SW_Pxx_REQ,
> + .map = IMX8MP_MIPI_PHY1_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MIPI1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_PCIE_PHY] = {
> + .genpd = {
> + .name = "pcie-phy1",
> + },
> + .bits = {
> + .pxx = IMX8MP_PCIE_PHY_SW_Pxx_REQ,
> + .map = IMX8MP_PCIE_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_PCIE),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB1_PHY] = {
> + .genpd = {
> + .name = "usb-otg1",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB1_PHY_Pxx_REQ,
> + .map = IMX8MP_USB1_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_USB2_PHY] = {
> + .genpd = {
> + .name = "usb-otg2",
> + },
> + .bits = {
> + .pxx = IMX8MP_USB2_PHY_Pxx_REQ,
> + .map = IMX8MP_USB2_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_USB2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MLMIX] = {
> + .genpd = {
> + .name = "mlmix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MLMIX_Pxx_REQ,
> + .map = IMX8MP_MLMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_MLMIX_PWRDNREQN,
> + .hskack = IMX8MP_MLMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MLMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_AUDIOMIX] = {
> + .genpd = {
> + .name = "audiomix",
> + },
> + .bits = {
> + .pxx = IMX8MP_AUDIOMIX_Pxx_REQ,
> + .map = IMX8MP_AUDIOMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_AUDIOMIX_PWRDNREQN,
> + .hskack = IMX8MP_AUDIOMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_AUDIOMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU2D] = {
> + .genpd = {
> + .name = "gpu2d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_2D_Pxx_REQ,
> + .map = IMX8MP_GPU2D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU2D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPUMIX] = {
> + .genpd = {
> + .name = "gpumix",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_SHARE_LOGIC_Pxx_REQ,
> + .map = IMX8MP_GPUMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_GPUMIX_PWRDNREQN,
> + .hskack = IMX8MP_GPUMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPUMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPUMIX] = {
> + .genpd = {
> + .name = "vpumix",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_MIX_SHARE_LOGIC_Pxx_REQ,
> + .map = IMX8MP_VPUMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_VPUMIX_PWRDNREQN,
> + .hskack = IMX8MP_VPUMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPUMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_GPU3D] = {
> + .genpd = {
> + .name = "gpu3d",
> + },
> + .bits = {
> + .pxx = IMX8MP_GPU_3D_Pxx_REQ,
> + .map = IMX8MP_GPU3D_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_GPU3D),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MEDIAMIX] = {
> + .genpd = {
> + .name = "mediamix",
> + },
> + .bits = {
> + .pxx = IMX8MP_MEDIMIX_Pxx_REQ,
> + .map = IMX8MP_MEDIAMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_MEDIAMIX_PWRDNREQN,
> + .hskack = IMX8MP_MEDIAMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MEDIAMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_G1] = {
> + .genpd = {
> + .name = "vpu-g1",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_G1_Pxx_REQ,
> + .map = IMX8MP_VPU_G1_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_G1),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_G2] = {
> + .genpd = {
> + .name = "vpu-g2",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_G2_Pxx_REQ,
> + .map = IMX8MP_VPU_G2_A53_DOMAIN
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_G2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_VPU_VC8000E] = {
> + .genpd = {
> + .name = "vpu-h1",
> + },
> + .bits = {
> + .pxx = IMX8MP_VPU_VC8K_Pxx_REQ,
> + .map = IMX8MP_VPU_VC8000E_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_VPU_VC8000E),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HDMIMIX] = {
> + .genpd = {
> + .name = "hdmimix",
> + },
> + .bits = {
> + .pxx = IMX8MP_HDMIMIX_Pxx_REQ,
> + .map = IMX8MP_HDMIMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_HDMIMIX_PWRDNREQN,
> + .hskack = IMX8MP_HDMIMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HDMIMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HDMI_PHY] = {
> + .genpd = {
> + .name = "hdmi-phy",
> + },
> + .bits = {
> + .pxx = IMX8MP_HDMI_PHY_Pxx_REQ,
> + .map = IMX8MP_HDMI_PHY_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HDMI),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MIPI_PHY2] = {
> + .genpd = {
> + .name = "mipi-phy2",
> + },
> + .bits = {
> + .pxx = IMX8MP_MIPI_PHY2_Pxx_REQ,
> + .map = IMX8MP_MIPI_PHY2_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MIPI2),
> + },
> +
> + [IMX8MP_POWER_DOMAIN_HSIOMIX] = {
> + .genpd = {
> + .name = "hsiomix",
> + },
> + .bits = {
> + .pxx = IMX8MP_HSIOMIX_Pxx_REQ,
> + .map = IMX8MP_HSIOMIX_A53_DOMAIN,
> + .hskreq = IMX8MP_HSIOMIX_PWRDNREQN,
> + .hskack = IMX8MP_HSIOMIX_PWRDNACKN,
> + },
> + .pgc = BIT(IMX8MP_PGC_HSIOMIX),
> + .keep_clocks = true,
> + },
> +
> + [IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP] = {
> + .genpd = {
> + .name = "mediamix-isp-dwp",
> + },
> + .bits = {
> + .pxx = IMX8MP_MEDIA_ISP_DWP_Pxx_REQ,
> + .map = IMX8MP_MEDIA_ISPDWP_A53_DOMAIN,
> + },
> + .pgc = BIT(IMX8MP_PGC_MEDIA_ISP_DWP),
> + },
> +};
> +
> +static const struct regmap_range imx8mp_yes_ranges[] = {
> + regmap_reg_range(GPC_LPCR_A_CORE_BSC,
> + IMX8MP_GPC_PGC_CPU_MAPPING),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_NOC),
> + GPC_PGC_SR(IMX8MP_PGC_NOC)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI1),
> + GPC_PGC_SR(IMX8MP_PGC_MIPI1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_PCIE),
> + GPC_PGC_SR(IMX8MP_PGC_PCIE)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB1),
> + GPC_PGC_SR(IMX8MP_PGC_USB1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_USB2),
> + GPC_PGC_SR(IMX8MP_PGC_USB2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MLMIX),
> + GPC_PGC_SR(IMX8MP_PGC_MLMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_AUDIOMIX),
> + GPC_PGC_SR(IMX8MP_PGC_AUDIOMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU2D),
> + GPC_PGC_SR(IMX8MP_PGC_GPU2D)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPUMIX),
> + GPC_PGC_SR(IMX8MP_PGC_GPUMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPUMIX),
> + GPC_PGC_SR(IMX8MP_PGC_VPUMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_GPU3D),
> + GPC_PGC_SR(IMX8MP_PGC_GPU3D)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIAMIX),
> + GPC_PGC_SR(IMX8MP_PGC_MEDIAMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G1),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_G1)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_G2),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_G2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_VPU_VC8000E),
> + GPC_PGC_SR(IMX8MP_PGC_VPU_VC8000E)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMIMIX),
> + GPC_PGC_SR(IMX8MP_PGC_HDMIMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HDMI),
> + GPC_PGC_SR(IMX8MP_PGC_HDMI)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MIPI2),
> + GPC_PGC_SR(IMX8MP_PGC_MIPI2)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_HSIOMIX),
> + GPC_PGC_SR(IMX8MP_PGC_HSIOMIX)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_MEDIA_ISP_DWP),
> + GPC_PGC_SR(IMX8MP_PGC_MEDIA_ISP_DWP)),
> + regmap_reg_range(GPC_PGC_CTRL(IMX8MP_PGC_DDRMIX),
> + GPC_PGC_SR(IMX8MP_PGC_DDRMIX)),
> +};
> +
> +static const struct regmap_access_table imx8mp_access_table = {
> + .yes_ranges = imx8mp_yes_ranges,
> + .n_yes_ranges = ARRAY_SIZE(imx8mp_yes_ranges),
> +};
> +
> +static const struct imx_pgc_regs imx8mp_pgc_regs = {
> + .map = IMX8MP_GPC_PGC_CPU_MAPPING,
> + .pup = IMX8MP_GPC_PU_PGC_SW_PUP_REQ,
> + .pdn = IMX8MP_GPC_PU_PGC_SW_PDN_REQ,
> + .hsk = IMX8MP_GPC_PU_PWRHSK,
> +};
> +static const struct imx_pgc_domain_data imx8mp_pgc_domain_data = {
> + .domains = imx8mp_pgc_domains,
> + .domains_num = ARRAY_SIZE(imx8mp_pgc_domains),
> + .reg_access_table = &imx8mp_access_table,
> + .pgc_regs = &imx8mp_pgc_regs,
> +};
> +
> static const struct imx_pgc_domain imx8mn_pgc_domains[] = {
> [IMX8MN_POWER_DOMAIN_HSIOMIX] = {
> .genpd = {
> @@ -1119,6 +1502,7 @@ static int imx_gpcv2_probe(struct platform_device *pdev)
> domain = pd_pdev->dev.platform_data;
> domain->regmap = regmap;
> domain->regs = domain_data->pgc_regs;
> +
> domain->genpd.power_on = imx_pgc_power_up;
> domain->genpd.power_off = imx_pgc_power_down;
>
> @@ -1140,6 +1524,7 @@ static const struct of_device_id imx_gpcv2_dt_ids[] = {
> { .compatible = "fsl,imx7d-gpc", .data = &imx7_pgc_domain_data, },
> { .compatible = "fsl,imx8mm-gpc", .data = &imx8mm_pgc_domain_data, },
> { .compatible = "fsl,imx8mn-gpc", .data = &imx8mn_pgc_domain_data, },
> + { .compatible = "fsl,imx8mp-gpc", .data = &imx8mp_pgc_domain_data, },
> { .compatible = "fsl,imx8mq-gpc", .data = &imx8m_pgc_domain_data, },
> { }
> };
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
2022-02-28 20:17 ` Lucas Stach
@ 2022-02-28 21:10 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 21:10 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> Hi all,
>
> third and hopefully last revision of this patchset. The dt-binding
> patches are dropped, as Shawn already picked them up. I fixed up all
> the review comments received by Laurent and Marek.
For patches 1/7 to 3/7 and 5/7 to 7/7,
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Lucas Stach (7):
> soc: imx: gpcv2: add PGC control register indirection
> soc: imx: gpcv2: add support for i.MX8MP power domains
> soc: imx: add i.MX8MP HSIO blk-ctrl
> dt-bindings: usb: dwc3-imx8mp: add power domain property
> arm64: dts: imx8mp: add HSIO power-domains
> arm64: dts: imx8mp: add GPU power domains
> arm64: dts: imx8mp: add GPU nodes
>
> .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> drivers/soc/imx/Makefile | 1 +
> drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> 5 files changed, 994 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
@ 2022-02-28 21:10 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-02-28 21:10 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> Hi all,
>
> third and hopefully last revision of this patchset. The dt-binding
> patches are dropped, as Shawn already picked them up. I fixed up all
> the review comments received by Laurent and Marek.
For patches 1/7 to 3/7 and 5/7 to 7/7,
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Lucas Stach (7):
> soc: imx: gpcv2: add PGC control register indirection
> soc: imx: gpcv2: add support for i.MX8MP power domains
> soc: imx: add i.MX8MP HSIO blk-ctrl
> dt-bindings: usb: dwc3-imx8mp: add power domain property
> arm64: dts: imx8mp: add HSIO power-domains
> arm64: dts: imx8mp: add GPU power domains
> arm64: dts: imx8mp: add GPU nodes
>
> .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> drivers/soc/imx/Makefile | 1 +
> drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> 5 files changed, 994 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-03-01 7:13 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-01 7:13 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> This adds the GPC and HSIO blk-ctrl nodes providing power control for
> the high-speed (USB and PCIe) IOs.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 6b840c05dd77..69e533add539 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/power/imx8mp-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mp-gpc";
> + reg = <0x303a0000 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_pcie_phy: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> + };
> +
> + pgc_usb1_phy: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> + };
> +
> + pgc_usb2_phy: power-domain@3 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> + };
> +
> + pgc_hsiomix: power-domains@17 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_HSIO_ROOT>;
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> };
> };
>
> + aips4 {
I think this should be
aips4: bus@32c00000 {
to match the other buses. Apart from that, the patch looks good, my Rb
tag still applies.
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x32c00000 0x400000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + hsio_blk_ctrl: blk-ctrl@32f10000 {
> + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> + reg = <0x32f10000 0x24>;
> + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "usb", "pcie";
> + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> + power-domain-names = "bus", "usb", "usb-phy1",
> + "usb-phy2", "pcie", "pcie-phy";
> + #power-domain-cells = <1>;
> + };
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
> @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> #phy-cells = <0>;
> status = "disabled";
> };
> @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref", "suspend";
> - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates = <500000000>;
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy0>, <&usb3_phy0>;
> phy-names = "usb2-phy", "usb3-phy";
> @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> #phy-cells = <0>;
> };
>
> @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref", "suspend";
> - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates = <500000000>;
> interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy1>, <&usb3_phy1>;
> phy-names = "usb2-phy", "usb3-phy";
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-01 7:13 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-01 7:13 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Lucas,
Thank you for the patch.
On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> This adds the GPC and HSIO blk-ctrl nodes providing power control for
> the high-speed (USB and PCIe) IOs.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index 6b840c05dd77..69e533add539 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/power/imx8mp-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mp-gpc";
> + reg = <0x303a0000 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_pcie_phy: power-domain@1 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> + };
> +
> + pgc_usb1_phy: power-domain@2 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> + };
> +
> + pgc_usb2_phy: power-domain@3 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> + };
> +
> + pgc_hsiomix: power-domains@17 {
> + #power-domain-cells = <0>;
> + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> + <&clk IMX8MP_CLK_HSIO_ROOT>;
> + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-clock-rates = <500000000>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> };
> };
>
> + aips4 {
I think this should be
aips4: bus@32c00000 {
to match the other buses. Apart from that, the patch looks good, my Rb
tag still applies.
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x32c00000 0x400000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + hsio_blk_ctrl: blk-ctrl@32f10000 {
> + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> + reg = <0x32f10000 0x24>;
> + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> + <&clk IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "usb", "pcie";
> + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> + power-domain-names = "bus", "usb", "usb-phy1",
> + "usb-phy2", "pcie", "pcie-phy";
> + #power-domain-cells = <1>;
> + };
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
> @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> #phy-cells = <0>;
> status = "disabled";
> };
> @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref", "suspend";
> - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates = <500000000>;
> interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy0>, <&usb3_phy0>;
> phy-names = "usb2-phy", "usb3-phy";
> @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> #phy-cells = <0>;
> };
>
> @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> <&clk IMX8MP_CLK_USB_CORE_REF>,
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref", "suspend";
> - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates = <500000000>;
> interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy1>, <&usb3_phy1>;
> phy-names = "usb2-phy", "usb3-phy";
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-01 7:13 ` Laurent Pinchart
@ 2022-03-01 9:09 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-03-01 9:09 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent Pinchart:
> Hi Lucas,
>
> Thank you for the patch.
>
> On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > This adds the GPC and HSIO blk-ctrl nodes providing power control for
> > the high-speed (USB and PCIe) IOs.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> > 1 file changed, 65 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 6b840c05dd77..69e533add539 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include <dt-bindings/clock/imx8mp-clock.h>
> > +#include <dt-bindings/power/imx8mp-power.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/input/input.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > #reset-cells = <1>;
> > };
> > +
> > + gpc: gpc@303a0000 {
> > + compatible = "fsl,imx8mp-gpc";
> > + reg = <0x303a0000 0x1000>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > +
> > + pgc {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + pgc_pcie_phy: power-domain@1 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > + };
> > +
> > + pgc_usb1_phy: power-domain@2 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > + };
> > +
> > + pgc_usb2_phy: power-domain@3 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > + };
> > +
> > + pgc_hsiomix: power-domains@17 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > + <&clk IMX8MP_CLK_HSIO_ROOT>;
> > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + };
> > + };
> > + };
> > };
> >
> > aips2: bus@30400000 {
> > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > };
> > };
> >
> > + aips4 {
>
> I think this should be
>
> aips4: bus@32c00000 {
>
> to match the other buses. Apart from that, the patch looks good, my Rb
> tag still applies.
Urgh, apparently one shouldn't do those reworks too late in the
evening. :/
Shawn, would you be willing to fix this up while applying, or should I
resend the series?
Regards,
Lucas
>
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + reg = <0x32c00000 0x400000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> > + reg = <0x32f10000 0x24>;
> > + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> > + <&clk IMX8MP_CLK_PCIE_ROOT>;
> > + clock-names = "usb", "pcie";
> > + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> > + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> > + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> > + power-domain-names = "bus", "usb", "usb-phy1",
> > + "usb-phy2", "pcie", "pcie-phy";
> > + #power-domain-cells = <1>;
> > + };
> > + };
> > +
> > gic: interrupt-controller@38800000 {
> > compatible = "arm,gic-v3";
> > reg = <0x38800000 0x10000>,
> > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > clock-names = "phy";
> > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > #phy-cells = <0>;
> > status = "disabled";
> > };
> > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "hsio", "suspend";
> > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> > @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "bus_early", "ref", "suspend";
> > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > - assigned-clock-rates = <500000000>;
> > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > phys = <&usb3_phy0>, <&usb3_phy0>;
> > phy-names = "usb2-phy", "usb3-phy";
> > @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> > clock-names = "phy";
> > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > #phy-cells = <0>;
> > };
> >
> > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "hsio", "suspend";
> > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> > @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "bus_early", "ref", "suspend";
> > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > - assigned-clock-rates = <500000000>;
> > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > phys = <&usb3_phy1>, <&usb3_phy1>;
> > phy-names = "usb2-phy", "usb3-phy";
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-01 9:09 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-03-01 9:09 UTC (permalink / raw)
To: Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent Pinchart:
> Hi Lucas,
>
> Thank you for the patch.
>
> On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > This adds the GPC and HSIO blk-ctrl nodes providing power control for
> > the high-speed (USB and PCIe) IOs.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > ---
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> > 1 file changed, 65 insertions(+), 6 deletions(-)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > index 6b840c05dd77..69e533add539 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > @@ -4,6 +4,7 @@
> > */
> >
> > #include <dt-bindings/clock/imx8mp-clock.h>
> > +#include <dt-bindings/power/imx8mp-power.h>
> > #include <dt-bindings/gpio/gpio.h>
> > #include <dt-bindings/input/input.h>
> > #include <dt-bindings/interrupt-controller/arm-gic.h>
> > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > #reset-cells = <1>;
> > };
> > +
> > + gpc: gpc@303a0000 {
> > + compatible = "fsl,imx8mp-gpc";
> > + reg = <0x303a0000 0x1000>;
> > + interrupt-parent = <&gic>;
> > + interrupt-controller;
> > + #interrupt-cells = <3>;
> > +
> > + pgc {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + pgc_pcie_phy: power-domain@1 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > + };
> > +
> > + pgc_usb1_phy: power-domain@2 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > + };
> > +
> > + pgc_usb2_phy: power-domain@3 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > + };
> > +
> > + pgc_hsiomix: power-domains@17 {
> > + #power-domain-cells = <0>;
> > + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > + <&clk IMX8MP_CLK_HSIO_ROOT>;
> > + assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > + assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > + assigned-clock-rates = <500000000>;
> > + };
> > + };
> > + };
> > };
> >
> > aips2: bus@30400000 {
> > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > };
> > };
> >
> > + aips4 {
>
> I think this should be
>
> aips4: bus@32c00000 {
>
> to match the other buses. Apart from that, the patch looks good, my Rb
> tag still applies.
Urgh, apparently one shouldn't do those reworks too late in the
evening. :/
Shawn, would you be willing to fix this up while applying, or should I
resend the series?
Regards,
Lucas
>
> > + compatible = "fsl,aips-bus", "simple-bus";
> > + reg = <0x32c00000 0x400000>;
> > + #address-cells = <1>;
> > + #size-cells = <1>;
> > + ranges;
> > +
> > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> > + reg = <0x32f10000 0x24>;
> > + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> > + <&clk IMX8MP_CLK_PCIE_ROOT>;
> > + clock-names = "usb", "pcie";
> > + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> > + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> > + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> > + power-domain-names = "bus", "usb", "usb-phy1",
> > + "usb-phy2", "pcie", "pcie-phy";
> > + #power-domain-cells = <1>;
> > + };
> > + };
> > +
> > gic: interrupt-controller@38800000 {
> > compatible = "arm,gic-v3";
> > reg = <0x38800000 0x10000>,
> > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > clock-names = "phy";
> > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > #phy-cells = <0>;
> > status = "disabled";
> > };
> > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "hsio", "suspend";
> > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> > @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "bus_early", "ref", "suspend";
> > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > - assigned-clock-rates = <500000000>;
> > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > phys = <&usb3_phy0>, <&usb3_phy0>;
> > phy-names = "usb2-phy", "usb3-phy";
> > @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> > clock-names = "phy";
> > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > #phy-cells = <0>;
> > };
> >
> > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "hsio", "suspend";
> > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > #address-cells = <1>;
> > #size-cells = <1>;
> > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> > @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > <&clk IMX8MP_CLK_USB_ROOT>;
> > clock-names = "bus_early", "ref", "suspend";
> > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > - assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> > - assigned-clock-rates = <500000000>;
> > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > phys = <&usb3_phy1>, <&usb3_phy1>;
> > phy-names = "usb2-phy", "usb3-phy";
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-01 9:09 ` Lucas Stach
@ 2022-03-02 8:47 ` Hongxing Zhu
-1 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-02 8:47 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年3月1日 17:09
> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent Pinchart:
> > Hi Lucas,
> >
> > Thank you for the patch.
> >
> > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > This adds the GPC and HSIO blk-ctrl nodes providing power control
> > > for the high-speed (USB and PCIe) IOs.
> > >
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Hi Lucas:
Thank you for the patch.
Based on this V3 serial patch-set. I'm trying to bring up PCIe on i.MX8MP EVK.
But I encounter system hang when access the controller's register.
Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
It seems that the pd of PCIe controller is not up properly.
More investigation is still on-going.
BTW, the access of PHY register is successful.
Best Regards
Richard Zhu
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > +++++++++++++++++++++--
> > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index 6b840c05dd77..69e533add539 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -4,6 +4,7 @@
> > > */
> > >
> > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > +#include <dt-bindings/power/imx8mp-power.h>
> > > #include <dt-bindings/gpio/gpio.h>
> > > #include <dt-bindings/input/input.h> #include
> > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > > #reset-cells = <1>;
> > > };
> > > +
> > > + gpc: gpc@303a0000 {
> > > + compatible = "fsl,imx8mp-gpc";
> > > + reg = <0x303a0000 0x1000>;
> > > + interrupt-parent = <&gic>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > +
> > > + pgc {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + pgc_pcie_phy: power-domain@1 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > + };
> > > +
> > > + pgc_usb1_phy: power-domain@2 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > + };
> > > +
> > > + pgc_usb2_phy: power-domain@3 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > + };
> > > +
> > > + pgc_hsiomix: power-domains@17 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > > + <&clk IMX8MP_CLK_HSIO_ROOT>;
> > > + assigned-clocks = <&clk
> IMX8MP_CLK_HSIO_AXI>;
> > > + assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > + assigned-clock-rates = <500000000>;
> > > + };
> > > + };
> > > + };
> > > };
> > >
> > > aips2: bus@30400000 {
> > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > };
> > > };
> > >
> > > + aips4 {
> >
> > I think this should be
> >
> > aips4: bus@32c00000 {
> >
> > to match the other buses. Apart from that, the patch looks good, my Rb
> > tag still applies.
>
> Urgh, apparently one shouldn't do those reworks too late in the evening. :/
>
> Shawn, would you be willing to fix this up while applying, or should I resend
> the series?
>
> Regards,
> Lucas
>
> >
> > > + compatible = "fsl,aips-bus", "simple-bus";
> > > + reg = <0x32c00000 0x400000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > +
> > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> > > + reg = <0x32f10000 0x24>;
> > > + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> > > + <&clk IMX8MP_CLK_PCIE_ROOT>;
> > > + clock-names = "usb", "pcie";
> > > + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> > > + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> > > + power-domain-names = "bus", "usb", "usb-phy1",
> > > + "usb-phy2", "pcie", "pcie-phy";
> > > + #power-domain-cells = <1>;
> > > + };
> > > + };
> > > +
> > > gic: interrupt-controller@38800000 {
> > > compatible = "arm,gic-v3";
> > > reg = <0x38800000 0x10000>,
> > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > clock-names = "phy";
> > > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > + power-domains = <&hsio_blk_ctrl
> IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > #phy-cells = <0>;
> > > status = "disabled";
> > > };
> > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "hsio", "suspend";
> > > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -939,9
> > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "bus_early", "ref", "suspend";
> > > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > > - assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > - assigned-clock-rates = <500000000>;
> > > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > > phys = <&usb3_phy0>, <&usb3_phy0>;
> > > phy-names = "usb2-phy", "usb3-phy"; @@ -957,6
> +1017,7 @@
> > > usb3_phy1: usb-phy@382f0040 {
> > > clock-names = "phy";
> > > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > + power-domains = <&hsio_blk_ctrl
> IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > #phy-cells = <0>;
> > > };
> > >
> > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "hsio", "suspend";
> > > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -980,9
> > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "bus_early", "ref", "suspend";
> > > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > > - assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > - assigned-clock-rates = <500000000>;
> > > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > > phys = <&usb3_phy1>, <&usb3_phy1>;
> > > phy-names = "usb2-phy", "usb3-phy";
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-02 8:47 ` Hongxing Zhu
0 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-02 8:47 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年3月1日 17:09
> To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent Pinchart:
> > Hi Lucas,
> >
> > Thank you for the patch.
> >
> > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > This adds the GPC and HSIO blk-ctrl nodes providing power control
> > > for the high-speed (USB and PCIe) IOs.
> > >
> > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Hi Lucas:
Thank you for the patch.
Based on this V3 serial patch-set. I'm trying to bring up PCIe on i.MX8MP EVK.
But I encounter system hang when access the controller's register.
Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
It seems that the pd of PCIe controller is not up properly.
More investigation is still on-going.
BTW, the access of PHY register is successful.
Best Regards
Richard Zhu
> > > ---
> > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > +++++++++++++++++++++--
> > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > >
> > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > index 6b840c05dd77..69e533add539 100644
> > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > @@ -4,6 +4,7 @@
> > > */
> > >
> > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > +#include <dt-bindings/power/imx8mp-power.h>
> > > #include <dt-bindings/gpio/gpio.h>
> > > #include <dt-bindings/input/input.h> #include
> > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
> > > #reset-cells = <1>;
> > > };
> > > +
> > > + gpc: gpc@303a0000 {
> > > + compatible = "fsl,imx8mp-gpc";
> > > + reg = <0x303a0000 0x1000>;
> > > + interrupt-parent = <&gic>;
> > > + interrupt-controller;
> > > + #interrupt-cells = <3>;
> > > +
> > > + pgc {
> > > + #address-cells = <1>;
> > > + #size-cells = <0>;
> > > +
> > > + pgc_pcie_phy: power-domain@1 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > + };
> > > +
> > > + pgc_usb1_phy: power-domain@2 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > + };
> > > +
> > > + pgc_usb2_phy: power-domain@3 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > + };
> > > +
> > > + pgc_hsiomix: power-domains@17 {
> > > + #power-domain-cells = <0>;
> > > + reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > + clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
> > > + <&clk IMX8MP_CLK_HSIO_ROOT>;
> > > + assigned-clocks = <&clk
> IMX8MP_CLK_HSIO_AXI>;
> > > + assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > + assigned-clock-rates = <500000000>;
> > > + };
> > > + };
> > > + };
> > > };
> > >
> > > aips2: bus@30400000 {
> > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > };
> > > };
> > >
> > > + aips4 {
> >
> > I think this should be
> >
> > aips4: bus@32c00000 {
> >
> > to match the other buses. Apart from that, the patch looks good, my Rb
> > tag still applies.
>
> Urgh, apparently one shouldn't do those reworks too late in the evening. :/
>
> Shawn, would you be willing to fix this up while applying, or should I resend
> the series?
>
> Regards,
> Lucas
>
> >
> > > + compatible = "fsl,aips-bus", "simple-bus";
> > > + reg = <0x32c00000 0x400000>;
> > > + #address-cells = <1>;
> > > + #size-cells = <1>;
> > > + ranges;
> > > +
> > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > + compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
> > > + reg = <0x32f10000 0x24>;
> > > + clocks = <&clk IMX8MP_CLK_USB_ROOT>,
> > > + <&clk IMX8MP_CLK_PCIE_ROOT>;
> > > + clock-names = "usb", "pcie";
> > > + power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > + <&pgc_usb1_phy>, <&pgc_usb2_phy>,
> > > + <&pgc_hsiomix>, <&pgc_pcie_phy>;
> > > + power-domain-names = "bus", "usb", "usb-phy1",
> > > + "usb-phy2", "pcie", "pcie-phy";
> > > + #power-domain-cells = <1>;
> > > + };
> > > + };
> > > +
> > > gic: interrupt-controller@38800000 {
> > > compatible = "arm,gic-v3";
> > > reg = <0x38800000 0x10000>,
> > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > clock-names = "phy";
> > > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > + power-domains = <&hsio_blk_ctrl
> IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > #phy-cells = <0>;
> > > status = "disabled";
> > > };
> > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "hsio", "suspend";
> > > interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
> > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -939,9
> > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "bus_early", "ref", "suspend";
> > > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > > - assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > - assigned-clock-rates = <500000000>;
> > > interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> > > phys = <&usb3_phy0>, <&usb3_phy0>;
> > > phy-names = "usb2-phy", "usb3-phy"; @@ -957,6
> +1017,7 @@
> > > usb3_phy1: usb-phy@382f0040 {
> > > clock-names = "phy";
> > > assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
> > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > + power-domains = <&hsio_blk_ctrl
> IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > #phy-cells = <0>;
> > > };
> > >
> > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "hsio", "suspend";
> > > interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
> > > + power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
> > > #address-cells = <1>;
> > > #size-cells = <1>;
> > > dma-ranges = <0x40000000 0x40000000 0xc0000000>;
> @@ -980,9
> > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > <&clk IMX8MP_CLK_USB_CORE_REF>,
> > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > clock-names = "bus_early", "ref", "suspend";
> > > - assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> > > - assigned-clock-parents = <&clk
> IMX8MP_SYS_PLL2_500M>;
> > > - assigned-clock-rates = <500000000>;
> > > interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> > > phys = <&usb3_phy1>, <&usb3_phy1>;
> > > phy-names = "usb2-phy", "usb3-phy";
> >
>
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^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-02 8:47 ` Hongxing Zhu
@ 2022-03-02 9:18 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-03-02 9:18 UTC (permalink / raw)
To: Hongxing Zhu, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Richard,
Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年3月1日 17:09
> > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > <robh+dt@kernel.org>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> > <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > patchwork-lst@pengutronix.de
> > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > domains
> >
> > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > Pinchart:
> > > Hi Lucas,
> > >
> > > Thank you for the patch.
> > >
> > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > control
> > > > for the high-speed (USB and PCIe) IOs.
> > > >
> > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > Reviewed-by: Laurent Pinchart
> > > > <laurent.pinchart@ideasonboard.com>
> Hi Lucas:
> Thank you for the patch.
> Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> i.MX8MP EVK.
> But I encounter system hang when access the controller's register.
> Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> It seems that the pd of PCIe controller is not up properly.
> More investigation is still on-going.
Just to check the obvious things: you've put the controller into the
IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY,
right?
If the PHY access works then the power-domains should be powered up
properly, as the PHY domain is nested inside the HSIO domain where the
controller is located according to my information. So the most likely
reason is still a clock path that isn't fully turned on.
Regards,
Lucas
> BTW, the access of PHY register is successful.
>
> Best Regards
> Richard Zhu
>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > +++++++++++++++++++++--
> > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > index 6b840c05dd77..69e533add539 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > @@ -4,6 +4,7 @@
> > > > */
> > > >
> > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > #include <dt-bindings/gpio/gpio.h>
> > > > #include <dt-bindings/input/input.h> #include
> > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > interrupts = <GIC_SPI 89
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > #reset-cells = <1>;
> > > > };
> > > > +
> > > > + gpc: gpc@303a0000 {
> > > > + compatible = "fsl,imx8mp-gpc";
> > > > + reg = <0x303a0000 0x1000>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <3>;
> > > > +
> > > > + pgc {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + pgc_pcie_phy: power-
> > > > domain@1 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > + };
> > > > +
> > > > + pgc_usb1_phy: power-
> > > > domain@2 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > + };
> > > > +
> > > > + pgc_usb2_phy: power-
> > > > domain@3 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > + };
> > > > +
> > > > + pgc_hsiomix:
> > > > power-domains@17 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > + clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>,
> > > > + <&clk
> > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > + assigned-
> > > > clocks = <&clk
> > IMX8MP_CLK_HSIO_AXI>;
> > > > + assigned-
> > > > clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > + assigned-
> > > > clock-rates = <500000000>;
> > > > + };
> > > > + };
> > > > + };
> > > > };
> > > >
> > > > aips2: bus@30400000 {
> > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > };
> > > > };
> > > >
> > > > + aips4 {
> > >
> > > I think this should be
> > >
> > > aips4: bus@32c00000 {
> > >
> > > to match the other buses. Apart from that, the patch looks good,
> > > my Rb
> > > tag still applies.
> >
> > Urgh, apparently one shouldn't do those reworks too late in the
> > evening. :/
> >
> > Shawn, would you be willing to fix this up while applying, or
> > should I resend
> > the series?
> >
> > Regards,
> > Lucas
> >
> > >
> > > > + compatible = "fsl,aips-bus", "simple-
> > > > bus";
> > > > + reg = <0x32c00000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > + compatible = "fsl,imx8mp-hsio-
> > > > blk-ctrl", "syscon";
> > > > + reg = <0x32f10000 0x24>;
> > > > + clocks = <&clk
> > > > IMX8MP_CLK_USB_ROOT>,
> > > > + <&clk
> > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > + clock-names = "usb", "pcie";
> > > > + power-domains =
> > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > + <&pgc_usb1_phy
> > > > >, <&pgc_usb2_phy>,
> > > > + <&pgc_hsiomix>
> > > > , <&pgc_pcie_phy>;
> > > > + power-domain-names = "bus",
> > > > "usb", "usb-phy1",
> > > > + "usb-
> > > > phy2", "pcie", "pcie-phy";
> > > > + #power-domain-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > gic: interrupt-controller@38800000 {
> > > > compatible = "arm,gic-v3";
> > > > reg = <0x38800000 0x10000>,
> > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > clock-names = "phy";
> > > > assigned-clocks = <&clk
> > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > assigned-clock-parents = <&clk
> > > > IMX8MP_CLK_24M>;
> > > > + power-domains = <&hsio_blk_ctrl
> > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > #phy-cells = <0>;
> > > > status = "disabled";
> > > > };
> > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "hsio", "suspend";
> > > > interrupts = <GIC_SPI 148
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > > dma-ranges = <0x40000000 0x40000000
> > > > 0xc0000000>;
> > @@ -939,9
> > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > <&clk
> > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > <&clk
> > > > IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "bus_early",
> > > > "ref", "suspend";
> > > > - assigned-clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > - assigned-clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > - assigned-clock-rates =
> > > > <500000000>;
> > > > interrupts = <GIC_SPI 40
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > phys = <&usb3_phy0>,
> > > > <&usb3_phy0>;
> > > > phy-names = "usb2-phy", "usb3-
> > > > phy"; @@ -957,6
> > +1017,7 @@
> > > > usb3_phy1: usb-phy@382f0040 {
> > > > clock-names = "phy";
> > > > assigned-clocks = <&clk
> > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > assigned-clock-parents = <&clk
> > > > IMX8MP_CLK_24M>;
> > > > + power-domains = <&hsio_blk_ctrl
> > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > #phy-cells = <0>;
> > > > };
> > > >
> > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "hsio", "suspend";
> > > > interrupts = <GIC_SPI 149
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > > dma-ranges = <0x40000000 0x40000000
> > > > 0xc0000000>;
> > @@ -980,9
> > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > <&clk
> > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > <&clk
> > > > IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "bus_early",
> > > > "ref", "suspend";
> > > > - assigned-clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > - assigned-clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > - assigned-clock-rates =
> > > > <500000000>;
> > > > interrupts = <GIC_SPI 41
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > phys = <&usb3_phy1>,
> > > > <&usb3_phy1>;
> > > > phy-names = "usb2-phy", "usb3-
> > > > phy";
> > >
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-02 9:18 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-03-02 9:18 UTC (permalink / raw)
To: Hongxing Zhu, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
Hi Richard,
Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年3月1日 17:09
> > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > <robh+dt@kernel.org>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> > <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > patchwork-lst@pengutronix.de
> > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > domains
> >
> > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > Pinchart:
> > > Hi Lucas,
> > >
> > > Thank you for the patch.
> > >
> > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > control
> > > > for the high-speed (USB and PCIe) IOs.
> > > >
> > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > Reviewed-by: Laurent Pinchart
> > > > <laurent.pinchart@ideasonboard.com>
> Hi Lucas:
> Thank you for the patch.
> Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> i.MX8MP EVK.
> But I encounter system hang when access the controller's register.
> Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> It seems that the pd of PCIe controller is not up properly.
> More investigation is still on-going.
Just to check the obvious things: you've put the controller into the
IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY,
right?
If the PHY access works then the power-domains should be powered up
properly, as the PHY domain is nested inside the HSIO domain where the
controller is located according to my information. So the most likely
reason is still a clock path that isn't fully turned on.
Regards,
Lucas
> BTW, the access of PHY register is successful.
>
> Best Regards
> Richard Zhu
>
> > > > ---
> > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > +++++++++++++++++++++--
> > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > index 6b840c05dd77..69e533add539 100644
> > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > @@ -4,6 +4,7 @@
> > > > */
> > > >
> > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > #include <dt-bindings/gpio/gpio.h>
> > > > #include <dt-bindings/input/input.h> #include
> > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > interrupts = <GIC_SPI 89
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > #reset-cells = <1>;
> > > > };
> > > > +
> > > > + gpc: gpc@303a0000 {
> > > > + compatible = "fsl,imx8mp-gpc";
> > > > + reg = <0x303a0000 0x1000>;
> > > > + interrupt-parent = <&gic>;
> > > > + interrupt-controller;
> > > > + #interrupt-cells = <3>;
> > > > +
> > > > + pgc {
> > > > + #address-cells = <1>;
> > > > + #size-cells = <0>;
> > > > +
> > > > + pgc_pcie_phy: power-
> > > > domain@1 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > + };
> > > > +
> > > > + pgc_usb1_phy: power-
> > > > domain@2 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > + };
> > > > +
> > > > + pgc_usb2_phy: power-
> > > > domain@3 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > + };
> > > > +
> > > > + pgc_hsiomix:
> > > > power-domains@17 {
> > > > + #power-domain-
> > > > cells = <0>;
> > > > + reg =
> > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > + clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>,
> > > > + <&clk
> > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > + assigned-
> > > > clocks = <&clk
> > IMX8MP_CLK_HSIO_AXI>;
> > > > + assigned-
> > > > clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > + assigned-
> > > > clock-rates = <500000000>;
> > > > + };
> > > > + };
> > > > + };
> > > > };
> > > >
> > > > aips2: bus@30400000 {
> > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > };
> > > > };
> > > >
> > > > + aips4 {
> > >
> > > I think this should be
> > >
> > > aips4: bus@32c00000 {
> > >
> > > to match the other buses. Apart from that, the patch looks good,
> > > my Rb
> > > tag still applies.
> >
> > Urgh, apparently one shouldn't do those reworks too late in the
> > evening. :/
> >
> > Shawn, would you be willing to fix this up while applying, or
> > should I resend
> > the series?
> >
> > Regards,
> > Lucas
> >
> > >
> > > > + compatible = "fsl,aips-bus", "simple-
> > > > bus";
> > > > + reg = <0x32c00000 0x400000>;
> > > > + #address-cells = <1>;
> > > > + #size-cells = <1>;
> > > > + ranges;
> > > > +
> > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > + compatible = "fsl,imx8mp-hsio-
> > > > blk-ctrl", "syscon";
> > > > + reg = <0x32f10000 0x24>;
> > > > + clocks = <&clk
> > > > IMX8MP_CLK_USB_ROOT>,
> > > > + <&clk
> > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > + clock-names = "usb", "pcie";
> > > > + power-domains =
> > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > + <&pgc_usb1_phy
> > > > >, <&pgc_usb2_phy>,
> > > > + <&pgc_hsiomix>
> > > > , <&pgc_pcie_phy>;
> > > > + power-domain-names = "bus",
> > > > "usb", "usb-phy1",
> > > > + "usb-
> > > > phy2", "pcie", "pcie-phy";
> > > > + #power-domain-cells = <1>;
> > > > + };
> > > > + };
> > > > +
> > > > gic: interrupt-controller@38800000 {
> > > > compatible = "arm,gic-v3";
> > > > reg = <0x38800000 0x10000>,
> > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > clock-names = "phy";
> > > > assigned-clocks = <&clk
> > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > assigned-clock-parents = <&clk
> > > > IMX8MP_CLK_24M>;
> > > > + power-domains = <&hsio_blk_ctrl
> > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > #phy-cells = <0>;
> > > > status = "disabled";
> > > > };
> > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "hsio", "suspend";
> > > > interrupts = <GIC_SPI 148
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > > dma-ranges = <0x40000000 0x40000000
> > > > 0xc0000000>;
> > @@ -939,9
> > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > <&clk
> > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > <&clk
> > > > IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "bus_early",
> > > > "ref", "suspend";
> > > > - assigned-clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > - assigned-clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > - assigned-clock-rates =
> > > > <500000000>;
> > > > interrupts = <GIC_SPI 40
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > phys = <&usb3_phy0>,
> > > > <&usb3_phy0>;
> > > > phy-names = "usb2-phy", "usb3-
> > > > phy"; @@ -957,6
> > +1017,7 @@
> > > > usb3_phy1: usb-phy@382f0040 {
> > > > clock-names = "phy";
> > > > assigned-clocks = <&clk
> > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > assigned-clock-parents = <&clk
> > > > IMX8MP_CLK_24M>;
> > > > + power-domains = <&hsio_blk_ctrl
> > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > #phy-cells = <0>;
> > > > };
> > > >
> > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "hsio", "suspend";
> > > > interrupts = <GIC_SPI 149
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > #address-cells = <1>;
> > > > #size-cells = <1>;
> > > > dma-ranges = <0x40000000 0x40000000
> > > > 0xc0000000>;
> > @@ -980,9
> > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > <&clk
> > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > <&clk
> > > > IMX8MP_CLK_USB_ROOT>;
> > > > clock-names = "bus_early",
> > > > "ref", "suspend";
> > > > - assigned-clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > - assigned-clock-parents = <&clk
> > IMX8MP_SYS_PLL2_500M>;
> > > > - assigned-clock-rates =
> > > > <500000000>;
> > > > interrupts = <GIC_SPI 41
> > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > phys = <&usb3_phy1>,
> > > > <&usb3_phy1>;
> > > > phy-names = "usb2-phy", "usb3-
> > > > phy";
> > >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-02 9:18 ` Lucas Stach
@ 2022-03-02 11:29 ` Jun Li
-1 siblings, 0 replies; 48+ messages in thread
From: Jun Li @ 2022-03-02 11:29 UTC (permalink / raw)
To: Lucas Stach, Hongxing Zhu, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: Wednesday, March 2, 2022 5:19 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Hi Richard,
>
> Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <l.stach@pengutronix.de>
> > > Sent: 2022年3月1日 17:09
> > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org;
> > > patchwork-lst@pengutronix.de
> > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > domains
> > >
> > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > Pinchart:
> > > > Hi Lucas,
> > > >
> > > > Thank you for the patch.
> > > >
> > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > control for the high-speed (USB and PCIe) IOs.
> > > > >
> > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > Reviewed-by: Laurent Pinchart
> > > > > <laurent.pinchart@ideasonboard.com>
> > Hi Lucas:
> > Thank you for the patch.
> > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > i.MX8MP EVK.
> > But I encounter system hang when access the controller's register.
> > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > It seems that the pd of PCIe controller is not up properly.
> > More investigation is still on-going.
>
> Just to check the obvious things: you've put the controller into the
> IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY, right?
>
> If the PHY access works then the power-domains should be powered up properly,
> as the PHY domain is nested inside the HSIO domain where the controller is
> located according to my information. So the most likely reason is still a
> clock path that isn't fully turned on.
Tested USB and it works fine, so
Tested-by: Li Jun <jun.li@nxp.com>
>
> Regards,
> Lucas
>
> > BTW, the access of PHY register is successful.
> >
> > Best Regards
> > Richard Zhu
> >
> > > > > ---
> > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > +++++++++++++++++++++--
> > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > index 6b840c05dd77..69e533add539 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > @@ -4,6 +4,7 @@
> > > > > */
> > > > >
> > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > #include <dt-bindings/input/input.h> #include
> > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > interrupts = <GIC_SPI 89
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > > +
> > > > > + gpc: gpc@303a0000 {
> > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > + reg = <0x303a0000 0x1000>;
> > > > > + interrupt-parent = <&gic>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > +
> > > > > + pgc {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + pgc_pcie_phy: power-
> > > > > domain@1 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb1_phy: power-
> > > > > domain@2 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb2_phy: power-
> > > > > domain@3 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_hsiomix:
> > > > > power-domains@17 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > + assigned-
> > > > > clocks = <&clk
> > > IMX8MP_CLK_HSIO_AXI>;
> > > > > + assigned-
> > > > > clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > + assigned-
> > > > > clock-rates = <500000000>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > };
> > > > >
> > > > > aips2: bus@30400000 {
> > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > };
> > > > > };
> > > > >
> > > > > + aips4 {
> > > >
> > > > I think this should be
> > > >
> > > > aips4: bus@32c00000 {
> > > >
> > > > to match the other buses. Apart from that, the patch looks good,
> > > > my Rb tag still applies.
> > >
> > > Urgh, apparently one shouldn't do those reworks too late in the
> > > evening. :/
> > >
> > > Shawn, would you be willing to fix this up while applying, or should
> > > I resend the series?
> > >
> > > Regards,
> > > Lucas
> > >
> > > >
> > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > bus";
> > > > > + reg = <0x32c00000 0x400000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + ranges;
> > > > > +
> > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > blk-ctrl", "syscon";
> > > > > + reg = <0x32f10000 0x24>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > + clock-names = "usb", "pcie";
> > > > > + power-domains =
> > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > + <&pgc_usb1_phy
> > > > > >, <&pgc_usb2_phy>,
> > > > > + <&pgc_hsiomix>
> > > > > , <&pgc_pcie_phy>;
> > > > > + power-domain-names = "bus",
> > > > > "usb", "usb-phy1",
> > > > > + "usb-
> > > > > phy2", "pcie", "pcie-phy";
> > > > > + #power-domain-cells = <1>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > gic: interrupt-controller@38800000 {
> > > > > compatible = "arm,gic-v3";
> > > > > reg = <0x38800000 0x10000>,
> > > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > #phy-cells = <0>;
> > > > > status = "disabled";
> > > > > };
> > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 148
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -939,9
> > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 40
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy0>,
> > > > > <&usb3_phy0>;
> > > > > phy-names = "usb2-phy", "usb3- phy"; @@ -957,6
> > > +1017,7 @@
> > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > #phy-cells = <0>;
> > > > > };
> > > > >
> > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 149
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -980,9
> > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 41
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy1>,
> > > > > <&usb3_phy1>;
> > > > > phy-names = "usb2-phy", "usb3- phy";
> > > >
> > >
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-02 11:29 ` Jun Li
0 siblings, 0 replies; 48+ messages in thread
From: Jun Li @ 2022-03-02 11:29 UTC (permalink / raw)
To: Lucas Stach, Hongxing Zhu, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: Wednesday, March 2, 2022 5:19 PM
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Hi Richard,
>
> Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <l.stach@pengutronix.de>
> > > Sent: 2022年3月1日 17:09
> > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org;
> > > patchwork-lst@pengutronix.de
> > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > domains
> > >
> > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > Pinchart:
> > > > Hi Lucas,
> > > >
> > > > Thank you for the patch.
> > > >
> > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > control for the high-speed (USB and PCIe) IOs.
> > > > >
> > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > Reviewed-by: Laurent Pinchart
> > > > > <laurent.pinchart@ideasonboard.com>
> > Hi Lucas:
> > Thank you for the patch.
> > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > i.MX8MP EVK.
> > But I encounter system hang when access the controller's register.
> > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > It seems that the pd of PCIe controller is not up properly.
> > More investigation is still on-going.
>
> Just to check the obvious things: you've put the controller into the
> IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY, right?
>
> If the PHY access works then the power-domains should be powered up properly,
> as the PHY domain is nested inside the HSIO domain where the controller is
> located according to my information. So the most likely reason is still a
> clock path that isn't fully turned on.
Tested USB and it works fine, so
Tested-by: Li Jun <jun.li@nxp.com>
>
> Regards,
> Lucas
>
> > BTW, the access of PHY register is successful.
> >
> > Best Regards
> > Richard Zhu
> >
> > > > > ---
> > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > +++++++++++++++++++++--
> > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > index 6b840c05dd77..69e533add539 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > @@ -4,6 +4,7 @@
> > > > > */
> > > > >
> > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > #include <dt-bindings/input/input.h> #include
> > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > interrupts = <GIC_SPI 89
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > > +
> > > > > + gpc: gpc@303a0000 {
> > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > + reg = <0x303a0000 0x1000>;
> > > > > + interrupt-parent = <&gic>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > +
> > > > > + pgc {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + pgc_pcie_phy: power-
> > > > > domain@1 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb1_phy: power-
> > > > > domain@2 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb2_phy: power-
> > > > > domain@3 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_hsiomix:
> > > > > power-domains@17 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > + assigned-
> > > > > clocks = <&clk
> > > IMX8MP_CLK_HSIO_AXI>;
> > > > > + assigned-
> > > > > clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > + assigned-
> > > > > clock-rates = <500000000>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > };
> > > > >
> > > > > aips2: bus@30400000 {
> > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > };
> > > > > };
> > > > >
> > > > > + aips4 {
> > > >
> > > > I think this should be
> > > >
> > > > aips4: bus@32c00000 {
> > > >
> > > > to match the other buses. Apart from that, the patch looks good,
> > > > my Rb tag still applies.
> > >
> > > Urgh, apparently one shouldn't do those reworks too late in the
> > > evening. :/
> > >
> > > Shawn, would you be willing to fix this up while applying, or should
> > > I resend the series?
> > >
> > > Regards,
> > > Lucas
> > >
> > > >
> > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > bus";
> > > > > + reg = <0x32c00000 0x400000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + ranges;
> > > > > +
> > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > blk-ctrl", "syscon";
> > > > > + reg = <0x32f10000 0x24>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > + clock-names = "usb", "pcie";
> > > > > + power-domains =
> > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > + <&pgc_usb1_phy
> > > > > >, <&pgc_usb2_phy>,
> > > > > + <&pgc_hsiomix>
> > > > > , <&pgc_pcie_phy>;
> > > > > + power-domain-names = "bus",
> > > > > "usb", "usb-phy1",
> > > > > + "usb-
> > > > > phy2", "pcie", "pcie-phy";
> > > > > + #power-domain-cells = <1>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > gic: interrupt-controller@38800000 {
> > > > > compatible = "arm,gic-v3";
> > > > > reg = <0x38800000 0x10000>,
> > > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > #phy-cells = <0>;
> > > > > status = "disabled";
> > > > > };
> > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 148
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -939,9
> > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 40
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy0>,
> > > > > <&usb3_phy0>;
> > > > > phy-names = "usb2-phy", "usb3- phy"; @@ -957,6
> > > +1017,7 @@
> > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > #phy-cells = <0>;
> > > > > };
> > > > >
> > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 149
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -980,9
> > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 41
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy1>,
> > > > > <&usb3_phy1>;
> > > > > phy-names = "usb2-phy", "usb3- phy";
> > > >
> > >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: (EXT) [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes
2022-02-28 20:17 ` Lucas Stach
@ 2022-03-02 16:49 ` Alexander Stein
-1 siblings, 0 replies; 48+ messages in thread
From: Alexander Stein @ 2022-03-02 16:49 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: linux-arm-kernel, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, Laurent Pinchart, devicetree, linux-arm-kernel,
patchwork-lst, Lucas Stach
Am Montag, 28. Februar 2022, 21:17:31 CET schrieb Lucas Stach:
> Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP.
>
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
> etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
> [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 9f2c335cc7a1..3ded7314c473 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -980,6 +980,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
> };
> };
>
> + gpu3d: gpu@38000000 {
> + compatible = "vivante,gc";
> + reg = <0x38000000 0x8000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
> + <&clk
IMX8MP_CLK_GPU3D_SHADER_CORE>,
> + <&clk IMX8MP_CLK_GPU_ROOT>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + clock-names = "core", "shader", "bus", "reg";
> + assigned-clocks = <&clk
IMX8MP_CLK_GPU3D_CORE>,
> + <&clk
IMX8MP_CLK_GPU3D_SHADER_CORE>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL1_800M>,
> + <&clk
IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <800000000>,
<800000000>;
> + power-domains = <&pgc_gpu3d>;
> + };
> +
> + gpu2d: gpu@38008000 {
> + compatible = "vivante,gc";
> + reg = <0x38008000 0x8000>;
> + interrupts = <GIC_SPI 25
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
> + <&clk IMX8MP_CLK_GPU_ROOT>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + clock-names = "core", "bus", "reg";
> + assigned-clocks = <&clk
IMX8MP_CLK_GPU2D_CORE>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <800000000>;
> + power-domains = <&pgc_gpu2d>;
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: (EXT) [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes
@ 2022-03-02 16:49 ` Alexander Stein
0 siblings, 0 replies; 48+ messages in thread
From: Alexander Stein @ 2022-03-02 16:49 UTC (permalink / raw)
To: Shawn Guo, Rob Herring
Cc: linux-arm-kernel, Pengutronix Kernel Team, NXP Linux Team,
Marek Vasut, Laurent Pinchart, devicetree, linux-arm-kernel,
patchwork-lst, Lucas Stach
Am Montag, 28. Februar 2022, 21:17:31 CET schrieb Lucas Stach:
> Add the DT nodes for both the 3D and 2D GPU cores found on the i.MX8MP.
>
> etnaviv-gpu 38000000.gpu: model: GC7000, revision: 6204
> etnaviv-gpu 38008000.gpu: model: GC520, revision: 5341
> [drm] Initialized etnaviv 1.3.0 20151214 for etnaviv on minor 0
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 31 +++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 9f2c335cc7a1..3ded7314c473 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -980,6 +980,37 @@ hsio_blk_ctrl: blk-ctrl@32f10000 {
> };
> };
>
> + gpu3d: gpu@38000000 {
> + compatible = "vivante,gc";
> + reg = <0x38000000 0x8000>;
> + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPU3D_ROOT>,
> + <&clk
IMX8MP_CLK_GPU3D_SHADER_CORE>,
> + <&clk IMX8MP_CLK_GPU_ROOT>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + clock-names = "core", "shader", "bus", "reg";
> + assigned-clocks = <&clk
IMX8MP_CLK_GPU3D_CORE>,
> + <&clk
IMX8MP_CLK_GPU3D_SHADER_CORE>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL1_800M>,
> + <&clk
IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <800000000>,
<800000000>;
> + power-domains = <&pgc_gpu3d>;
> + };
> +
> + gpu2d: gpu@38008000 {
> + compatible = "vivante,gc";
> + reg = <0x38008000 0x8000>;
> + interrupts = <GIC_SPI 25
IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&clk IMX8MP_CLK_GPU2D_ROOT>,
> + <&clk IMX8MP_CLK_GPU_ROOT>,
> + <&clk IMX8MP_CLK_GPU_AHB>;
> + clock-names = "core", "bus", "reg";
> + assigned-clocks = <&clk
IMX8MP_CLK_GPU2D_CORE>;
> + assigned-clock-parents = <&clk
IMX8MP_SYS_PLL1_800M>;
> + assigned-clock-rates = <800000000>;
> + power-domains = <&pgc_gpu2d>;
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: (EXT) [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-02-28 20:17 ` Lucas Stach
@ 2022-03-02 16:49 ` Alexander Stein
-1 siblings, 0 replies; 48+ messages in thread
From: Alexander Stein @ 2022-03-02 16:49 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, linux-arm-kernel
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst,
Lucas Stach
Am Montag, 28. Februar 2022, 21:17:29 CET schrieb Lucas Stach:
> This adds the GPC and HSIO blk-ctrl nodes providing power control for
> the high-speed (USB and PCIe) IOs.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 6b840c05dd77..69e533add539 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/power/imx8mp-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89
IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mp-gpc";
> + reg = <0x303a0000 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_pcie_phy: power-
domain@1 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> + };
> +
> + pgc_usb1_phy: power-
domain@2 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_USB1_PHY>;
> + };
> +
> + pgc_usb2_phy: power-
domain@3 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_USB2_PHY>;
> + };
> +
> + pgc_hsiomix: power-
domains@17 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_HSIOMIX>;
> + clocks =
<&clk IMX8MP_CLK_HSIO_AXI>,
> +
<&clk IMX8MP_CLK_HSIO_ROOT>;
> + assigned-
clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-
clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-
clock-rates = <500000000>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> };
> };
>
> + aips4 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x32c00000 0x400000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + hsio_blk_ctrl: blk-ctrl@32f10000 {
> + compatible = "fsl,imx8mp-hsio-blk-
ctrl", "syscon";
> + reg = <0x32f10000 0x24>;
> + clocks = <&clk
IMX8MP_CLK_USB_ROOT>,
> + <&clk
IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "usb", "pcie";
> + power-domains = <&pgc_hsiomix>,
<&pgc_hsiomix>,
> +
<&pgc_usb1_phy>, <&pgc_usb2_phy>,
> +
<&pgc_hsiomix>, <&pgc_pcie_phy>;
> + power-domain-names = "bus", "usb",
"usb-phy1",
> + "usb-
phy2", "pcie", "pcie-phy";
> + #power-domain-cells = <1>;
> + };
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
> @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk
IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk
IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB_PHY1>;
> #phy-cells = <0>;
> status = "disabled";
> };
> @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 148
IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000
0xc0000000>;
> @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> <&clk
IMX8MP_CLK_USB_CORE_REF>,
> <&clk
IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref",
"suspend";
> - assigned-clocks = <&clk
IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates =
<500000000>;
> interrupts = <GIC_SPI 40
IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy0>, <&usb3_phy0>;
> phy-names = "usb2-phy", "usb3-
phy";
> @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk
IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk
IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB_PHY2>;
> #phy-cells = <0>;
> };
>
> @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000
0xc0000000>;
> @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> <&clk
IMX8MP_CLK_USB_CORE_REF>,
> <&clk
IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref",
"suspend";
> - assigned-clocks = <&clk
IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates =
<500000000>;
> interrupts = <GIC_SPI 41
IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy1>, <&usb3_phy1>;
> phy-names = "usb2-phy", "usb3-
phy";
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: (EXT) [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-02 16:49 ` Alexander Stein
0 siblings, 0 replies; 48+ messages in thread
From: Alexander Stein @ 2022-03-02 16:49 UTC (permalink / raw)
To: Shawn Guo, Rob Herring, linux-arm-kernel
Cc: Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst,
Lucas Stach
Am Montag, 28. Februar 2022, 21:17:29 CET schrieb Lucas Stach:
> This adds the GPC and HSIO blk-ctrl nodes providing power control for
> the high-speed (USB and PCIe) IOs.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> ---
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71 +++++++++++++++++++++--
> 1 file changed, 65 insertions(+), 6 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> 6b840c05dd77..69e533add539 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -4,6 +4,7 @@
> */
>
> #include <dt-bindings/clock/imx8mp-clock.h>
> +#include <dt-bindings/power/imx8mp-power.h>
> #include <dt-bindings/gpio/gpio.h>
> #include <dt-bindings/input/input.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> interrupts = <GIC_SPI 89
IRQ_TYPE_LEVEL_HIGH>;
> #reset-cells = <1>;
> };
> +
> + gpc: gpc@303a0000 {
> + compatible = "fsl,imx8mp-gpc";
> + reg = <0x303a0000 0x1000>;
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + pgc {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pgc_pcie_phy: power-
domain@1 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> + };
> +
> + pgc_usb1_phy: power-
domain@2 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_USB1_PHY>;
> + };
> +
> + pgc_usb2_phy: power-
domain@3 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_USB2_PHY>;
> + };
> +
> + pgc_hsiomix: power-
domains@17 {
> + #power-
domain-cells = <0>;
> + reg =
<IMX8MP_POWER_DOMAIN_HSIOMIX>;
> + clocks =
<&clk IMX8MP_CLK_HSIO_AXI>,
> +
<&clk IMX8MP_CLK_HSIO_ROOT>;
> + assigned-
clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
> + assigned-
clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
> + assigned-
clock-rates = <500000000>;
> + };
> + };
> + };
> };
>
> aips2: bus@30400000 {
> @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> };
> };
>
> + aips4 {
> + compatible = "fsl,aips-bus", "simple-bus";
> + reg = <0x32c00000 0x400000>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + hsio_blk_ctrl: blk-ctrl@32f10000 {
> + compatible = "fsl,imx8mp-hsio-blk-
ctrl", "syscon";
> + reg = <0x32f10000 0x24>;
> + clocks = <&clk
IMX8MP_CLK_USB_ROOT>,
> + <&clk
IMX8MP_CLK_PCIE_ROOT>;
> + clock-names = "usb", "pcie";
> + power-domains = <&pgc_hsiomix>,
<&pgc_hsiomix>,
> +
<&pgc_usb1_phy>, <&pgc_usb2_phy>,
> +
<&pgc_hsiomix>, <&pgc_pcie_phy>;
> + power-domain-names = "bus", "usb",
"usb-phy1",
> + "usb-
phy2", "pcie", "pcie-phy";
> + #power-domain-cells = <1>;
> + };
> + };
> +
> gic: interrupt-controller@38800000 {
> compatible = "arm,gic-v3";
> reg = <0x38800000 0x10000>,
> @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk
IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk
IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB_PHY1>;
> #phy-cells = <0>;
> status = "disabled";
> };
> @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 148
IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000
0xc0000000>;
> @@ -939,9 +1002,6 @@ usb_dwc3_0: usb@38100000 {
> <&clk
IMX8MP_CLK_USB_CORE_REF>,
> <&clk
IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref",
"suspend";
> - assigned-clocks = <&clk
IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates =
<500000000>;
> interrupts = <GIC_SPI 40
IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy0>, <&usb3_phy0>;
> phy-names = "usb2-phy", "usb3-
phy";
> @@ -957,6 +1017,7 @@ usb3_phy1: usb-phy@382f0040 {
> clock-names = "phy";
> assigned-clocks = <&clk
IMX8MP_CLK_USB_PHY_REF>;
> assigned-clock-parents = <&clk
IMX8MP_CLK_24M>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB_PHY2>;
> #phy-cells = <0>;
> };
>
> @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> <&clk IMX8MP_CLK_USB_ROOT>;
> clock-names = "hsio", "suspend";
> interrupts = <GIC_SPI 149
IRQ_TYPE_LEVEL_HIGH>;
> + power-domains = <&hsio_blk_ctrl
IMX8MP_HSIOBLK_PD_USB>;
> #address-cells = <1>;
> #size-cells = <1>;
> dma-ranges = <0x40000000 0x40000000
0xc0000000>;
> @@ -980,9 +1042,6 @@ usb_dwc3_1: usb@38200000 {
> <&clk
IMX8MP_CLK_USB_CORE_REF>,
> <&clk
IMX8MP_CLK_USB_ROOT>;
> clock-names = "bus_early", "ref",
"suspend";
> - assigned-clocks = <&clk
IMX8MP_CLK_HSIO_AXI>;
> - assigned-clock-parents = <&clk
IMX8MP_SYS_PLL2_500M>;
> - assigned-clock-rates =
<500000000>;
> interrupts = <GIC_SPI 41
IRQ_TYPE_LEVEL_HIGH>;
> phys = <&usb3_phy1>, <&usb3_phy1>;
> phy-names = "usb2-phy", "usb3-
phy";
Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
2022-02-28 20:17 ` Lucas Stach
@ 2022-03-02 17:39 ` Rob Herring
-1 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-03-02 17:39 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
On Mon, Feb 28, 2022 at 09:17:28PM +0100, Lucas Stach wrote:
> The USB controllers in the i.MX8MP are located inside the HSIO
> power domain. Add the power-domains property to the DT binding
> to be able to describe the hardware properly.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
@ 2022-03-02 17:39 ` Rob Herring
0 siblings, 0 replies; 48+ messages in thread
From: Rob Herring @ 2022-03-02 17:39 UTC (permalink / raw)
To: Lucas Stach
Cc: Shawn Guo, Pengutronix Kernel Team, NXP Linux Team, Marek Vasut,
Laurent Pinchart, devicetree, linux-arm-kernel, patchwork-lst
On Mon, Feb 28, 2022 at 09:17:28PM +0100, Lucas Stach wrote:
> The USB controllers in the i.MX8MP are located inside the HSIO
> power domain. Add the power-domains property to the DT binding
> to be able to describe the hardware properly.
>
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
> Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
> 1 file changed, 6 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-02 9:18 ` Lucas Stach
@ 2022-03-03 2:22 ` Hongxing Zhu
-1 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-03 2:22 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年3月2日 17:19
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Hi Richard,
>
> Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <l.stach@pengutronix.de>
> > > Sent: 2022年3月1日 17:09
> > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org;
> > > patchwork-lst@pengutronix.de
> > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > domains
> > >
> > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > Pinchart:
> > > > Hi Lucas,
> > > >
> > > > Thank you for the patch.
> > > >
> > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > control for the high-speed (USB and PCIe) IOs.
> > > > >
> > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > Reviewed-by: Laurent Pinchart
> > > > > <laurent.pinchart@ideasonboard.com>
> > Hi Lucas:
> > Thank you for the patch.
> > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > i.MX8MP EVK.
> > But I encounter system hang when access the controller's register.
> > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > It seems that the pd of PCIe controller is not up properly.
> > More investigation is still on-going.
>
> Just to check the obvious things: you've put the controller into the
> IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY,
> right?
>
> If the PHY access works then the power-domains should be powered up
> properly, as the PHY domain is nested inside the HSIO domain where the
> controller is located according to my information. So the most likely reason is
> still a clock path that isn't fully turned on.
Hi Lucas:
Thanks for your reply.
Yes, I had put the controller into the IMX8MP_HSIOBLK_PD_PCIE.
And the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY.
Your assumption is reasonable, I would do more debug on the clock.
Thanks.
Best Regards
Richard Zhu
>
> Regards,
> Lucas
>
> > BTW, the access of PHY register is successful.
> >
> > Best Regards
> > Richard Zhu
> >
> > > > > ---
> > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > +++++++++++++++++++++--
> > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > index 6b840c05dd77..69e533add539 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > @@ -4,6 +4,7 @@
> > > > > */
> > > > >
> > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > #include <dt-bindings/input/input.h> #include
> > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > interrupts = <GIC_SPI 89
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > > +
> > > > > + gpc: gpc@303a0000 {
> > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > + reg = <0x303a0000 0x1000>;
> > > > > + interrupt-parent = <&gic>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > +
> > > > > + pgc {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + pgc_pcie_phy: power-
> > > > > domain@1 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb1_phy: power-
> > > > > domain@2 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb2_phy: power-
> > > > > domain@3 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_hsiomix:
> > > > > power-domains@17 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > + assigned-
> > > > > clocks = <&clk
> > > IMX8MP_CLK_HSIO_AXI>;
> > > > > + assigned-
> > > > > clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > + assigned-
> > > > > clock-rates = <500000000>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > };
> > > > >
> > > > > aips2: bus@30400000 {
> > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > };
> > > > > };
> > > > >
> > > > > + aips4 {
> > > >
> > > > I think this should be
> > > >
> > > > aips4: bus@32c00000 {
> > > >
> > > > to match the other buses. Apart from that, the patch looks good,
> > > > my Rb tag still applies.
> > >
> > > Urgh, apparently one shouldn't do those reworks too late in the
> > > evening. :/
> > >
> > > Shawn, would you be willing to fix this up while applying, or should
> > > I resend the series?
> > >
> > > Regards,
> > > Lucas
> > >
> > > >
> > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > bus";
> > > > > + reg = <0x32c00000 0x400000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + ranges;
> > > > > +
> > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > blk-ctrl", "syscon";
> > > > > + reg = <0x32f10000 0x24>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > + clock-names = "usb", "pcie";
> > > > > + power-domains =
> > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > + <&pgc_usb1_phy
> > > > > >, <&pgc_usb2_phy>,
> > > > > + <&pgc_hsiomix>
> > > > > , <&pgc_pcie_phy>;
> > > > > + power-domain-names = "bus",
> > > > > "usb", "usb-phy1",
> > > > > + "usb-
> > > > > phy2", "pcie", "pcie-phy";
> > > > > + #power-domain-cells = <1>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > gic: interrupt-controller@38800000 {
> > > > > compatible = "arm,gic-v3";
> > > > > reg = <0x38800000 0x10000>,
> > > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > #phy-cells = <0>;
> > > > > status = "disabled";
> > > > > };
> > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 148
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -939,9
> > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 40
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy0>,
> > > > > <&usb3_phy0>;
> > > > > phy-names = "usb2-phy", "usb3- phy"; @@ -957,6
> > > +1017,7 @@
> > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > #phy-cells = <0>;
> > > > > };
> > > > >
> > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 149
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -980,9
> > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 41
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy1>,
> > > > > <&usb3_phy1>;
> > > > > phy-names = "usb2-phy", "usb3- phy";
> > > >
> > >
> >
>
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-03 2:22 ` Hongxing Zhu
0 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-03 2:22 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Lucas Stach <l.stach@pengutronix.de>
> Sent: 2022年3月2日 17:19
> To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> Hi Richard,
>
> Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > -----Original Message-----
> > > From: Lucas Stach <l.stach@pengutronix.de>
> > > Sent: 2022年3月1日 17:09
> > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > linux-arm-kernel@lists.infradead.org;
> > > patchwork-lst@pengutronix.de
> > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > domains
> > >
> > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > Pinchart:
> > > > Hi Lucas,
> > > >
> > > > Thank you for the patch.
> > > >
> > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > control for the high-speed (USB and PCIe) IOs.
> > > > >
> > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > Reviewed-by: Laurent Pinchart
> > > > > <laurent.pinchart@ideasonboard.com>
> > Hi Lucas:
> > Thank you for the patch.
> > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > i.MX8MP EVK.
> > But I encounter system hang when access the controller's register.
> > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > It seems that the pd of PCIe controller is not up properly.
> > More investigation is still on-going.
>
> Just to check the obvious things: you've put the controller into the
> IMX8MP_HSIOBLK_PD_PCIE and the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY,
> right?
>
> If the PHY access works then the power-domains should be powered up
> properly, as the PHY domain is nested inside the HSIO domain where the
> controller is located according to my information. So the most likely reason is
> still a clock path that isn't fully turned on.
Hi Lucas:
Thanks for your reply.
Yes, I had put the controller into the IMX8MP_HSIOBLK_PD_PCIE.
And the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY.
Your assumption is reasonable, I would do more debug on the clock.
Thanks.
Best Regards
Richard Zhu
>
> Regards,
> Lucas
>
> > BTW, the access of PHY register is successful.
> >
> > Best Regards
> > Richard Zhu
> >
> > > > > ---
> > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > +++++++++++++++++++++--
> > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > >
> > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > index 6b840c05dd77..69e533add539 100644
> > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > @@ -4,6 +4,7 @@
> > > > > */
> > > > >
> > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > #include <dt-bindings/input/input.h> #include
> > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > interrupts = <GIC_SPI 89
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > #reset-cells = <1>;
> > > > > };
> > > > > +
> > > > > + gpc: gpc@303a0000 {
> > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > + reg = <0x303a0000 0x1000>;
> > > > > + interrupt-parent = <&gic>;
> > > > > + interrupt-controller;
> > > > > + #interrupt-cells = <3>;
> > > > > +
> > > > > + pgc {
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <0>;
> > > > > +
> > > > > + pgc_pcie_phy: power-
> > > > > domain@1 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb1_phy: power-
> > > > > domain@2 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_usb2_phy: power-
> > > > > domain@3 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > + };
> > > > > +
> > > > > + pgc_hsiomix:
> > > > > power-domains@17 {
> > > > > + #power-domain-
> > > > > cells = <0>;
> > > > > + reg =
> > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > + assigned-
> > > > > clocks = <&clk
> > > IMX8MP_CLK_HSIO_AXI>;
> > > > > + assigned-
> > > > > clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > + assigned-
> > > > > clock-rates = <500000000>;
> > > > > + };
> > > > > + };
> > > > > + };
> > > > > };
> > > > >
> > > > > aips2: bus@30400000 {
> > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > };
> > > > > };
> > > > >
> > > > > + aips4 {
> > > >
> > > > I think this should be
> > > >
> > > > aips4: bus@32c00000 {
> > > >
> > > > to match the other buses. Apart from that, the patch looks good,
> > > > my Rb tag still applies.
> > >
> > > Urgh, apparently one shouldn't do those reworks too late in the
> > > evening. :/
> > >
> > > Shawn, would you be willing to fix this up while applying, or should
> > > I resend the series?
> > >
> > > Regards,
> > > Lucas
> > >
> > > >
> > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > bus";
> > > > > + reg = <0x32c00000 0x400000>;
> > > > > + #address-cells = <1>;
> > > > > + #size-cells = <1>;
> > > > > + ranges;
> > > > > +
> > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > blk-ctrl", "syscon";
> > > > > + reg = <0x32f10000 0x24>;
> > > > > + clocks = <&clk
> > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > + <&clk
> > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > + clock-names = "usb", "pcie";
> > > > > + power-domains =
> > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > + <&pgc_usb1_phy
> > > > > >, <&pgc_usb2_phy>,
> > > > > + <&pgc_hsiomix>
> > > > > , <&pgc_pcie_phy>;
> > > > > + power-domain-names = "bus",
> > > > > "usb", "usb-phy1",
> > > > > + "usb-
> > > > > phy2", "pcie", "pcie-phy";
> > > > > + #power-domain-cells = <1>;
> > > > > + };
> > > > > + };
> > > > > +
> > > > > gic: interrupt-controller@38800000 {
> > > > > compatible = "arm,gic-v3";
> > > > > reg = <0x38800000 0x10000>,
> > > > > @@ -915,6 +976,7 @@ usb3_phy0: usb-phy@381f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > #phy-cells = <0>;
> > > > > status = "disabled";
> > > > > };
> > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 148
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -939,9
> > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 40
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy0>,
> > > > > <&usb3_phy0>;
> > > > > phy-names = "usb2-phy", "usb3- phy"; @@ -957,6
> > > +1017,7 @@
> > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > clock-names = "phy";
> > > > > assigned-clocks = <&clk
> > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > #phy-cells = <0>;
> > > > > };
> > > > >
> > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "hsio", "suspend";
> > > > > interrupts = <GIC_SPI 149
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > + power-domains = <&hsio_blk_ctrl
> > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > #address-cells = <1>;
> > > > > #size-cells = <1>;
> > > > > dma-ranges = <0x40000000 0x40000000
> > > > > 0xc0000000>;
> > > @@ -980,9
> > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > <&clk
> > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > clock-names = "bus_early",
> > > > > "ref", "suspend";
> > > > > - assigned-clocks = <&clk
> > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > - assigned-clock-parents = <&clk
> > > IMX8MP_SYS_PLL2_500M>;
> > > > > - assigned-clock-rates =
> > > > > <500000000>;
> > > > > interrupts = <GIC_SPI 41
> > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > phys = <&usb3_phy1>,
> > > > > <&usb3_phy1>;
> > > > > phy-names = "usb2-phy", "usb3- phy";
> > > >
> > >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
2022-03-03 2:22 ` Hongxing Zhu
@ 2022-03-03 4:08 ` Hongxing Zhu
-1 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-03 4:08 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Hongxing Zhu <hongxing.zhu@nxp.com>
> Sent: 2022年3月3日 10:23
> To: Lucas Stach <l.stach@pengutronix.de>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年3月2日 17:19
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> > <laurent.pinchart@ideasonboard.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> <robh+dt@kernel.org>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> > <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > patchwork-lst@pengutronix.de
> > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
> >
> > Hi Richard,
> >
> > Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > > -----Original Message-----
> > > > From: Lucas Stach <l.stach@pengutronix.de>
> > > > Sent: 2022年3月1日 17:09
> > > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > > linux-arm-kernel@lists.infradead.org;
> > > > patchwork-lst@pengutronix.de
> > > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > > domains
> > > >
> > > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > > Pinchart:
> > > > > Hi Lucas,
> > > > >
> > > > > Thank you for the patch.
> > > > >
> > > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > > control for the high-speed (USB and PCIe) IOs.
> > > > > >
> > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > > Reviewed-by: Laurent Pinchart
> > > > > > <laurent.pinchart@ideasonboard.com>
> > > Hi Lucas:
> > > Thank you for the patch.
> > > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > > i.MX8MP EVK.
> > > But I encounter system hang when access the controller's register.
> > > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > > It seems that the pd of PCIe controller is not up properly.
> > > More investigation is still on-going.
> >
> > Just to check the obvious things: you've put the controller into the
> > IMX8MP_HSIOBLK_PD_PCIE and the PHY into
> IMX8MP_HSIOBLK_PD_PCIE_PHY,
> > right?
> >
> > If the PHY access works then the power-domains should be powered up
> > properly, as the PHY domain is nested inside the HSIO domain where the
> > controller is located according to my information. So the most likely
> > reason is still a clock path that isn't fully turned on.
> Hi Lucas:
> Thanks for your reply.
> Yes, I had put the controller into the IMX8MP_HSIOBLK_PD_PCIE.
> And the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY.
> Your assumption is reasonable, I would do more debug on the clock.
> Thanks.
>
> Best Regards
> Richard Zhu
>
Hi Lucas:
Find the root cause, it's caused by one missing reset configurations.
I would summit one reset patch when bring up the i.MX8MP PCIe patches later.
i.MX8MP PCIe works fine after add one more reset patch.
Thanks.
Tested-by: Richard Zhu <hongxing.zhu@nxp.com>
Best Regards
Richard Zhu
> >
> > Regards,
> > Lucas
> >
> > > BTW, the access of PHY register is successful.
> > >
> > > Best Regards
> > > Richard Zhu
> > >
> > > > > > ---
> > > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > > +++++++++++++++++++++--
> > > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > index 6b840c05dd77..69e533add539 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > @@ -4,6 +4,7 @@
> > > > > > */
> > > > > >
> > > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > > #include <dt-bindings/input/input.h> #include
> > > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > > interrupts = <GIC_SPI 89
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > #reset-cells = <1>;
> > > > > > };
> > > > > > +
> > > > > > + gpc: gpc@303a0000 {
> > > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > > + reg = <0x303a0000 0x1000>;
> > > > > > + interrupt-parent = <&gic>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <3>;
> > > > > > +
> > > > > > + pgc {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + pgc_pcie_phy: power-
> > > > > > domain@1 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_usb1_phy: power-
> > > > > > domain@2 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_usb2_phy: power-
> > > > > > domain@3 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_hsiomix:
> > > > > > power-domains@17 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > > + <&clk
> > > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > > + assigned-
> > > > > > clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > + assigned-
> > > > > > clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > + assigned-
> > > > > > clock-rates = <500000000>;
> > > > > > + };
> > > > > > + };
> > > > > > + };
> > > > > > };
> > > > > >
> > > > > > aips2: bus@30400000 {
> > > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > > };
> > > > > > };
> > > > > >
> > > > > > + aips4 {
> > > > >
> > > > > I think this should be
> > > > >
> > > > > aips4: bus@32c00000 {
> > > > >
> > > > > to match the other buses. Apart from that, the patch looks good,
> > > > > my Rb tag still applies.
> > > >
> > > > Urgh, apparently one shouldn't do those reworks too late in the
> > > > evening. :/
> > > >
> > > > Shawn, would you be willing to fix this up while applying, or
> > > > should I resend the series?
> > > >
> > > > Regards,
> > > > Lucas
> > > >
> > > > >
> > > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > > bus";
> > > > > > + reg = <0x32c00000 0x400000>;
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <1>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > > blk-ctrl", "syscon";
> > > > > > + reg = <0x32f10000 0x24>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > > + clock-names = "usb", "pcie";
> > > > > > + power-domains =
> > > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > > + <&pgc_usb1_phy
> > > > > > >, <&pgc_usb2_phy>,
> > > > > > + <&pgc_hsiomix>
> > > > > > , <&pgc_pcie_phy>;
> > > > > > + power-domain-names = "bus",
> > > > > > "usb", "usb-phy1",
> > > > > > + "usb-
> > > > > > phy2", "pcie", "pcie-phy";
> > > > > > + #power-domain-cells = <1>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > gic: interrupt-controller@38800000 {
> > > > > > compatible = "arm,gic-v3";
> > > > > > reg = <0x38800000 0x10000>, @@ -915,6 +976,7
> @@ usb3_phy0:
> > > > > > usb-phy@381f0040 {
> > > > > > clock-names = "phy";
> > > > > > assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > > #phy-cells = <0>;
> > > > > > status = "disabled";
> > > > > > };
> > > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "hsio", "suspend";
> > > > > > interrupts = <GIC_SPI 148
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > #address-cells = <1>;
> > > > > > #size-cells = <1>;
> > > > > > dma-ranges = <0x40000000 0x40000000
> > > > > > 0xc0000000>;
> > > > @@ -939,9
> > > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "bus_early", "ref", "suspend";
> > > > > > - assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > - assigned-clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > - assigned-clock-rates =
> > > > > > <500000000>;
> > > > > > interrupts = <GIC_SPI 40
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > phys = <&usb3_phy0>,
> > > > > > <&usb3_phy0>;
> > > > > > phy-names = "usb2-phy", "usb3- phy"; @@
> -957,6
> > > > +1017,7 @@
> > > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > > clock-names = "phy";
> > > > > > assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > > #phy-cells = <0>;
> > > > > > };
> > > > > >
> > > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "hsio", "suspend";
> > > > > > interrupts = <GIC_SPI 149
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > #address-cells = <1>;
> > > > > > #size-cells = <1>;
> > > > > > dma-ranges = <0x40000000 0x40000000
> > > > > > 0xc0000000>;
> > > > @@ -980,9
> > > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "bus_early", "ref", "suspend";
> > > > > > - assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > - assigned-clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > - assigned-clock-rates =
> > > > > > <500000000>;
> > > > > > interrupts = <GIC_SPI 41
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > phys = <&usb3_phy1>,
> > > > > > <&usb3_phy1>;
> > > > > > phy-names = "usb2-phy", "usb3- phy";
> > > > >
> > > >
> > >
> >
^ permalink raw reply [flat|nested] 48+ messages in thread
* RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
@ 2022-03-03 4:08 ` Hongxing Zhu
0 siblings, 0 replies; 48+ messages in thread
From: Hongxing Zhu @ 2022-03-03 4:08 UTC (permalink / raw)
To: Lucas Stach, Laurent Pinchart
Cc: Shawn Guo, Rob Herring, Pengutronix Kernel Team, dl-linux-imx,
Marek Vasut, devicetree, linux-arm-kernel, patchwork-lst
> -----Original Message-----
> From: Hongxing Zhu <hongxing.zhu@nxp.com>
> Sent: 2022年3月3日 10:23
> To: Lucas Stach <l.stach@pengutronix.de>; Laurent Pinchart
> <laurent.pinchart@ideasonboard.com>
> Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring <robh+dt@kernel.org>;
> Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> patchwork-lst@pengutronix.de
> Subject: RE: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
>
> > -----Original Message-----
> > From: Lucas Stach <l.stach@pengutronix.de>
> > Sent: 2022年3月2日 17:19
> > To: Hongxing Zhu <hongxing.zhu@nxp.com>; Laurent Pinchart
> > <laurent.pinchart@ideasonboard.com>
> > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> <robh+dt@kernel.org>;
> > Pengutronix Kernel Team <kernel@pengutronix.de>; dl-linux-imx
> > <linux-imx@nxp.com>; Marek Vasut <marex@denx.de>;
> > devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> > patchwork-lst@pengutronix.de
> > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains
> >
> > Hi Richard,
> >
> > Am Mittwoch, dem 02.03.2022 um 08:47 +0000 schrieb Hongxing Zhu:
> > > > -----Original Message-----
> > > > From: Lucas Stach <l.stach@pengutronix.de>
> > > > Sent: 2022年3月1日 17:09
> > > > To: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> > > > Cc: Shawn Guo <shawnguo@kernel.org>; Rob Herring
> > > > <robh+dt@kernel.org>; Pengutronix Kernel Team
> > > > <kernel@pengutronix.de>; dl-linux-imx <linux-imx@nxp.com>; Marek
> > > > Vasut <marex@denx.de>; devicetree@vger.kernel.org;
> > > > linux-arm-kernel@lists.infradead.org;
> > > > patchwork-lst@pengutronix.de
> > > > Subject: Re: [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-
> > > > domains
> > > >
> > > > Am Dienstag, dem 01.03.2022 um 09:13 +0200 schrieb Laurent
> > > > Pinchart:
> > > > > Hi Lucas,
> > > > >
> > > > > Thank you for the patch.
> > > > >
> > > > > On Mon, Feb 28, 2022 at 09:17:29PM +0100, Lucas Stach wrote:
> > > > > > This adds the GPC and HSIO blk-ctrl nodes providing power
> > > > > > control for the high-speed (USB and PCIe) IOs.
> > > > > >
> > > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > > > > > Reviewed-by: Laurent Pinchart
> > > > > > <laurent.pinchart@ideasonboard.com>
> > > Hi Lucas:
> > > Thank you for the patch.
> > > Based on this V3 serial patch-set. I'm trying to bring up PCIe on
> > > i.MX8MP EVK.
> > > But I encounter system hang when access the controller's register.
> > > Clocks are turned on refer to the /sys/kernel/debug/clk/clk_summary.
> > > It seems that the pd of PCIe controller is not up properly.
> > > More investigation is still on-going.
> >
> > Just to check the obvious things: you've put the controller into the
> > IMX8MP_HSIOBLK_PD_PCIE and the PHY into
> IMX8MP_HSIOBLK_PD_PCIE_PHY,
> > right?
> >
> > If the PHY access works then the power-domains should be powered up
> > properly, as the PHY domain is nested inside the HSIO domain where the
> > controller is located according to my information. So the most likely
> > reason is still a clock path that isn't fully turned on.
> Hi Lucas:
> Thanks for your reply.
> Yes, I had put the controller into the IMX8MP_HSIOBLK_PD_PCIE.
> And the PHY into IMX8MP_HSIOBLK_PD_PCIE_PHY.
> Your assumption is reasonable, I would do more debug on the clock.
> Thanks.
>
> Best Regards
> Richard Zhu
>
Hi Lucas:
Find the root cause, it's caused by one missing reset configurations.
I would summit one reset patch when bring up the i.MX8MP PCIe patches later.
i.MX8MP PCIe works fine after add one more reset patch.
Thanks.
Tested-by: Richard Zhu <hongxing.zhu@nxp.com>
Best Regards
Richard Zhu
> >
> > Regards,
> > Lucas
> >
> > > BTW, the access of PHY register is successful.
> > >
> > > Best Regards
> > > Richard Zhu
> > >
> > > > > > ---
> > > > > > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 71
> > > > > > +++++++++++++++++++++--
> > > > > > 1 file changed, 65 insertions(+), 6 deletions(-)
> > > > > >
> > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > index 6b840c05dd77..69e533add539 100644
> > > > > > --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> > > > > > @@ -4,6 +4,7 @@
> > > > > > */
> > > > > >
> > > > > > #include <dt-bindings/clock/imx8mp-clock.h>
> > > > > > +#include <dt-bindings/power/imx8mp-power.h>
> > > > > > #include <dt-bindings/gpio/gpio.h>
> > > > > > #include <dt-bindings/input/input.h> #include
> > > > > > <dt-bindings/interrupt-controller/arm-gic.h>
> > > > > > @@ -475,6 +476,44 @@ src: reset-controller@30390000 {
> > > > > > interrupts = <GIC_SPI 89
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > #reset-cells = <1>;
> > > > > > };
> > > > > > +
> > > > > > + gpc: gpc@303a0000 {
> > > > > > + compatible = "fsl,imx8mp-gpc";
> > > > > > + reg = <0x303a0000 0x1000>;
> > > > > > + interrupt-parent = <&gic>;
> > > > > > + interrupt-controller;
> > > > > > + #interrupt-cells = <3>;
> > > > > > +
> > > > > > + pgc {
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <0>;
> > > > > > +
> > > > > > + pgc_pcie_phy: power-
> > > > > > domain@1 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_usb1_phy: power-
> > > > > > domain@2 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_USB1_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_usb2_phy: power-
> > > > > > domain@3 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_USB2_PHY>;
> > > > > > + };
> > > > > > +
> > > > > > + pgc_hsiomix:
> > > > > > power-domains@17 {
> > > > > > + #power-domain-
> > > > > > cells = <0>;
> > > > > > + reg =
> > > > > > <IMX8MP_POWER_DOMAIN_HSIOMIX>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>,
> > > > > > + <&clk
> > > > > > IMX8MP_CLK_HSIO_ROOT>;
> > > > > > + assigned-
> > > > > > clocks = <&clk
> > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > + assigned-
> > > > > > clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > + assigned-
> > > > > > clock-rates = <500000000>;
> > > > > > + };
> > > > > > + };
> > > > > > + };
> > > > > > };
> > > > > >
> > > > > > aips2: bus@30400000 {
> > > > > > @@ -892,6 +931,28 @@ eqos: ethernet@30bf0000 {
> > > > > > };
> > > > > > };
> > > > > >
> > > > > > + aips4 {
> > > > >
> > > > > I think this should be
> > > > >
> > > > > aips4: bus@32c00000 {
> > > > >
> > > > > to match the other buses. Apart from that, the patch looks good,
> > > > > my Rb tag still applies.
> > > >
> > > > Urgh, apparently one shouldn't do those reworks too late in the
> > > > evening. :/
> > > >
> > > > Shawn, would you be willing to fix this up while applying, or
> > > > should I resend the series?
> > > >
> > > > Regards,
> > > > Lucas
> > > >
> > > > >
> > > > > > + compatible = "fsl,aips-bus", "simple-
> > > > > > bus";
> > > > > > + reg = <0x32c00000 0x400000>;
> > > > > > + #address-cells = <1>;
> > > > > > + #size-cells = <1>;
> > > > > > + ranges;
> > > > > > +
> > > > > > + hsio_blk_ctrl: blk-ctrl@32f10000 {
> > > > > > + compatible = "fsl,imx8mp-hsio-
> > > > > > blk-ctrl", "syscon";
> > > > > > + reg = <0x32f10000 0x24>;
> > > > > > + clocks = <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>,
> > > > > > + <&clk
> > > > > > IMX8MP_CLK_PCIE_ROOT>;
> > > > > > + clock-names = "usb", "pcie";
> > > > > > + power-domains =
> > > > > > <&pgc_hsiomix>, <&pgc_hsiomix>,
> > > > > > + <&pgc_usb1_phy
> > > > > > >, <&pgc_usb2_phy>,
> > > > > > + <&pgc_hsiomix>
> > > > > > , <&pgc_pcie_phy>;
> > > > > > + power-domain-names = "bus",
> > > > > > "usb", "usb-phy1",
> > > > > > + "usb-
> > > > > > phy2", "pcie", "pcie-phy";
> > > > > > + #power-domain-cells = <1>;
> > > > > > + };
> > > > > > + };
> > > > > > +
> > > > > > gic: interrupt-controller@38800000 {
> > > > > > compatible = "arm,gic-v3";
> > > > > > reg = <0x38800000 0x10000>, @@ -915,6 +976,7
> @@ usb3_phy0:
> > > > > > usb-phy@381f0040 {
> > > > > > clock-names = "phy";
> > > > > > assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB_PHY1>;
> > > > > > #phy-cells = <0>;
> > > > > > status = "disabled";
> > > > > > };
> > > > > > @@ -926,6 +988,7 @@ usb3_0: usb@32f10100 {
> > > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "hsio", "suspend";
> > > > > > interrupts = <GIC_SPI 148
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > #address-cells = <1>;
> > > > > > #size-cells = <1>;
> > > > > > dma-ranges = <0x40000000 0x40000000
> > > > > > 0xc0000000>;
> > > > @@ -939,9
> > > > > > +1002,6 @@ usb_dwc3_0: usb@38100000 {
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "bus_early", "ref", "suspend";
> > > > > > - assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > - assigned-clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > - assigned-clock-rates =
> > > > > > <500000000>;
> > > > > > interrupts = <GIC_SPI 40
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > phys = <&usb3_phy0>,
> > > > > > <&usb3_phy0>;
> > > > > > phy-names = "usb2-phy", "usb3- phy"; @@
> -957,6
> > > > +1017,7 @@
> > > > > > usb3_phy1: usb-phy@382f0040 {
> > > > > > clock-names = "phy";
> > > > > > assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_USB_PHY_REF>;
> > > > > > assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > IMX8MP_HSIOBLK_PD_USB_PHY2>;
> > > > > > #phy-cells = <0>;
> > > > > > };
> > > > > >
> > > > > > @@ -967,6 +1028,7 @@ usb3_1: usb@32f10108 {
> > > > > > <&clk IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "hsio", "suspend";
> > > > > > interrupts = <GIC_SPI 149
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > + power-domains = <&hsio_blk_ctrl
> > > > > > IMX8MP_HSIOBLK_PD_USB>;
> > > > > > #address-cells = <1>;
> > > > > > #size-cells = <1>;
> > > > > > dma-ranges = <0x40000000 0x40000000
> > > > > > 0xc0000000>;
> > > > @@ -980,9
> > > > > > +1042,6 @@ usb_dwc3_1: usb@38200000 {
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_CORE_REF>,
> > > > > > <&clk
> > > > > > IMX8MP_CLK_USB_ROOT>;
> > > > > > clock-names = "bus_early", "ref", "suspend";
> > > > > > - assigned-clocks = <&clk
> > > > > > IMX8MP_CLK_HSIO_AXI>;
> > > > > > - assigned-clock-parents = <&clk
> > > > IMX8MP_SYS_PLL2_500M>;
> > > > > > - assigned-clock-rates =
> > > > > > <500000000>;
> > > > > > interrupts = <GIC_SPI 41
> > > > > > IRQ_TYPE_LEVEL_HIGH>;
> > > > > > phys = <&usb3_phy1>,
> > > > > > <&usb3_phy1>;
> > > > > > phy-names = "usb2-phy", "usb3- phy";
> > > > >
> > > >
> > >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
2022-02-28 20:17 ` Lucas Stach
@ 2022-03-10 12:07 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-10 12:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Lucas Stach, Rob Herring, Pengutronix Kernel Team,
NXP Linux Team, Marek Vasut, devicetree, linux-arm-kernel,
patchwork-lst
Hi Shawn,
Is there still a chance this could get merged in v5.18 ?
On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> Hi all,
>
> third and hopefully last revision of this patchset. The dt-binding
> patches are dropped, as Shawn already picked them up. I fixed up all
> the review comments received by Laurent and Marek.
>
> Regards,
> Lucas
>
> Lucas Stach (7):
> soc: imx: gpcv2: add PGC control register indirection
> soc: imx: gpcv2: add support for i.MX8MP power domains
> soc: imx: add i.MX8MP HSIO blk-ctrl
> dt-bindings: usb: dwc3-imx8mp: add power domain property
> arm64: dts: imx8mp: add HSIO power-domains
> arm64: dts: imx8mp: add GPU power domains
> arm64: dts: imx8mp: add GPU nodes
>
> .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> drivers/soc/imx/Makefile | 1 +
> drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> 5 files changed, 994 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
@ 2022-03-10 12:07 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-10 12:07 UTC (permalink / raw)
To: Shawn Guo
Cc: Lucas Stach, Rob Herring, Pengutronix Kernel Team,
NXP Linux Team, Marek Vasut, devicetree, linux-arm-kernel,
patchwork-lst
Hi Shawn,
Is there still a chance this could get merged in v5.18 ?
On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> Hi all,
>
> third and hopefully last revision of this patchset. The dt-binding
> patches are dropped, as Shawn already picked them up. I fixed up all
> the review comments received by Laurent and Marek.
>
> Regards,
> Lucas
>
> Lucas Stach (7):
> soc: imx: gpcv2: add PGC control register indirection
> soc: imx: gpcv2: add support for i.MX8MP power domains
> soc: imx: add i.MX8MP HSIO blk-ctrl
> dt-bindings: usb: dwc3-imx8mp: add power domain property
> arm64: dts: imx8mp: add HSIO power-domains
> arm64: dts: imx8mp: add GPU power domains
> arm64: dts: imx8mp: add GPU nodes
>
> .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> drivers/soc/imx/Makefile | 1 +
> drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> 5 files changed, 994 insertions(+), 18 deletions(-)
> create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
2022-03-10 12:07 ` Laurent Pinchart
@ 2022-03-14 15:31 ` Laurent Pinchart
-1 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-14 15:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Lucas Stach, Rob Herring, Pengutronix Kernel Team,
NXP Linux Team, Marek Vasut, devicetree, linux-arm-kernel,
patchwork-lst
On Thu, Mar 10, 2022 at 02:07:32PM +0200, Laurent Pinchart wrote:
> Hi Shawn,
>
> Is there still a chance this could get merged in v5.18 ?
Ping ? Time is running out.
> On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> > Hi all,
> >
> > third and hopefully last revision of this patchset. The dt-binding
> > patches are dropped, as Shawn already picked them up. I fixed up all
> > the review comments received by Laurent and Marek.
> >
> > Regards,
> > Lucas
> >
> > Lucas Stach (7):
> > soc: imx: gpcv2: add PGC control register indirection
> > soc: imx: gpcv2: add support for i.MX8MP power domains
> > soc: imx: add i.MX8MP HSIO blk-ctrl
> > dt-bindings: usb: dwc3-imx8mp: add power domain property
> > arm64: dts: imx8mp: add HSIO power-domains
> > arm64: dts: imx8mp: add GPU power domains
> > arm64: dts: imx8mp: add GPU nodes
> >
> > .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> > drivers/soc/imx/Makefile | 1 +
> > drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> > drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> > 5 files changed, 994 insertions(+), 18 deletions(-)
> > create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl
@ 2022-03-14 15:31 ` Laurent Pinchart
0 siblings, 0 replies; 48+ messages in thread
From: Laurent Pinchart @ 2022-03-14 15:31 UTC (permalink / raw)
To: Shawn Guo
Cc: Lucas Stach, Rob Herring, Pengutronix Kernel Team,
NXP Linux Team, Marek Vasut, devicetree, linux-arm-kernel,
patchwork-lst
On Thu, Mar 10, 2022 at 02:07:32PM +0200, Laurent Pinchart wrote:
> Hi Shawn,
>
> Is there still a chance this could get merged in v5.18 ?
Ping ? Time is running out.
> On Mon, Feb 28, 2022 at 09:17:24PM +0100, Lucas Stach wrote:
> > Hi all,
> >
> > third and hopefully last revision of this patchset. The dt-binding
> > patches are dropped, as Shawn already picked them up. I fixed up all
> > the review comments received by Laurent and Marek.
> >
> > Regards,
> > Lucas
> >
> > Lucas Stach (7):
> > soc: imx: gpcv2: add PGC control register indirection
> > soc: imx: gpcv2: add support for i.MX8MP power domains
> > soc: imx: add i.MX8MP HSIO blk-ctrl
> > dt-bindings: usb: dwc3-imx8mp: add power domain property
> > arm64: dts: imx8mp: add HSIO power-domains
> > arm64: dts: imx8mp: add GPU power domains
> > arm64: dts: imx8mp: add GPU nodes
> >
> > .../bindings/usb/fsl,imx8mp-dwc3.yaml | 6 +
> > arch/arm64/boot/dts/freescale/imx8mp.dtsi | 129 ++++-
> > drivers/soc/imx/Makefile | 1 +
> > drivers/soc/imx/gpcv2.c | 430 ++++++++++++++++-
> > drivers/soc/imx/imx8mp-blk-ctrl.c | 446 ++++++++++++++++++
> > 5 files changed, 994 insertions(+), 18 deletions(-)
> > create mode 100644 drivers/soc/imx/imx8mp-blk-ctrl.c
--
Regards,
Laurent Pinchart
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
2022-03-02 17:39 ` Rob Herring
@ 2022-06-22 14:16 ` Lucas Stach
-1 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-06-22 14:16 UTC (permalink / raw)
To: Rob Herring
Cc: Marek Vasut, devicetree, patchwork-lst, NXP Linux Team,
Pengutronix Kernel Team, Shawn Guo, linux-arm-kernel,
Laurent Pinchart
Am Mittwoch, dem 02.03.2022 um 11:39 -0600 schrieb Rob Herring:
> On Mon, Feb 28, 2022 at 09:17:28PM +0100, Lucas Stach wrote:
> > The USB controllers in the i.MX8MP are located inside the HSIO
> > power domain. Add the power-domains property to the DT binding
> > to be able to describe the hardware properly.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Acked-by: Rob Herring <robh@kernel.org>
>
This patch hasn't landed anywhere, yet.
Rob, can you take it directly, or should I resend to go trough the
USB(?) tree?
Regards,
Lucas
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property
@ 2022-06-22 14:16 ` Lucas Stach
0 siblings, 0 replies; 48+ messages in thread
From: Lucas Stach @ 2022-06-22 14:16 UTC (permalink / raw)
To: Rob Herring
Cc: Marek Vasut, devicetree, patchwork-lst, NXP Linux Team,
Pengutronix Kernel Team, Shawn Guo, linux-arm-kernel,
Laurent Pinchart
Am Mittwoch, dem 02.03.2022 um 11:39 -0600 schrieb Rob Herring:
> On Mon, Feb 28, 2022 at 09:17:28PM +0100, Lucas Stach wrote:
> > The USB controllers in the i.MX8MP are located inside the HSIO
> > power domain. Add the power-domains property to the DT binding
> > to be able to describe the hardware properly.
> >
> > Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> > ---
> > Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml | 6 ++++++
> > 1 file changed, 6 insertions(+)
>
> Acked-by: Rob Herring <robh@kernel.org>
>
This patch hasn't landed anywhere, yet.
Rob, can you take it directly, or should I resend to go trough the
USB(?) tree?
Regards,
Lucas
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^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-06-22 14:17 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-02-28 20:17 [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-02-28 20:17 ` [PATCH v3 1/7] soc: imx: gpcv2: add PGC control register indirection Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-02-28 20:34 ` Laurent Pinchart
2022-02-28 20:34 ` Laurent Pinchart
2022-02-28 20:17 ` [PATCH v3 2/7] soc: imx: gpcv2: add support for i.MX8MP power domains Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-02-28 20:37 ` Laurent Pinchart
2022-02-28 20:37 ` Laurent Pinchart
2022-02-28 20:17 ` [PATCH v3 3/7] soc: imx: add i.MX8MP HSIO blk-ctrl Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-02-28 20:17 ` [PATCH v3 4/7] dt-bindings: usb: dwc3-imx8mp: add power domain property Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-03-02 17:39 ` Rob Herring
2022-03-02 17:39 ` Rob Herring
2022-06-22 14:16 ` Lucas Stach
2022-06-22 14:16 ` Lucas Stach
2022-02-28 20:17 ` [PATCH v3 5/7] arm64: dts: imx8mp: add HSIO power-domains Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-03-01 7:13 ` Laurent Pinchart
2022-03-01 7:13 ` Laurent Pinchart
2022-03-01 9:09 ` Lucas Stach
2022-03-01 9:09 ` Lucas Stach
2022-03-02 8:47 ` Hongxing Zhu
2022-03-02 8:47 ` Hongxing Zhu
2022-03-02 9:18 ` Lucas Stach
2022-03-02 9:18 ` Lucas Stach
2022-03-02 11:29 ` Jun Li
2022-03-02 11:29 ` Jun Li
2022-03-03 2:22 ` Hongxing Zhu
2022-03-03 2:22 ` Hongxing Zhu
2022-03-03 4:08 ` Hongxing Zhu
2022-03-03 4:08 ` Hongxing Zhu
2022-03-02 16:49 ` (EXT) " Alexander Stein
2022-03-02 16:49 ` Alexander Stein
2022-02-28 20:17 ` [PATCH v3 6/7] arm64: dts: imx8mp: add GPU power domains Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-02-28 20:17 ` [PATCH v3 7/7] arm64: dts: imx8mp: add GPU nodes Lucas Stach
2022-02-28 20:17 ` Lucas Stach
2022-03-02 16:49 ` (EXT) " Alexander Stein
2022-03-02 16:49 ` Alexander Stein
2022-02-28 21:10 ` [PATCH v3 0/7] i.MX8MP GPC and blk-ctrl Laurent Pinchart
2022-02-28 21:10 ` Laurent Pinchart
2022-03-10 12:07 ` Laurent Pinchart
2022-03-10 12:07 ` Laurent Pinchart
2022-03-14 15:31 ` Laurent Pinchart
2022-03-14 15:31 ` Laurent Pinchart
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