* [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema
@ 2022-04-05 6:34 Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with " Krzysztof Kozlowski
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
Hi,
Changes since v3
================
1. Correct dmas in serial/UART bindings example.
2. Use "const" in compatible for GSBI.
3. Add review tags.
Changes since v2
================
1. Several new schema patches (GSBI, I2C and UART schema).
2. Several DTS fixes for clocks and DMAs. The choice of dma tx-rx
and clocks core-iface was by more-or-less number of fixes needed.
3. Add Kuldeep acks to patches without changes.
Changes since v1
================
1. Fix path in com/qcom,gsbi.txt.
2. Merge clock-names in example, correct $ref path (Kuldeep).
Merging
=======
1. The DTS patches are independent and silence warnings pointed
out by schema.
2. The DT schema patches should be taken together as GSBI (final patch)
depends on previous bindings.
Best regards,
Krzysztof
Cc: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Krzysztof Kozlowski (9):
arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
arm64: dts: qcom: align clocks in I2C/SPI with DT schema
ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema
ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema
ARM: dts: qcom: msm8660: disable GSBI8
spi: dt-bindings: qcom,spi-qup: convert to dtschema
dt-bindings: serial: qcom,msm-uartdm: convert to dtschema
dt-bindings: i2c: qcom,i2c-qup: convert to dtschema
dt-bindings: qcom: qcom,gsbi: convert to dtschema
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 ------
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 89 ++++++++++++
.../bindings/serial/qcom,msm-uartdm.txt | 81 -----------
.../bindings/serial/qcom,msm-uartdm.yaml | 112 +++++++++++++++
.../bindings/soc/qcom/qcom,gsbi.txt | 87 ------------
.../bindings/soc/qcom/qcom,gsbi.yaml | 132 ++++++++++++++++++
.../devicetree/bindings/spi/qcom,spi-qup.txt | 103 --------------
.../devicetree/bindings/spi/qcom,spi-qup.yaml | 81 +++++++++++
arch/arm/boot/dts/qcom-ipq4019.dtsi | 36 ++---
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 20 +--
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 40 +++---
arch/arm64/boot/dts/qcom/msm8916.dtsi | 68 ++++-----
arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++----
arch/arm64/boot/dts/qcom/msm8994.dtsi | 42 +++---
arch/arm64/boot/dts/qcom/msm8996.dtsi | 36 ++---
arch/arm64/boot/dts/qcom/qcs404.dtsi | 92 ++++++------
17 files changed, 606 insertions(+), 502 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml
delete mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml
delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
--
2.32.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v4 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 2/9] arm64: dts: qcom: align clocks in I2C/SPI " Krzysztof Kozlowski
` (8 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
The DT schema expects dma channels in tx-rx order. No functional
change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Dropped Kuldeep's ack because of changes - more properties changed.
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 8 +++----
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 16 +++++++-------
arch/arm64/boot/dts/qcom/msm8916.dtsi | 32 +++++++++++++--------------
arch/arm64/boot/dts/qcom/qcs404.dtsi | 20 ++++++++---------
4 files changed, 38 insertions(+), 38 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index aac56575e30d..87c28ffa44d3 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -322,8 +322,8 @@ i2c_0: i2c@78b6000 {
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -337,8 +337,8 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
+ dma-names = "tx", "rx";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index d80b1cefab10..2072638006a4 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -471,8 +471,8 @@ blsp1_i2c2: i2c@78b6000 {
<&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-0 = <&i2c_0_pins>;
pinctrl-names = "default";
status = "disabled";
@@ -488,8 +488,8 @@ blsp1_i2c3: i2c@78b7000 {
<&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
- dmas = <&blsp_dma 17>, <&blsp_dma 16>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 16>, <&blsp_dma 17>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -503,8 +503,8 @@ blsp1_i2c5: i2c@78b9000 {
<&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <400000>;
- dmas = <&blsp_dma 21>, <&blsp_dma 20>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 20>, <&blsp_dma 21>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -518,8 +518,8 @@ blsp1_i2c6: i2c@78ba000 {
<&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
clock-names = "iface", "core";
clock-frequency = <100000>;
- dmas = <&blsp_dma 23>, <&blsp_dma 22>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 22>, <&blsp_dma 23>;
+ dma-names = "tx", "rx";
status = "disabled";
};
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index e34963505e07..384fc8738130 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1485,8 +1485,8 @@ blsp1_uart1: serial@78af000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart1_default>;
pinctrl-1 = <&blsp1_uart1_sleep>;
@@ -1499,8 +1499,8 @@ blsp1_uart2: serial@78b0000 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_uart2_default>;
pinctrl-1 = <&blsp1_uart2_sleep>;
@@ -1529,8 +1529,8 @@ blsp_spi1: spi@78b5000 {
clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 5>, <&blsp_dma 4>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi1_default>;
pinctrl-1 = <&spi1_sleep>;
@@ -1561,8 +1561,8 @@ blsp_spi2: spi@78b6000 {
clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 7>, <&blsp_dma 6>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi2_default>;
pinctrl-1 = <&spi2_sleep>;
@@ -1593,8 +1593,8 @@ blsp_spi3: spi@78b7000 {
clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 9>, <&blsp_dma 8>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi3_default>;
pinctrl-1 = <&spi3_sleep>;
@@ -1625,8 +1625,8 @@ blsp_spi4: spi@78b8000 {
clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 11>, <&blsp_dma 10>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi4_default>;
pinctrl-1 = <&spi4_sleep>;
@@ -1657,8 +1657,8 @@ blsp_spi5: spi@78b9000 {
clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 13>, <&blsp_dma 12>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 12>, <&blsp_dma 13>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi5_default>;
pinctrl-1 = <&spi5_sleep>;
@@ -1689,8 +1689,8 @@ blsp_spi6: spi@78ba000 {
clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 15>, <&blsp_dma 14>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 14>, <&blsp_dma 15>;
+ dma-names = "tx", "rx";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&spi6_default>;
pinctrl-1 = <&spi6_sleep>;
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 3f06f7cd3cf2..6b3a8e1006d0 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -823,8 +823,8 @@ blsp1_uart0: serial@78af000 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp1_dma 1>, <&blsp1_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp1_dma 0>, <&blsp1_dma 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart0_default>;
status = "disabled";
@@ -836,8 +836,8 @@ blsp1_uart1: serial@78b0000 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp1_dma 3>, <&blsp1_dma 2>;
- dma-names = "rx", "tx";
+ dmas = <&blsp1_dma 2>, <&blsp1_dma 3>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart1_default>;
status = "disabled";
@@ -849,8 +849,8 @@ blsp1_uart2: serial@78b1000 {
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp1_dma 5>, <&blsp1_dma 4>;
- dma-names = "rx", "tx";
+ dmas = <&blsp1_dma 4>, <&blsp1_dma 5>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart2_default>;
status = "okay";
@@ -903,8 +903,8 @@ blsp1_uart3: serial@78b2000 {
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp1_dma 7>, <&blsp1_dma 6>;
- dma-names = "rx", "tx";
+ dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_uart3_default>;
status = "disabled";
@@ -1067,8 +1067,8 @@ blsp2_uart0: serial@7aef000 {
interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp2_dma 1>, <&blsp2_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp2_dma 0>, <&blsp2_dma 1>;
+ dma-names = "tx", "rx";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_uart0_default>;
status = "disabled";
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 2/9] arm64: dts: qcom: align clocks in I2C/SPI with DT schema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 3/9] ARM: dts: qcom: ipq4019: align dmas in SPI/UART " Krzysztof Kozlowski
` (7 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
The DT schema expects clocks core-iface order. No functional change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Dropped Kuldeep's ack because of changes - more properties changed.
---
arch/arm64/boot/dts/qcom/ipq6018.dtsi | 12 ++---
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 24 ++++-----
arch/arm64/boot/dts/qcom/msm8916.dtsi | 36 +++++++-------
arch/arm64/boot/dts/qcom/msm8953.dtsi | 48 +++++++++---------
arch/arm64/boot/dts/qcom/msm8994.dtsi | 42 ++++++++--------
arch/arm64/boot/dts/qcom/msm8996.dtsi | 36 +++++++-------
arch/arm64/boot/dts/qcom/qcs404.dtsi | 72 +++++++++++++--------------
7 files changed, 135 insertions(+), 135 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index 87c28ffa44d3..8032d7933c66 100644
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -318,9 +318,9 @@ i2c_0: i2c@78b6000 {
#size-cells = <0>;
reg = <0x0 0x078b6000 0x0 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
@@ -333,9 +333,9 @@ i2c_1: i2c@78b7000 { /* BLSP1 QUP2 */
#size-cells = <0>;
reg = <0x0 0x078b7000 0x0 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
index 2072638006a4..8e41c910b8f9 100644
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
@@ -467,9 +467,9 @@ blsp1_i2c2: i2c@78b6000 {
#size-cells = <0>;
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 14>, <&blsp_dma 15>;
dma-names = "tx", "rx";
@@ -484,9 +484,9 @@ blsp1_i2c3: i2c@78b7000 {
#size-cells = <0>;
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 16>, <&blsp_dma 17>;
dma-names = "tx", "rx";
@@ -499,9 +499,9 @@ blsp1_i2c5: i2c@78b9000 {
#size-cells = <0>;
reg = <0x78b9000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp_dma 20>, <&blsp_dma 21>;
dma-names = "tx", "rx";
@@ -514,9 +514,9 @@ blsp1_i2c6: i2c@78ba000 {
#size-cells = <0>;
reg = <0x078ba000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <100000>;
dmas = <&blsp_dma 22>, <&blsp_dma 23>;
dma-names = "tx", "rx";
diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi
index 384fc8738130..15d9731469ca 100644
--- a/arch/arm64/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi
@@ -1511,9 +1511,9 @@ blsp_i2c1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c1_default>;
pinctrl-1 = <&i2c1_sleep>;
@@ -1543,9 +1543,9 @@ blsp_i2c2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c2_default>;
pinctrl-1 = <&i2c2_sleep>;
@@ -1575,9 +1575,9 @@ blsp_i2c3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x500>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c3_default>;
pinctrl-1 = <&i2c3_sleep>;
@@ -1607,9 +1607,9 @@ blsp_i2c4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c4_default>;
pinctrl-1 = <&i2c4_sleep>;
@@ -1639,9 +1639,9 @@ blsp_i2c5: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c5_default>;
pinctrl-1 = <&i2c5_sleep>;
@@ -1671,9 +1671,9 @@ blsp_i2c6: i2c@78ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078ba000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c6_default>;
pinctrl-1 = <&i2c6_sleep>;
diff --git a/arch/arm64/boot/dts/qcom/msm8953.dtsi b/arch/arm64/boot/dts/qcom/msm8953.dtsi
index 431228faacdd..2a70263a701d 100644
--- a/arch/arm64/boot/dts/qcom/msm8953.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8953.dtsi
@@ -923,9 +923,9 @@ i2c_1: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_1_default>;
@@ -941,9 +941,9 @@ i2c_2: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_2_default>;
@@ -959,9 +959,9 @@ i2c_3: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_3_default>;
pinctrl-1 = <&i2c_3_sleep>;
@@ -976,9 +976,9 @@ i2c_4: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_4_default>;
pinctrl-1 = <&i2c_4_sleep>;
@@ -993,9 +993,9 @@ i2c_5: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_5_default>;
pinctrl-1 = <&i2c_5_sleep>;
@@ -1010,9 +1010,9 @@ i2c_6: i2c@7af6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af6000 0x600>;
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_6_default>;
pinctrl-1 = <&i2c_6_sleep>;
@@ -1027,9 +1027,9 @@ i2c_7: i2c@7af7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af7000 0x600>;
interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_7_default>;
pinctrl-1 = <&i2c_7_sleep>;
@@ -1044,9 +1044,9 @@ i2c_8: i2c@7af8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x7af8000 0x600>;
interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
- clock-names = "iface", "core";
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>;
+ clock-names = "core", "iface";
+ clocks = <&gcc GCC_BLSP2_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&i2c_8_default>;
pinctrl-1 = <&i2c_8_sleep>;
diff --git a/arch/arm64/boot/dts/qcom/msm8994.dtsi b/arch/arm64/boot/dts/qcom/msm8994.dtsi
index 8c1dc5155b71..209f9ef030e5 100644
--- a/arch/arm64/boot/dts/qcom/msm8994.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8994.dtsi
@@ -519,9 +519,9 @@ blsp1_i2c1: i2c@f9923000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9923000 0x500>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
dma-names = "tx", "rx";
@@ -555,9 +555,9 @@ blsp1_i2c2: i2c@f9924000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9924000 0x500>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 14>, <&blsp1_dma 15>;
dma-names = "tx", "rx";
@@ -575,9 +575,9 @@ blsp1_i2c4: i2c@f9926000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9926000 0x500>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 18>, <&blsp1_dma 19>;
dma-names = "tx", "rx";
@@ -593,9 +593,9 @@ blsp1_i2c5: i2c@f9927000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9927000 0x500>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
@@ -611,9 +611,9 @@ blsp1_i2c6: i2c@f9928000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9928000 0x500>;
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp1_dma 22>, <&blsp1_dma 23>;
dma-names = "tx", "rx";
@@ -657,9 +657,9 @@ blsp2_i2c1: i2c@f9963000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9963000 0x500>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
dmas = <&blsp2_dma 12>, <&blsp2_dma 13>;
dma-names = "tx", "rx";
@@ -693,9 +693,9 @@ blsp2_i2c5: i2c@f9967000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0xf9967000 0x500>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <355000>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
dma-names = "tx", "rx";
diff --git a/arch/arm64/boot/dts/qcom/msm8996.dtsi b/arch/arm64/boot/dts/qcom/msm8996.dtsi
index f0f81c23c16f..dc77880e8927 100644
--- a/arch/arm64/boot/dts/qcom/msm8996.dtsi
+++ b/arch/arm64/boot/dts/qcom/msm8996.dtsi
@@ -2786,9 +2786,9 @@ blsp1_i2c3: i2c@7577000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07577000 0x1000>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp1_i2c3_default>;
pinctrl-1 = <&blsp1_i2c3_sleep>;
@@ -2834,9 +2834,9 @@ blsp2_i2c1: i2c@75b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b5000 0x1000>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c1_default>;
pinctrl-1 = <&blsp2_i2c1_sleep>;
@@ -2851,9 +2851,9 @@ blsp2_i2c2: i2c@75b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b6000 0x1000>;
interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c2_default>;
pinctrl-1 = <&blsp2_i2c2_sleep>;
@@ -2868,9 +2868,9 @@ blsp2_i2c3: i2c@75b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x075b7000 0x1000>;
interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
clock-frequency = <400000>;
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c3_default>;
@@ -2886,9 +2886,9 @@ blsp2_i2c5: i2c@75b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75b9000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP5_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c5_default>;
dmas = <&blsp2_dma 20>, <&blsp2_dma 21>;
@@ -2902,9 +2902,9 @@ blsp2_i2c6: i2c@75ba000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x75ba000 0x1000>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default", "sleep";
pinctrl-0 = <&blsp2_i2c6_default>;
pinctrl-1 = <&blsp2_i2c6_sleep>;
diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi
index 6b3a8e1006d0..acf120f91b42 100644
--- a/arch/arm64/boot/dts/qcom/qcs404.dtsi
+++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi
@@ -914,9 +914,9 @@ blsp1_i2c0: i2c@78b5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c0_default>;
#address-cells = <1>;
@@ -928,9 +928,9 @@ blsp1_spi0: spi@78b5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b5000 0x600>;
interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi0_default>;
#address-cells = <1>;
@@ -942,9 +942,9 @@ blsp1_i2c1: i2c@78b6000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c1_default>;
#address-cells = <1>;
@@ -956,9 +956,9 @@ blsp1_spi1: spi@78b6000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b6000 0x600>;
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi1_default>;
#address-cells = <1>;
@@ -970,9 +970,9 @@ blsp1_i2c2: i2c@78b7000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c2_default>;
#address-cells = <1>;
@@ -984,9 +984,9 @@ blsp1_spi2: spi@78b7000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi2_default>;
#address-cells = <1>;
@@ -998,9 +998,9 @@ blsp1_i2c3: i2c@78b8000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c3_default>;
#address-cells = <1>;
@@ -1012,9 +1012,9 @@ blsp1_spi3: spi@78b8000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi3_default>;
#address-cells = <1>;
@@ -1026,9 +1026,9 @@ blsp1_i2c4: i2c@78b9000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_i2c4_default>;
#address-cells = <1>;
@@ -1040,9 +1040,9 @@ blsp1_spi4: spi@78b9000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x078b9000 0x600>;
interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp1_spi4_default>;
#address-cells = <1>;
@@ -1078,9 +1078,9 @@ blsp2_i2c0: i2c@7af5000 {
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_i2c0_default>;
#address-cells = <1>;
@@ -1092,9 +1092,9 @@ blsp2_spi0: spi@7af5000 {
compatible = "qcom,spi-qup-v2.2.1";
reg = <0x07af5000 0x600>;
interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP2_AHB_CLK>,
- <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP2_AHB_CLK>;
+ clock-names = "core", "iface";
pinctrl-names = "default";
pinctrl-0 = <&blsp2_spi0_default>;
#address-cells = <1>;
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 3/9] ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with " Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 2/9] arm64: dts: qcom: align clocks in I2C/SPI " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 4/9] ARM: dts: qcom: ipq4019: align clocks in I2C " Krzysztof Kozlowski
` (6 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
The DT schema expects dma channels in tx-rx order. No functional
change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Dropped Kuldeep's ack because of changes - more properties changed.
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index a9d0566a3190..1f6c4ab7f37e 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -253,8 +253,8 @@ blsp1_spi1: spi@78b5000 { /* BLSP1 QUP1 */
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 5>, <&blsp_dma 4>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 4>, <&blsp_dma 5>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -267,8 +267,8 @@ blsp1_spi2: spi@78b6000 { /* BLSP1 QUP2 */
clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 7>, <&blsp_dma 6>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 6>, <&blsp_dma 7>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -281,8 +281,8 @@ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 9>, <&blsp_dma 8>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 8>, <&blsp_dma 9>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -295,8 +295,8 @@ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
clock-names = "iface", "core";
#address-cells = <1>;
#size-cells = <0>;
- dmas = <&blsp_dma 11>, <&blsp_dma 10>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 10>, <&blsp_dma 11>;
+ dma-names = "tx", "rx";
status = "disabled";
};
@@ -382,8 +382,8 @@ blsp1_uart1: serial@78af000 {
clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 1>, <&blsp_dma 0>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 0>, <&blsp_dma 1>;
+ dma-names = "tx", "rx";
};
blsp1_uart2: serial@78b0000 {
@@ -394,8 +394,8 @@ blsp1_uart2: serial@78b0000 {
clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
<&gcc GCC_BLSP1_AHB_CLK>;
clock-names = "core", "iface";
- dmas = <&blsp_dma 3>, <&blsp_dma 2>;
- dma-names = "rx", "tx";
+ dmas = <&blsp_dma 2>, <&blsp_dma 3>;
+ dma-names = "tx", "rx";
};
watchdog: watchdog@b017000 {
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 4/9] ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (2 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 3/9] ARM: dts: qcom: ipq4019: align dmas in SPI/UART " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 5/9] ARM: dts: qcom: msm8660: disable GSBI8 Krzysztof Kozlowski
` (5 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
The DT schema expects clocks core-iface order. No functional change.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom-ipq4019.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi
index 1f6c4ab7f37e..897442157f5f 100644
--- a/arch/arm/boot/dts/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi
@@ -276,9 +276,9 @@ blsp1_i2c3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b7000 0x600>;
interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 8>, <&blsp_dma 9>;
@@ -290,9 +290,9 @@ blsp1_i2c4: i2c@78b8000 { /* BLSP1 QUP4 */
compatible = "qcom,i2c-qup-v2.2.1";
reg = <0x78b8000 0x600>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&gcc GCC_BLSP1_AHB_CLK>,
- <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
- clock-names = "iface", "core";
+ clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
#address-cells = <1>;
#size-cells = <0>;
dmas = <&blsp_dma 10>, <&blsp_dma 11>;
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 5/9] ARM: dts: qcom: msm8660: disable GSBI8
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (3 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 4/9] ARM: dts: qcom: ipq4019: align clocks in I2C " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema Krzysztof Kozlowski
` (4 subsequent siblings)
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
The GSBI8 child node (I2C controller) is disabled, so as parent GSBI
node should be the same.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
arch/arm/boot/dts/qcom-msm8660.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/boot/dts/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom-msm8660.dtsi
index a258abb23a64..47b97daecef1 100644
--- a/arch/arm/boot/dts/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom-msm8660.dtsi
@@ -212,6 +212,7 @@ gsbi8: gsbi@19800000 {
ranges;
syscon-tcsr = <&tcsr>;
+ status = "disabled";
gsbi8_i2c: i2c@19880000 {
compatible = "qcom,i2c-qup-v1.1.1";
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (4 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 5/9] ARM: dts: qcom: msm8660: disable GSBI8 Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-05 8:34 ` Mark Brown
2022-04-05 6:34 ` [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: " Krzysztof Kozlowski
` (3 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski, Rob Herring
Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral
Interface (SPI) bindings to DT Schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Kuldeep Singh <singh.kuldeep87k@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/spi/qcom,spi-qup.txt | 103 ------------------
.../devicetree/bindings/spi/qcom,spi-qup.yaml | 81 ++++++++++++++
2 files changed, 81 insertions(+), 103 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
create mode 100644 Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt b/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
deleted file mode 100644
index 5c090771c016..000000000000
--- a/Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
+++ /dev/null
@@ -1,103 +0,0 @@
-Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
-
-The QUP core is an AHB slave that provides a common data path (an output FIFO
-and an input FIFO) for serial peripheral interface (SPI) mini-core.
-
-SPI in master mode supports up to 50MHz, up to four chip selects, programmable
-data path from 4 bits to 32 bits and numerous protocol variants.
-
-Required properties:
-- compatible: Should contain:
- "qcom,spi-qup-v1.1.1" for 8660, 8960 and 8064.
- "qcom,spi-qup-v2.1.1" for 8974 and later
- "qcom,spi-qup-v2.2.1" for 8974 v2 and later.
-
-- reg: Should contain base register location and length
-- interrupts: Interrupt number used by this controller
-
-- clocks: Should contain the core clock and the AHB clock.
-- clock-names: Should be "core" for the core clock and "iface" for the
- AHB clock.
-
-- #address-cells: Number of cells required to define a chip select
- address on the SPI bus. Should be set to 1.
-- #size-cells: Should be zero.
-
-Optional properties:
-- spi-max-frequency: Specifies maximum SPI clock frequency,
- Units - Hz. Definition as per
- Documentation/devicetree/bindings/spi/spi-bus.txt
-- num-cs: total number of chipselects
-- cs-gpios: should specify GPIOs used for chipselects.
- The gpios will be referred to as reg = <index> in the SPI child
- nodes. If unspecified, a single SPI device without a chip
- select can be used.
-
-- dmas: Two DMA channel specifiers following the convention outlined
- in bindings/dma/dma.txt
-- dma-names: Names for the dma channels, if present. There must be at
- least one channel named "tx" for transmit and named "rx" for
- receive.
-
-SPI slave nodes must be children of the SPI master node and can contain
-properties described in Documentation/devicetree/bindings/spi/spi-bus.txt
-
-Example:
-
- spi_8: spi@f9964000 { /* BLSP2 QUP2 */
-
- compatible = "qcom,spi-qup-v2";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0xf9964000 0x1000>;
- interrupts = <0 102 0>;
- spi-max-frequency = <19200000>;
-
- clocks = <&gcc GCC_BLSP2_QUP2_SPI_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
- clock-names = "core", "iface";
-
- dmas = <&blsp1_bam 13>, <&blsp1_bam 12>;
- dma-names = "rx", "tx";
-
- pinctrl-names = "default";
- pinctrl-0 = <&spi8_default>;
-
- device@0 {
- compatible = "arm,pl022-dummy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>; /* Chip select 0 */
- spi-max-frequency = <19200000>;
- spi-cpol;
- };
-
- device@1 {
- compatible = "arm,pl022-dummy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <1>; /* Chip select 1 */
- spi-max-frequency = <9600000>;
- spi-cpha;
- };
-
- device@2 {
- compatible = "arm,pl022-dummy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <2>; /* Chip select 2 */
- spi-max-frequency = <19200000>;
- spi-cpol;
- spi-cpha;
- };
-
- device@3 {
- compatible = "arm,pl022-dummy";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <3>; /* Chip select 3 */
- spi-max-frequency = <19200000>;
- spi-cpol;
- spi-cpha;
- spi-cs-high;
- };
- };
diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
new file mode 100644
index 000000000000..93f14dd01afc
--- /dev/null
+++ b/Documentation/devicetree/bindings/spi/qcom,spi-qup.yaml
@@ -0,0 +1,81 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/spi/qcom,spi-qup.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Peripheral (QUP) Serial Peripheral Interface (SPI)
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The QUP core is an AHB slave that provides a common data path (an output FIFO
+ and an input FIFO) for serial peripheral interface (SPI) mini-core.
+
+ SPI in master mode supports up to 50MHz, up to four chip selects,
+ programmable data path from 4 bits to 32 bits and numerous protocol variants.
+
+allOf:
+ - $ref: /schemas/spi/spi-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,spi-qup-v1.1.1 # for 8660, 8960 and 8064
+ - qcom,spi-qup-v2.1.1 # for 8974 and later
+ - qcom,spi-qup-v2.2.1 # for 8974 v2 and later
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - interrupts
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8996.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ spi@7575000 {
+ compatible = "qcom,spi-qup-v2.2.1";
+ reg = <0x07575000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_spi1_default>;
+ pinctrl-1 = <&blsp1_spi1_sleep>;
+ dmas = <&blsp1_dma 12>, <&blsp1_dma 13>;
+ dma-names = "tx", "rx";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: convert to dtschema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (5 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-06 18:09 ` Rob Herring
2022-04-05 6:34 ` [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: " Krzysztof Kozlowski
` (2 subsequent siblings)
9 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski
Convert the Qualcomm MSM Serial UARTDM bindings to DT Schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../bindings/serial/qcom,msm-uartdm.txt | 81 -------------
.../bindings/serial/qcom,msm-uartdm.yaml | 112 ++++++++++++++++++
2 files changed, 112 insertions(+), 81 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
deleted file mode 100644
index 9d098cf73b53..000000000000
--- a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
+++ /dev/null
@@ -1,81 +0,0 @@
-* MSM Serial UARTDM
-
-The MSM serial UARTDM hardware is designed for high-speed use cases where the
-transmit and/or receive channels can be offloaded to a dma-engine. From a
-software perspective it's mostly compatible with the MSM serial UART except
-that it supports reading and writing multiple characters at a time.
-
-Required properties:
-- compatible: Should contain at least "qcom,msm-uartdm".
- A more specific property should be specified as follows depending
- on the version:
- "qcom,msm-uartdm-v1.1"
- "qcom,msm-uartdm-v1.2"
- "qcom,msm-uartdm-v1.3"
- "qcom,msm-uartdm-v1.4"
-- reg: Should contain UART register locations and lengths. The first
- register shall specify the main control registers. An optional second
- register location shall specify the GSBI control region.
- "qcom,msm-uartdm-v1.3" is the only compatible value that might
- need the GSBI control region.
-- interrupts: Should contain UART interrupt.
-- clocks: Should contain the core clock and the AHB clock.
-- clock-names: Should be "core" for the core clock and "iface" for the
- AHB clock.
-
-Optional properties:
-- dmas: Should contain dma specifiers for transmit and receive channels
-- dma-names: Should contain "tx" for transmit and "rx" for receive channels
-- qcom,tx-crci: Identificator <u32> for Client Rate Control Interface to be
- used with TX DMA channel. Required when using DMA for transmission
- with UARTDM v1.3 and below.
-- qcom,rx-crci: Identificator <u32> for Client Rate Control Interface to be
- used with RX DMA channel. Required when using DMA for reception
- with UARTDM v1.3 and below.
-
-Note: Aliases may be defined to ensure the correct ordering of the UARTs.
-The alias serialN will result in the UART being assigned port N. If any
-serialN alias exists, then an alias must exist for each enabled UART. The
-serialN aliases should be in a .dts file instead of in a .dtsi file.
-
-Examples:
-
-- A uartdm v1.4 device with dma capabilities.
-
- serial@f991e000 {
- compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
- reg = <0xf991e000 0x1000>;
- interrupts = <0 108 0x0>;
- clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
- clock-names = "core", "iface";
- dmas = <&dma0 0>, <&dma0 1>;
- dma-names = "tx", "rx";
- };
-
-- A uartdm v1.3 device without dma capabilities and part of a GSBI complex.
-
- serial@19c40000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x19c40000 0x1000>,
- <0x19c00000 0x1000>;
- interrupts = <0 195 0x0>;
- clocks = <&gsbi5_uart_cxc>, <&gsbi5_ahb_cxc>;
- clock-names = "core", "iface";
- };
-
-- serialN alias.
-
- aliases {
- serial0 = &uarta;
- serial1 = &uartc;
- serial2 = &uartb;
- };
-
- uarta: serial@12490000 {
- };
-
- uartb: serial@16340000 {
- };
-
- uartc: serial@1a240000 {
- };
diff --git a/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
new file mode 100644
index 000000000000..484b9a51f6a9
--- /dev/null
+++ b/Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
@@ -0,0 +1,112 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm MSM Serial UARTDM
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description: |
+ The MSM serial UARTDM hardware is designed for high-speed use cases where the
+ transmit and/or receive channels can be offloaded to a dma-engine. From a
+ software perspective it's mostly compatible with the MSM serial UART except
+ that it supports reading and writing multiple characters at a time.
+
+ Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
+ The alias serialN will result in the UART being assigned port N. If any
+ serialN alias exists, then an alias must exist for each enabled UART. The
+ serialN aliases should be in a .dts file instead of in a .dtsi file.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qcom,msm-uartdm-v1.1
+ - qcom,msm-uartdm-v1.2
+ - qcom,msm-uartdm-v1.3
+ - qcom,msm-uartdm-v1.4
+ - const: qcom,msm-uartdm
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ maxItems: 1
+
+ qcom,rx-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Identificator for Client Rate Control Interface to be used with RX DMA
+ channel. Required when using DMA for reception with UARTDM v1.3 and
+ below.
+
+ qcom,tx-crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ Identificator for Client Rate Control Interface to be used with TX DMA
+ channel. Required when using DMA for transmission with UARTDM v1.3 and
+ below.
+
+ reg:
+ minItems: 1
+ items:
+ - description: Main control registers
+ - description: An optional second register location shall specify the GSBI control region.
+
+required:
+ - compatible
+ - clock-names
+ - clocks
+ - interrupts
+ - reg
+
+unevaluatedProperties: false
+
+allOf:
+ - $ref: /schemas/serial/serial.yaml#
+
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,msm-uartdm-v1.3
+ then:
+ properties:
+ reg:
+ minItems: 2
+ else:
+ properties:
+ reg:
+ maxItems: 1
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ serial@f991e000 {
+ compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
+ reg = <0xf991e000 0x1000>;
+ interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
+ clock-names = "core", "iface";
+ dmas = <&dma0 0>, <&dma0 1>;
+ dma-names = "tx", "rx";
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: convert to dtschema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (6 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-15 21:10 ` Wolfram Sang
2022-04-05 6:34 ` [PATCH v4 9/9] dt-bindings: qcom: qcom,gsbi: " Krzysztof Kozlowski
2022-04-07 17:46 ` [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Rob Herring
9 siblings, 1 reply; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski, Rob Herring
Convert the Qualcomm Universal Peripheral (QUP) I2C controller to DT
Schema.
Add missing properties: dma and dma-names, pinctrl states (to indicate
support for sleep pinctrl).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../devicetree/bindings/i2c/qcom,i2c-qup.txt | 40 ---------
.../devicetree/bindings/i2c/qcom,i2c-qup.yaml | 89 +++++++++++++++++++
2 files changed, 89 insertions(+), 40 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
create mode 100644 Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
deleted file mode 100644
index dc71754a56af..000000000000
--- a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-Qualcomm Universal Peripheral (QUP) I2C controller
-
-Required properties:
- - compatible: Should be:
- * "qcom,i2c-qup-v1.1.1" for 8660, 8960 and 8064.
- * "qcom,i2c-qup-v2.1.1" for 8974 v1.
- * "qcom,i2c-qup-v2.2.1" for 8974 v2 and later.
- - reg: Should contain QUP register address and length.
- - interrupts: Should contain I2C interrupt.
-
- - clocks: A list of phandles + clock-specifiers, one for each entry in
- clock-names.
- - clock-names: Should contain:
- * "core" for the core clock
- * "iface" for the AHB clock
-
- - #address-cells: Should be <1> Address cells for i2c device address
- - #size-cells: Should be <0> as i2c addresses have no size component
-
-Optional properties:
- - clock-frequency: Should specify the desired i2c bus clock frequency in Hz,
- defaults to 100kHz if omitted.
-
-Child nodes should conform to i2c bus binding.
-
-Example:
-
- i2c@f9924000 {
- compatible = "qcom,i2c-qup-v2.2.1";
- reg = <0xf9924000 0x1000>;
- interrupts = <0 96 0>;
-
- clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
- clock-names = "core", "iface";
-
- clock-frequency = <355000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
- };
diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml
new file mode 100644
index 000000000000..f43947514d48
--- /dev/null
+++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-qup.yaml
@@ -0,0 +1,89 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/i2c/qcom,i2c-qup.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Universal Peripheral (QUP) I2C controller
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+allOf:
+ - $ref: /schemas/i2c/i2c-controller.yaml#
+
+properties:
+ compatible:
+ enum:
+ - qcom,i2c-qup-v1.1.1 # for 8660, 8960 and 8064
+ - qcom,i2c-qup-v2.1.1 # for 8974 v1
+ - qcom,i2c-qup-v2.2.1 # for 8974 v2 and later
+
+ clocks:
+ maxItems: 2
+
+ clock-names:
+ items:
+ - const: core
+ - const: iface
+
+ clock-frequency:
+ default: 100000
+
+ dmas:
+ maxItems: 2
+
+ dma-names:
+ items:
+ - const: tx
+ - const: rx
+
+ interrupts:
+ maxItems: 1
+
+ pinctrl-0: true
+ pinctrl-1: true
+
+ pinctrl-names:
+ minItems: 1
+ items:
+ - const: default
+ - const: sleep
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - clock-names
+ - clocks
+ - interrupts
+ - reg
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8998.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+
+ i2c@c175000 {
+ compatible = "qcom,i2c-qup-v2.2.1";
+ reg = <0x0c175000 0x600>;
+ interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
+ <&gcc GCC_BLSP1_AHB_CLK>;
+ clock-names = "core", "iface";
+ dmas = <&blsp1_dma 6>, <&blsp1_dma 7>;
+ dma-names = "tx", "rx";
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&blsp1_i2c1_default>;
+ pinctrl-1 = <&blsp1_i2c1_sleep>;
+ clock-frequency = <400000>;
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v4 9/9] dt-bindings: qcom: qcom,gsbi: convert to dtschema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (7 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: " Krzysztof Kozlowski
@ 2022-04-05 6:34 ` Krzysztof Kozlowski
2022-04-07 17:46 ` [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Rob Herring
9 siblings, 0 replies; 14+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-05 6:34 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi
Cc: Kuldeep Singh, Krzysztof Kozlowski, Rob Herring
Convert the Qualcomm General Serial Bus Interface (GSBI) to DT
Schema.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
---
.../bindings/soc/qcom/qcom,gsbi.txt | 87 ------------
.../bindings/soc/qcom/qcom,gsbi.yaml | 132 ++++++++++++++++++
2 files changed, 132 insertions(+), 87 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
deleted file mode 100644
index fe1855f09dcc..000000000000
--- a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.txt
+++ /dev/null
@@ -1,87 +0,0 @@
-QCOM GSBI (General Serial Bus Interface) Driver
-
-The GSBI controller is modeled as a node with zero or more child nodes, each
-representing a serial sub-node device that is mux'd as part of the GSBI
-configuration settings. The mode setting will govern the input/output mode of
-the 4 GSBI IOs.
-
-Required properties:
-- compatible: Should contain "qcom,gsbi-v1.0.0"
-- cell-index: Should contain the GSBI index
-- reg: Address range for GSBI registers
-- clocks: required clock
-- clock-names: must contain "iface" entry
-- qcom,mode : indicates MUX value for configuration of the serial interface.
- Please reference dt-bindings/soc/qcom,gsbi.h for valid mux values.
-
-Optional properties:
-- qcom,crci : indicates CRCI MUX value for QUP CRCI ports. Please reference
- dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
-- syscon-tcsr: indicates phandle of TCSR syscon node. Required if child uses
- dma.
-
-Required properties if child node exists:
-- #address-cells: Must be 1
-- #size-cells: Must be 1
-- ranges: Must be present
-
-Properties for children:
-
-A GSBI controller node can contain 0 or more child nodes representing serial
-devices. These serial devices can be a QCOM UART, I2C controller, spi
-controller, or some combination of aforementioned devices.
-
-See the following for child node definitions:
-Documentation/devicetree/bindings/i2c/qcom,i2c-qup.txt
-Documentation/devicetree/bindings/spi/qcom,spi-qup.txt
-Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
-
-Example for APQ8064:
-
-#include <dt-bindings/soc/qcom,gsbi.h>
-
- gsbi4@16300000 {
- compatible = "qcom,gsbi-v1.0.0";
- cell-index = <4>;
- reg = <0x16300000 0x100>;
- clocks = <&gcc GSBI4_H_CLK>;
- clock-names = "iface";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- qcom,mode = <GSBI_PROT_I2C_UART>;
- qcom,crci = <GSBI_CRCI_QUP>;
-
- syscon-tcsr = <&tcsr>;
-
- /* child nodes go under here */
-
- i2c_qup4: i2c@16380000 {
- compatible = "qcom,i2c-qup-v1.1.1";
- reg = <0x16380000 0x1000>;
- interrupts = <0 153 0>;
-
- clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
- clock-names = "core", "iface";
-
- clock-frequency = <200000>;
-
- #address-cells = <1>;
- #size-cells = <0>;
-
- };
-
- uart4: serial@16340000 {
- compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
- reg = <0x16340000 0x1000>,
- <0x16300000 0x1000>;
- interrupts = <0 152 0x0>;
- clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
- clock-names = "core", "iface";
- };
- };
-
- tcsr: syscon@1a400000 {
- compatible = "qcom,apq8064-tcsr", "syscon";
- reg = <0x1a400000 0x100>;
- };
diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml
new file mode 100644
index 000000000000..c33704333e49
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/qcom/qcom,gsbi.yaml
@@ -0,0 +1,132 @@
+# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm General Serial Bus Interface (GSBI)
+
+maintainers:
+ - Andy Gross <agross@kernel.org>
+ - Bjorn Andersson <bjorn.andersson@linaro.org>
+ - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+
+description:
+ The GSBI controller is modeled as a node with zero or more child nodes, each
+ representing a serial sub-node device that is mux'd as part of the GSBI
+ configuration settings. The mode setting will govern the input/output mode
+ of the 4 GSBI IOs.
+
+ A GSBI controller node can contain 0 or more child nodes representing serial
+ devices. These serial devices can be a QCOM UART, I2C controller, spi
+ controller, or some combination of aforementioned devices.
+
+properties:
+ compatible:
+ const: qcom,gsbi-v1.0.0
+
+ '#address-cells':
+ const: 1
+
+ cell-index:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ The GSBI index.
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ const: iface
+
+ qcom,crci:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ CRCI MUX value for QUP CRCI ports. Please reference
+ include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values.
+
+ qcom,mode:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ description:
+ MUX value for configuration of the serial interface. Please reference
+ include/dt-bindings/soc/qcom,gsbi.h for valid mux values.
+
+ '#size-cells':
+ const: 1
+
+ syscon-tcsr:
+ $ref: /schemas/types.yaml#/definitions/phandle
+ description:
+ Phandle of TCSR syscon node.Required if child uses dma.
+
+ ranges: true
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "spi@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/spi/qcom,spi-qup.yaml#
+
+ "i2c@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/i2c/qcom,i2c-qup.yaml#
+
+ "serial@[0-9a-f]+$":
+ type: object
+ $ref: /schemas/serial/qcom,msm-uartdm.yaml#
+
+required:
+ - compatible
+ - cell-index
+ - clocks
+ - clock-names
+ - qcom,mode
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-msm8960.h>
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
+
+ gsbi@12440000 {
+ compatible = "qcom,gsbi-v1.0.0";
+ reg = <0x12440000 0x100>;
+ cell-index = <1>;
+ clocks = <&gcc GSBI1_H_CLK>;
+ clock-names = "iface";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ syscon-tcsr = <&tcsr>;
+ qcom,mode = <GSBI_PROT_I2C_UART>;
+
+ serial@12450000 {
+ compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
+ reg = <0x12450000 0x100>,
+ <0x12400000 0x03>;
+ interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ };
+
+ i2c@12460000 {
+ compatible = "qcom,i2c-qup-v1.1.1";
+ reg = <0x12460000 0x1000>;
+ pinctrl-0 = <&i2c1_pins>;
+ pinctrl-1 = <&i2c1_pins_sleep>;
+ pinctrl-names = "default", "sleep";
+ interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
+ clock-names = "core", "iface";
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled"; /* UART chosen */
+ };
+ };
--
2.32.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema
2022-04-05 6:34 ` [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema Krzysztof Kozlowski
@ 2022-04-05 8:34 ` Mark Brown
0 siblings, 0 replies; 14+ messages in thread
From: Mark Brown @ 2022-04-05 8:34 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, linux-arm-msm, linux-i2c, devicetree,
linux-kernel, linux-serial, linux-spi, Kuldeep Singh,
Rob Herring
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On Tue, Apr 05, 2022 at 08:34:48AM +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm Universal Peripheral (QUP) Serial Peripheral
> Interface (SPI) bindings to DT Schema.
Acked-by: Mark Brown <broonie@kernel.org>
[-- Attachment #2: signature.asc --]
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^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: convert to dtschema
2022-04-05 6:34 ` [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: " Krzysztof Kozlowski
@ 2022-04-06 18:09 ` Rob Herring
0 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2022-04-06 18:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: linux-i2c, devicetree, linux-arm-msm, Kuldeep Singh, Andy Gross,
Mark Brown, Greg Kroah-Hartman, Krzysztof Kozlowski,
linux-serial, Bjorn Andersson, Rob Herring, linux-kernel,
linux-spi
On Tue, 05 Apr 2022 08:34:49 +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm MSM Serial UARTDM bindings to DT Schema.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
> .../bindings/serial/qcom,msm-uartdm.txt | 81 -------------
> .../bindings/serial/qcom,msm-uartdm.yaml | 112 ++++++++++++++++++
> 2 files changed, 112 insertions(+), 81 deletions(-)
> delete mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.txt
> create mode 100644 Documentation/devicetree/bindings/serial/qcom,msm-uartdm.yaml
>
Reviewed-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
` (8 preceding siblings ...)
2022-04-05 6:34 ` [PATCH v4 9/9] dt-bindings: qcom: qcom,gsbi: " Krzysztof Kozlowski
@ 2022-04-07 17:46 ` Rob Herring
9 siblings, 0 replies; 14+ messages in thread
From: Rob Herring @ 2022-04-07 17:46 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi, Kuldeep Singh
On Tue, Apr 05, 2022 at 08:34:42AM +0200, Krzysztof Kozlowski wrote:
> Hi,
>
> Changes since v3
> ================
> 1. Correct dmas in serial/UART bindings example.
> 2. Use "const" in compatible for GSBI.
> 3. Add review tags.
>
> Changes since v2
> ================
> 1. Several new schema patches (GSBI, I2C and UART schema).
> 2. Several DTS fixes for clocks and DMAs. The choice of dma tx-rx
> and clocks core-iface was by more-or-less number of fixes needed.
> 3. Add Kuldeep acks to patches without changes.
>
> Changes since v1
> ================
> 1. Fix path in com/qcom,gsbi.txt.
> 2. Merge clock-names in example, correct $ref path (Kuldeep).
>
> Merging
> =======
> 1. The DTS patches are independent and silence warnings pointed
> out by schema.
>
> 2. The DT schema patches should be taken together as GSBI (final patch)
> depends on previous bindings.
>
> Best regards,
> Krzysztof
>
> Cc: Kuldeep Singh <singh.kuldeep87k@gmail.com>
>
> Krzysztof Kozlowski (9):
> arm64: dts: qcom: align dmas in I2C/SPI/UART with DT schema
> arm64: dts: qcom: align clocks in I2C/SPI with DT schema
> ARM: dts: qcom: ipq4019: align dmas in SPI/UART with DT schema
> ARM: dts: qcom: ipq4019: align clocks in I2C with DT schema
> ARM: dts: qcom: msm8660: disable GSBI8
> spi: dt-bindings: qcom,spi-qup: convert to dtschema
> dt-bindings: serial: qcom,msm-uartdm: convert to dtschema
> dt-bindings: i2c: qcom,i2c-qup: convert to dtschema
> dt-bindings: qcom: qcom,gsbi: convert to dtschema
Patches 6-9 applied.
Rob
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: convert to dtschema
2022-04-05 6:34 ` [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: " Krzysztof Kozlowski
@ 2022-04-15 21:10 ` Wolfram Sang
0 siblings, 0 replies; 14+ messages in thread
From: Wolfram Sang @ 2022-04-15 21:10 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski,
Greg Kroah-Hartman, Mark Brown, linux-arm-msm, linux-i2c,
devicetree, linux-kernel, linux-serial, linux-spi, Kuldeep Singh,
Rob Herring
[-- Attachment #1: Type: text/plain, Size: 417 bytes --]
On Tue, Apr 05, 2022 at 08:34:50AM +0200, Krzysztof Kozlowski wrote:
> Convert the Qualcomm Universal Peripheral (QUP) I2C controller to DT
> Schema.
>
> Add missing properties: dma and dma-names, pinctrl states (to indicate
> support for sleep pinctrl).
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Reviewed-by: Rob Herring <robh@kernel.org>
Applied to for-next, thanks!
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^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-04-15 21:10 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-05 6:34 [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 1/9] arm64: dts: qcom: align dmas in I2C/SPI/UART with " Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 2/9] arm64: dts: qcom: align clocks in I2C/SPI " Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 3/9] ARM: dts: qcom: ipq4019: align dmas in SPI/UART " Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 4/9] ARM: dts: qcom: ipq4019: align clocks in I2C " Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 5/9] ARM: dts: qcom: msm8660: disable GSBI8 Krzysztof Kozlowski
2022-04-05 6:34 ` [PATCH v4 6/9] spi: dt-bindings: qcom,spi-qup: convert to dtschema Krzysztof Kozlowski
2022-04-05 8:34 ` Mark Brown
2022-04-05 6:34 ` [PATCH v4 7/9] dt-bindings: serial: qcom,msm-uartdm: " Krzysztof Kozlowski
2022-04-06 18:09 ` Rob Herring
2022-04-05 6:34 ` [PATCH v4 8/9] dt-bindings: i2c: qcom,i2c-qup: " Krzysztof Kozlowski
2022-04-15 21:10 ` Wolfram Sang
2022-04-05 6:34 ` [PATCH v4 9/9] dt-bindings: qcom: qcom,gsbi: " Krzysztof Kozlowski
2022-04-07 17:46 ` [PATCH v4 0/9] dt-bindings: qcom: convert entire GSBI (QUP I2C/SPI/UART) to DT schema Rob Herring
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