* [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The Display SubSystem IP on the ti's am65x soc has an additional
register space "common1" and services a maximum of 2 interrupts.
The first patch in the series adds the required updates to the yaml
file. The second patch then reflects the yaml updates in the DSS DT
node of am65x soc.
Aradhya Bhatia (2):
dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
2 files changed, 11 insertions(+), 5 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The Display SubSystem IP on the ti's am65x soc has an additional
register space "common1" and services a maximum of 2 interrupts.
The first patch in the series adds the required updates to the yaml
file. The second patch then reflects the yaml updates in the DSS DT
node of am65x soc.
Aradhya Bhatia (2):
dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
2 files changed, 11 insertions(+), 5 deletions(-)
--
2.35.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: Devicetree, Aradhya Bhatia, Linux Kernel, DRI Development,
Nikhil Devshatwar, Linux ARM Kernel
The Display SubSystem IP on the ti's am65x soc has an additional
register space "common1" and services a maximum of 2 interrupts.
The first patch in the series adds the required updates to the yaml
file. The second patch then reflects the yaml updates in the DSS DT
node of am65x soc.
Aradhya Bhatia (2):
dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
2 files changed, 11 insertions(+), 5 deletions(-)
--
2.35.3
^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 7:03 ` Aradhya Bhatia
-1 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The DSS IP on the ti-am65x soc supports an additional register space,
named "common1". Further. the IP services a maximum number of 2
interrupts.
Add the missing register space "common1" and the additional interrupt.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 5c7d2cbc4aac..102059e9e0d5 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -26,6 +26,7 @@ properties:
Addresses to each DSS memory region described in the SoC's TRM.
items:
- description: common DSS register area
+ - description: common1 DSS register area
- description: VIDL1 light video plane
- description: VID video plane
- description: OVR1 overlay manager for vp1
@@ -36,6 +37,7 @@ properties:
reg-names:
items:
- const: common
+ - const: common1
- const: vidl1
- const: vid
- const: ovr1
@@ -64,7 +66,7 @@ properties:
maxItems: 3
interrupts:
- maxItems: 1
+ maxItems: 2
power-domains:
maxItems: 1
@@ -122,13 +124,14 @@ examples:
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x04a00000 0x1000>, /* common */
+ reg = <0x04a01000 0x1000>, /* common1 */
<0x04a02000 0x1000>, /* vidl1 */
<0x04a06000 0x1000>, /* vid */
<0x04a07000 0x1000>, /* ovr1 */
<0x04a08000 0x1000>, /* ovr2 */
<0x04a0a000 0x1000>, /* vp1 */
<0x04a0b000 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1". "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
@@ -136,7 +139,8 @@ examples:
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.3
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/2] dt-bindings: display: ti, am65x-dss: Add missing register & interrupt
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: Devicetree, Aradhya Bhatia, Linux Kernel, DRI Development,
Nikhil Devshatwar, Linux ARM Kernel
The DSS IP on the ti-am65x soc supports an additional register space,
named "common1". Further. the IP services a maximum number of 2
interrupts.
Add the missing register space "common1" and the additional interrupt.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 5c7d2cbc4aac..102059e9e0d5 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -26,6 +26,7 @@ properties:
Addresses to each DSS memory region described in the SoC's TRM.
items:
- description: common DSS register area
+ - description: common1 DSS register area
- description: VIDL1 light video plane
- description: VID video plane
- description: OVR1 overlay manager for vp1
@@ -36,6 +37,7 @@ properties:
reg-names:
items:
- const: common
+ - const: common1
- const: vidl1
- const: vid
- const: ovr1
@@ -64,7 +66,7 @@ properties:
maxItems: 3
interrupts:
- maxItems: 1
+ maxItems: 2
power-domains:
maxItems: 1
@@ -122,13 +124,14 @@ examples:
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x04a00000 0x1000>, /* common */
+ reg = <0x04a01000 0x1000>, /* common1 */
<0x04a02000 0x1000>, /* vidl1 */
<0x04a06000 0x1000>, /* vid */
<0x04a07000 0x1000>, /* ovr1 */
<0x04a08000 0x1000>, /* ovr2 */
<0x04a0a000 0x1000>, /* vp1 */
<0x04a0b000 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1". "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
@@ -136,7 +139,8 @@ examples:
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.3
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 1/2] dt-bindings: display: ti, am65x-dss: Add missing register & interrupt
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The DSS IP on the ti-am65x soc supports an additional register space,
named "common1". Further. the IP services a maximum number of 2
interrupts.
Add the missing register space "common1" and the additional interrupt.
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
.../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
index 5c7d2cbc4aac..102059e9e0d5 100644
--- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
+++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
@@ -26,6 +26,7 @@ properties:
Addresses to each DSS memory region described in the SoC's TRM.
items:
- description: common DSS register area
+ - description: common1 DSS register area
- description: VIDL1 light video plane
- description: VID video plane
- description: OVR1 overlay manager for vp1
@@ -36,6 +37,7 @@ properties:
reg-names:
items:
- const: common
+ - const: common1
- const: vidl1
- const: vid
- const: ovr1
@@ -64,7 +66,7 @@ properties:
maxItems: 3
interrupts:
- maxItems: 1
+ maxItems: 2
power-domains:
maxItems: 1
@@ -122,13 +124,14 @@ examples:
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x04a00000 0x1000>, /* common */
+ reg = <0x04a01000 0x1000>, /* common1 */
<0x04a02000 0x1000>, /* vidl1 */
<0x04a06000 0x1000>, /* vid */
<0x04a07000 0x1000>, /* ovr1 */
<0x04a08000 0x1000>, /* ovr2 */
<0x04a0a000 0x1000>, /* vp1 */
<0x04a0b000 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1". "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
@@ -136,7 +139,8 @@ examples:
<&k3_clks 216 1>,
<&k3_clks 67 2>;
clock-names = "fck", "vp1", "vp2";
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
ports {
#address-cells = <1>;
#size-cells = <0>;
--
2.35.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 7:03 ` Aradhya Bhatia
-1 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: Devicetree, Aradhya Bhatia, Linux Kernel, DRI Development,
Nikhil Devshatwar, Linux ARM Kernel
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
@ 2022-04-19 7:03 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 7:03 UTC (permalink / raw)
To: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar, Aradhya Bhatia
The DSS IP on the ti-am65x soc supports an additional register space
named "common1". Further, it services a maximum of 2 interrupts.
Add the missing register space "common1" and the additional interrupt in
the dss DT node .
Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
---
arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
index e749343acced..1bafa3a98e71 100644
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -830,13 +830,14 @@ csi2_0: port@0 {
dss: dss@4a00000 {
compatible = "ti,am65x-dss";
reg = <0x0 0x04a00000 0x0 0x1000>, /* common */
+ <0x0 0x04a01000 0x0 0x1000>, /* common1 */
<0x0 0x04a02000 0x0 0x1000>, /* vidl1 */
<0x0 0x04a06000 0x0 0x1000>, /* vid */
<0x0 0x04a07000 0x0 0x1000>, /* ovr1 */
<0x0 0x04a08000 0x0 0x1000>, /* ovr2 */
<0x0 0x04a0a000 0x0 0x1000>, /* vp1 */
<0x0 0x04a0b000 0x0 0x1000>; /* vp2 */
- reg-names = "common", "vidl1", "vid",
+ reg-names = "common", "common1", "vidl1", "vid",
"ovr1", "ovr2", "vp1", "vp2";
ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
@@ -856,7 +857,8 @@ dss: dss@4a00000 {
assigned-clocks = <&k3_clks 67 2>;
assigned-clock-parents = <&k3_clks 67 5>;
- interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
+ <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
dma-coherent;
--
2.35.3
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 12:06 ` Tomi Valkeinen
-1 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-19 12:06 UTC (permalink / raw)
To: Aradhya Bhatia, Jyri Sarha, Vignesh Raghavendra, Nishanth Menon
Cc: Devicetree, Nikhil Devshatwar, Linux ARM Kernel, DRI Development,
Linux Kernel
On 19/04/2022 10:03, Aradhya Bhatia wrote:
> The Display SubSystem IP on the ti's am65x soc has an additional
> register space "common1" and services a maximum of 2 interrupts.
>
> The first patch in the series adds the required updates to the yaml
> file. The second patch then reflects the yaml updates in the DSS DT
> node of am65x soc.
>
> Aradhya Bhatia (2):
> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
How are you planning to use the common1 area?
Tomi
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 12:06 ` Tomi Valkeinen
0 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-19 12:06 UTC (permalink / raw)
To: Aradhya Bhatia, Jyri Sarha, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar
On 19/04/2022 10:03, Aradhya Bhatia wrote:
> The Display SubSystem IP on the ti's am65x soc has an additional
> register space "common1" and services a maximum of 2 interrupts.
>
> The first patch in the series adds the required updates to the yaml
> file. The second patch then reflects the yaml updates in the DSS DT
> node of am65x soc.
>
> Aradhya Bhatia (2):
> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
How are you planning to use the common1 area?
Tomi
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 12:06 ` Tomi Valkeinen
0 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-19 12:06 UTC (permalink / raw)
To: Aradhya Bhatia, Jyri Sarha, Vignesh Raghavendra, Nishanth Menon
Cc: DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar
On 19/04/2022 10:03, Aradhya Bhatia wrote:
> The Display SubSystem IP on the ti's am65x soc has an additional
> register space "common1" and services a maximum of 2 interrupts.
>
> The first patch in the series adds the required updates to the yaml
> file. The second patch then reflects the yaml updates in the DSS DT
> node of am65x soc.
>
> Aradhya Bhatia (2):
> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
> 2 files changed, 11 insertions(+), 5 deletions(-)
>
Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
How are you planning to use the common1 area?
Tomi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti, am65x-dss: Add missing register & interrupt
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 12:12 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 12:12 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Nishanth Menon, Devicetree, Vignesh Raghavendra, Tomi Valkeinen,
Linux Kernel, DRI Development, Jyri Sarha, Nikhil Devshatwar,
Linux ARM Kernel
On Tue, 19 Apr 2022 12:33:01 +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dts:30.17-18 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-19 12:12 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 12:12 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: DRI Development, Linux ARM Kernel, Linux Kernel, Tomi Valkeinen,
Nishanth Menon, Vignesh Raghavendra, Nikhil Devshatwar,
Jyri Sarha, Devicetree
On Tue, 19 Apr 2022 12:33:01 +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dts:30.17-18 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti, am65x-dss: Add missing register & interrupt
@ 2022-04-19 12:12 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 12:12 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: DRI Development, Linux ARM Kernel, Linux Kernel, Tomi Valkeinen,
Nishanth Menon, Vignesh Raghavendra, Nikhil Devshatwar,
Jyri Sarha, Devicetree
On Tue, 19 Apr 2022 12:33:01 +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):
yamllint warnings/errors:
dtschema/dtc warnings/errors:
Error: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dts:30.17-18 syntax error
FATAL ERROR: Unable to parse input tree
make[1]: *** [scripts/Makefile.lib:364: Documentation/devicetree/bindings/display/ti/ti,am65x-dss.example.dtb] Error 1
make[1]: *** Waiting for unfinished jobs....
make: *** [Makefile:1401: dt_binding_check] Error 2
doc reference errors (make refcheckdocs):
See https://patchwork.ozlabs.org/patch/
This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:
pip3 install dtschema --upgrade
Please check and re-submit.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 12:40 ` Nishanth Menon
-1 siblings, 0 replies; 30+ messages in thread
From: Nishanth Menon @ 2022-04-19 12:40 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar
On 12:33-20220419, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
What are the interrupts supposed to be?
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-19 12:40 ` Nishanth Menon
0 siblings, 0 replies; 30+ messages in thread
From: Nishanth Menon @ 2022-04-19 12:40 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Devicetree, Vignesh Raghavendra, Tomi Valkeinen, Linux Kernel,
DRI Development, Jyri Sarha, Nikhil Devshatwar, Linux ARM Kernel
On 12:33-20220419, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
What are the interrupts supposed to be?
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-19 12:40 ` Nishanth Menon
0 siblings, 0 replies; 30+ messages in thread
From: Nishanth Menon @ 2022-04-19 12:40 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar
On 12:33-20220419, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
What are the interrupts supposed to be?
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
2022-04-19 7:03 ` Aradhya Bhatia
(?)
@ 2022-04-19 14:20 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 14:20 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon,
DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar
On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
You've just broken the ABI.
New entries have to go on the end.
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
Once there is more than 1, we need to know what each entry is and the
order.
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-19 14:20 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 14:20 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Nishanth Menon, Devicetree, Vignesh Raghavendra, Tomi Valkeinen,
Linux Kernel, DRI Development, Jyri Sarha, Nikhil Devshatwar,
Linux ARM Kernel
On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
You've just broken the ABI.
New entries have to go on the end.
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
Once there is more than 1, we need to know what each entry is and the
order.
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-19 14:20 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-19 14:20 UTC (permalink / raw)
To: Aradhya Bhatia
Cc: Jyri Sarha, Tomi Valkeinen, Vignesh Raghavendra, Nishanth Menon,
DRI Development, Devicetree, Linux ARM Kernel, Linux Kernel,
Nikhil Devshatwar
On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> The DSS IP on the ti-am65x soc supports an additional register space,
> named "common1". Further. the IP services a maximum number of 2
> interrupts.
>
> Add the missing register space "common1" and the additional interrupt.
>
> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> ---
> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> index 5c7d2cbc4aac..102059e9e0d5 100644
> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> @@ -26,6 +26,7 @@ properties:
> Addresses to each DSS memory region described in the SoC's TRM.
> items:
> - description: common DSS register area
> + - description: common1 DSS register area
You've just broken the ABI.
New entries have to go on the end.
> - description: VIDL1 light video plane
> - description: VID video plane
> - description: OVR1 overlay manager for vp1
> @@ -36,6 +37,7 @@ properties:
> reg-names:
> items:
> - const: common
> + - const: common1
> - const: vidl1
> - const: vid
> - const: ovr1
> @@ -64,7 +66,7 @@ properties:
> maxItems: 3
>
> interrupts:
> - maxItems: 1
> + maxItems: 2
Once there is more than 1, we need to know what each entry is and the
order.
>
> power-domains:
> maxItems: 1
> @@ -122,13 +124,14 @@ examples:
> dss: dss@4a00000 {
> compatible = "ti,am65x-dss";
> reg = <0x04a00000 0x1000>, /* common */
> + reg = <0x04a01000 0x1000>, /* common1 */
> <0x04a02000 0x1000>, /* vidl1 */
> <0x04a06000 0x1000>, /* vid */
> <0x04a07000 0x1000>, /* ovr1 */
> <0x04a08000 0x1000>, /* ovr2 */
> <0x04a0a000 0x1000>, /* vp1 */
> <0x04a0b000 0x1000>; /* vp2 */
> - reg-names = "common", "vidl1", "vid",
> + reg-names = "common", "common1". "vidl1", "vid",
> "ovr1", "ovr2", "vp1", "vp2";
> ti,am65x-oldi-io-ctrl = <&dss_oldi_io_ctrl>;
> power-domains = <&k3_pds 67 TI_SCI_PD_EXCLUSIVE>;
> @@ -136,7 +139,8 @@ examples:
> <&k3_clks 216 1>,
> <&k3_clks 67 2>;
> clock-names = "fck", "vp1", "vp2";
> - interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>;
> + interrupts = <GIC_SPI 166 IRQ_TYPE_EDGE_RISING>,
> + <GIC_SPI 167 IRQ_TYPE_EDGE_RISING>;
> ports {
> #address-cells = <1>;
> #size-cells = <0>;
> --
> 2.35.3
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
2022-04-19 12:06 ` Tomi Valkeinen
(?)
@ 2022-04-19 17:29 ` Aradhya Bhatia
-1 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 17:29 UTC (permalink / raw)
To: Tomi Valkeinen, Rob Herring, Nishanth Menon
Cc: Jyri Sarha, Vignesh Raghavendra, DRI Development, Devicetree,
Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 17:29 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 17:29 UTC (permalink / raw)
To: Tomi Valkeinen, Rob Herring, Nishanth Menon
Cc: Devicetree, Vignesh Raghavendra, Linux Kernel, DRI Development,
Jyri Sarha, Nikhil Devshatwar, Linux ARM Kernel
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 0/2] Update register & interrupt info in am65x DSS
@ 2022-04-19 17:29 ` Aradhya Bhatia
0 siblings, 0 replies; 30+ messages in thread
From: Aradhya Bhatia @ 2022-04-19 17:29 UTC (permalink / raw)
To: Tomi Valkeinen, Rob Herring, Nishanth Menon
Cc: Jyri Sarha, Vignesh Raghavendra, DRI Development, Devicetree,
Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar
On 19/04/22 17:36, Tomi Valkeinen wrote:
> On 19/04/2022 10:03, Aradhya Bhatia wrote:
>> The Display SubSystem IP on the ti's am65x soc has an additional
>> register space "common1" and services a maximum of 2 interrupts.
>>
>> The first patch in the series adds the required updates to the yaml
>> file. The second patch then reflects the yaml updates in the DSS DT
>> node of am65x soc.
>>
>> Aradhya Bhatia (2):
>> dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
>> arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node
>>
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 6 ++++--
>> 2 files changed, 11 insertions(+), 5 deletions(-)
>>
>
> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
>
> How are you planning to use the common1 area?
Tomi, Nishanth,
Thank you for taking out time to review this.
The DSS IP is such that it services 2 interrupts in case people want to
use DSS from 2 SW entities (2nd VM or 2nd core). The regions "common" &
"common1" cater registers for managing these 2 interrupts.
Historically, on linux, only 1 interrupt and hence only the "common"
region has been used. Therefore, the "common1" region is not actually
required.
The patches, thus, can be ignored.
Rob,
Thank you for pointing out the mistakes I have made. I will be more
careful about them going further.
>
> Tomi
Regards
Aradhya Bhatia
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
2022-04-19 14:20 ` Rob Herring
(?)
@ 2022-04-20 7:05 ` Tomi Valkeinen
-1 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-20 7:05 UTC (permalink / raw)
To: Rob Herring
Cc: Jyri Sarha, Vignesh Raghavendra, Nishanth Menon, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar,
Aradhya Bhatia
Hi,
On 19/04/2022 17:20, Rob Herring wrote:
> On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
>> The DSS IP on the ti-am65x soc supports an additional register space,
>> named "common1". Further. the IP services a maximum number of 2
>> interrupts.
>>
>> Add the missing register space "common1" and the additional interrupt.
>>
>> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
>> ---
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> index 5c7d2cbc4aac..102059e9e0d5 100644
>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> @@ -26,6 +26,7 @@ properties:
>> Addresses to each DSS memory region described in the SoC's TRM.
>> items:
>> - description: common DSS register area
>> + - description: common1 DSS register area
>
> You've just broken the ABI.
>
> New entries have to go on the end.
I'm curious, if the 'reg-names' is a required property, as it is here,
does this still break the ABI?
Tomi
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-20 7:05 ` Tomi Valkeinen
0 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-20 7:05 UTC (permalink / raw)
To: Rob Herring
Cc: Nishanth Menon, Devicetree, Vignesh Raghavendra, Aradhya Bhatia,
Linux Kernel, DRI Development, Jyri Sarha, Nikhil Devshatwar,
Linux ARM Kernel
Hi,
On 19/04/2022 17:20, Rob Herring wrote:
> On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
>> The DSS IP on the ti-am65x soc supports an additional register space,
>> named "common1". Further. the IP services a maximum number of 2
>> interrupts.
>>
>> Add the missing register space "common1" and the additional interrupt.
>>
>> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
>> ---
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> index 5c7d2cbc4aac..102059e9e0d5 100644
>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> @@ -26,6 +26,7 @@ properties:
>> Addresses to each DSS memory region described in the SoC's TRM.
>> items:
>> - description: common DSS register area
>> + - description: common1 DSS register area
>
> You've just broken the ABI.
>
> New entries have to go on the end.
I'm curious, if the 'reg-names' is a required property, as it is here,
does this still break the ABI?
Tomi
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-20 7:05 ` Tomi Valkeinen
0 siblings, 0 replies; 30+ messages in thread
From: Tomi Valkeinen @ 2022-04-20 7:05 UTC (permalink / raw)
To: Rob Herring
Cc: Jyri Sarha, Vignesh Raghavendra, Nishanth Menon, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar,
Aradhya Bhatia
Hi,
On 19/04/2022 17:20, Rob Herring wrote:
> On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
>> The DSS IP on the ti-am65x soc supports an additional register space,
>> named "common1". Further. the IP services a maximum number of 2
>> interrupts.
>>
>> Add the missing register space "common1" and the additional interrupt.
>>
>> Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
>> ---
>> .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
>> 1 file changed, 7 insertions(+), 3 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> index 5c7d2cbc4aac..102059e9e0d5 100644
>> --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
>> @@ -26,6 +26,7 @@ properties:
>> Addresses to each DSS memory region described in the SoC's TRM.
>> items:
>> - description: common DSS register area
>> + - description: common1 DSS register area
>
> You've just broken the ABI.
>
> New entries have to go on the end.
I'm curious, if the 'reg-names' is a required property, as it is here,
does this still break the ABI?
Tomi
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
2022-04-20 7:05 ` Tomi Valkeinen
(?)
@ 2022-04-20 21:30 ` Rob Herring
-1 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-20 21:30 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: Jyri Sarha, Vignesh Raghavendra, Nishanth Menon, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar,
Aradhya Bhatia
On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote:
> Hi,
>
> On 19/04/2022 17:20, Rob Herring wrote:
> > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> > > The DSS IP on the ti-am65x soc supports an additional register space,
> > > named "common1". Further. the IP services a maximum number of 2
> > > interrupts.
> > >
> > > Add the missing register space "common1" and the additional interrupt.
> > >
> > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> > > ---
> > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> > > 1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > index 5c7d2cbc4aac..102059e9e0d5 100644
> > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > @@ -26,6 +26,7 @@ properties:
> > > Addresses to each DSS memory region described in the SoC's TRM.
> > > items:
> > > - description: common DSS register area
> > > + - description: common1 DSS register area
> >
> > You've just broken the ABI.
> >
> > New entries have to go on the end.
>
> I'm curious, if the 'reg-names' is a required property, as it is here, does
> this still break the ABI?
Yes, the order is part of the ABI.
Sometimes we just give up with multiple optional entries or inherited
any order allowed, but here there is no reason. Just add 'common1' to
the end.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-20 21:30 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-20 21:30 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: Nishanth Menon, Devicetree, Vignesh Raghavendra, Aradhya Bhatia,
Linux Kernel, DRI Development, Jyri Sarha, Nikhil Devshatwar,
Linux ARM Kernel
On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote:
> Hi,
>
> On 19/04/2022 17:20, Rob Herring wrote:
> > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> > > The DSS IP on the ti-am65x soc supports an additional register space,
> > > named "common1". Further. the IP services a maximum number of 2
> > > interrupts.
> > >
> > > Add the missing register space "common1" and the additional interrupt.
> > >
> > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> > > ---
> > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> > > 1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > index 5c7d2cbc4aac..102059e9e0d5 100644
> > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > @@ -26,6 +26,7 @@ properties:
> > > Addresses to each DSS memory region described in the SoC's TRM.
> > > items:
> > > - description: common DSS register area
> > > + - description: common1 DSS register area
> >
> > You've just broken the ABI.
> >
> > New entries have to go on the end.
>
> I'm curious, if the 'reg-names' is a required property, as it is here, does
> this still break the ABI?
Yes, the order is part of the ABI.
Sometimes we just give up with multiple optional entries or inherited
any order allowed, but here there is no reason. Just add 'common1' to
the end.
Rob
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt
@ 2022-04-20 21:30 ` Rob Herring
0 siblings, 0 replies; 30+ messages in thread
From: Rob Herring @ 2022-04-20 21:30 UTC (permalink / raw)
To: Tomi Valkeinen
Cc: Jyri Sarha, Vignesh Raghavendra, Nishanth Menon, DRI Development,
Devicetree, Linux ARM Kernel, Linux Kernel, Nikhil Devshatwar,
Aradhya Bhatia
On Wed, Apr 20, 2022 at 10:05:34AM +0300, Tomi Valkeinen wrote:
> Hi,
>
> On 19/04/2022 17:20, Rob Herring wrote:
> > On Tue, Apr 19, 2022 at 12:33:01PM +0530, Aradhya Bhatia wrote:
> > > The DSS IP on the ti-am65x soc supports an additional register space,
> > > named "common1". Further. the IP services a maximum number of 2
> > > interrupts.
> > >
> > > Add the missing register space "common1" and the additional interrupt.
> > >
> > > Signed-off-by: Aradhya Bhatia <a-bhatia1@ti.com>
> > > ---
> > > .../devicetree/bindings/display/ti/ti,am65x-dss.yaml | 10 +++++++---
> > > 1 file changed, 7 insertions(+), 3 deletions(-)
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > index 5c7d2cbc4aac..102059e9e0d5 100644
> > > --- a/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > +++ b/Documentation/devicetree/bindings/display/ti/ti,am65x-dss.yaml
> > > @@ -26,6 +26,7 @@ properties:
> > > Addresses to each DSS memory region described in the SoC's TRM.
> > > items:
> > > - description: common DSS register area
> > > + - description: common1 DSS register area
> >
> > You've just broken the ABI.
> >
> > New entries have to go on the end.
>
> I'm curious, if the 'reg-names' is a required property, as it is here, does
> this still break the ABI?
Yes, the order is part of the ABI.
Sometimes we just give up with multiple optional entries or inherited
any order allowed, but here there is no reason. Just add 'common1' to
the end.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-04-20 21:31 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-19 7:03 [PATCH 0/2] Update register & interrupt info in am65x DSS Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: Add missing register & interrupt Aradhya Bhatia
2022-04-19 7:03 ` [PATCH 1/2] dt-bindings: display: ti, am65x-dss: " Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` Rob Herring
2022-04-19 12:12 ` [PATCH 1/2] dt-bindings: display: ti,am65x-dss: " Rob Herring
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 12:40 ` Nishanth Menon
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-19 14:20 ` Rob Herring
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 7:05 ` Tomi Valkeinen
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-20 21:30 ` Rob Herring
2022-04-19 7:03 ` [PATCH 2/2] arm64: dts: ti: k3-am65: Add missing register & interrupt in DSS node Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 7:03 ` Aradhya Bhatia
2022-04-19 12:06 ` [PATCH 0/2] Update register & interrupt info in am65x DSS Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 12:06 ` Tomi Valkeinen
2022-04-19 17:29 ` Aradhya Bhatia
2022-04-19 17:29 ` Aradhya Bhatia
2022-04-19 17:29 ` Aradhya Bhatia
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.