Re: [Intel-gfx] [PATCH 1/2] drm/i915/dg2: Add workaround 18019627453

[Matt Roper <matthew.d.roper@intel.com>]

On Tue, Apr 19, 2022 at 07:44:53AM -0700, José Roberto de Souza wrote:
> A new DG2 workaround added to some corner cases hangs.
> 
> BSpec: 54077
> BSpec: 68173
> BSpec: 71488
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_gt_regs.h     | 1 +
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> index 0a5c2648aaf07..10db058d9038c 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h
> @@ -368,6 +368,7 @@
>  #define   GEN9_FACTOR_IN_CLR_VAL_HIZ		(1 << 9)
>  
>  #define VFLSKPD					_MMIO(0x62a8)
> +#define   VF_PREFETCH_TLB_DIS			REG_BIT(5)
>  #define   DIS_OVER_FETCH_CACHE			REG_BIT(1)
>  #define   DIS_MULT_MISS_RD_SQUASH		REG_BIT(0)
>  
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 29c8cd0a81b6f..a1ba775bcb705 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -688,6 +688,9 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
>  	if (IS_DG2_GRAPHICS_STEP(engine->i915, G10, STEP_B0, STEP_FOREVER) ||
>  		IS_DG2_G11(engine->i915) || IS_DG2_G12(engine->i915))
>  		wa_masked_field_set(wal, VF_PREEMPTION, PREEMPTION_VERTEX_COUNT, 0x4000);
> +
> +	/* Wa_18019627453:dg2 */

I just took a closer look at this one...it looks like the DG2-specific
version of this workaround (e.g., per-platform ID #14015981138) lists
two potential workarounds:  the prefetch TLB bit you're setting here, or
a fixed function DOP clock gate bit.  The suggestion (on DG2
specifically) is to use the DOP gate bit.  So we might want to switch
this implementation, even if other platforms wind up going with the
other option.


Matt

> +	wa_masked_en(wal, VFLSKPD, VF_PREFETCH_TLB_DIS);
>  }
>  
>  static void fakewa_disable_nestedbb_mode(struct intel_engine_cs *engine,
> -- 
> 2.35.3
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795