From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 63019C433FE for ; Fri, 8 Apr 2022 11:15:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232983AbiDHLRm (ORCPT ); Fri, 8 Apr 2022 07:17:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232802AbiDHLRl (ORCPT ); Fri, 8 Apr 2022 07:17:41 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4BF87263652; Fri, 8 Apr 2022 04:15:38 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 12C0911FB; Fri, 8 Apr 2022 04:15:38 -0700 (PDT) Received: from lpieralisi (unknown [10.57.11.200]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A99A3F73B; Fri, 8 Apr 2022 04:15:35 -0700 (PDT) Date: Fri, 8 Apr 2022 12:15:34 +0100 From: Lorenzo Pieralisi To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Taniya Das , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Bjorn Helgaas , Prasad Malisetty , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-pci@vger.kernel.org Subject: Re: [PATCH v1 1/5] clk: qcom: regmap-mux: add pipe clk implementation Message-ID: References: <20220323085010.1753493-1-dmitry.baryshkov@linaro.org> <20220323085010.1753493-2-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220323085010.1753493-2-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Mar 23, 2022 at 11:50:06AM +0300, Dmitry Baryshkov wrote: > On recent Qualcomm platforms the QMP PIPE clocks feed into a set of > muxes which must be parked to the "safe" source (bi_tcxo) when > corresponding GDSC is turned off and on again. Currently this is > handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src > clock. However the same code sequence should be applied in the > pcie-qcom endpoint, USB3 and UFS drivers. > > Rather than copying this sequence over and over again, follow the > example of clk_rcg2_shared_ops and implement this parking in the > enable() and disable() clock operations. As we are changing the parent > behind the back of the clock framework, also implement custom > set_parent() and get_parent() operations behaving accroding to the clock > framework expectations (cache the new parent if the clock is in disabled > state, return cached parent). > > Signed-off-by: Dmitry Baryshkov > --- > drivers/clk/qcom/clk-regmap-mux.c | 78 +++++++++++++++++++++++++++++++ > drivers/clk/qcom/clk-regmap-mux.h | 3 ++ > 2 files changed, 81 insertions(+) Need BjornA's ACK on this patch and I can pull the series then. Lorenzo > diff --git a/drivers/clk/qcom/clk-regmap-mux.c b/drivers/clk/qcom/clk-regmap-mux.c > index 45d9cca28064..c39ee783ee83 100644 > --- a/drivers/clk/qcom/clk-regmap-mux.c > +++ b/drivers/clk/qcom/clk-regmap-mux.c > @@ -49,9 +49,87 @@ static int mux_set_parent(struct clk_hw *hw, u8 index) > return regmap_update_bits(clkr->regmap, mux->reg, mask, val); > } > > +static u8 mux_safe_get_parent(struct clk_hw *hw) > +{ > + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); > + unsigned int val; > + > + if (clk_hw_is_enabled(hw)) > + return mux_get_parent(hw); > + > + val = mux->stored_parent_cfg; > + > + if (mux->parent_map) > + return qcom_find_cfg_index(hw, mux->parent_map, val); > + > + return val; > +} > + > +static int mux_safe_set_parent(struct clk_hw *hw, u8 index) > +{ > + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); > + > + if (clk_hw_is_enabled(hw)) > + return mux_set_parent(hw, index); > + > + if (mux->parent_map) > + index = mux->parent_map[index].cfg; > + > + mux->stored_parent_cfg = index; > + > + return 0; > +} > + > +static void mux_safe_disable(struct clk_hw *hw) > +{ > + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); > + struct clk_regmap *clkr = to_clk_regmap(hw); > + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); > + unsigned int val; > + > + regmap_read(clkr->regmap, mux->reg, &val); > + > + mux->stored_parent_cfg = (val & mask) >> mux->shift; > + > + val = mux->safe_src_parent; > + if (mux->parent_map) { > + int index = qcom_find_src_index(hw, mux->parent_map, val); > + > + if (WARN_ON(index < 0)) > + return; > + > + val = mux->parent_map[index].cfg; > + } > + val <<= mux->shift; > + > + regmap_update_bits(clkr->regmap, mux->reg, mask, val); > +} > + > +static int mux_safe_enable(struct clk_hw *hw) > +{ > + struct clk_regmap_mux *mux = to_clk_regmap_mux(hw); > + struct clk_regmap *clkr = to_clk_regmap(hw); > + unsigned int mask = GENMASK(mux->width + mux->shift - 1, mux->shift); > + unsigned int val; > + > + val = mux->stored_parent_cfg; > + val <<= mux->shift; > + > + return regmap_update_bits(clkr->regmap, mux->reg, mask, val); > +} > + > const struct clk_ops clk_regmap_mux_closest_ops = { > .get_parent = mux_get_parent, > .set_parent = mux_set_parent, > .determine_rate = __clk_mux_determine_rate_closest, > }; > EXPORT_SYMBOL_GPL(clk_regmap_mux_closest_ops); > + > +const struct clk_ops clk_regmap_mux_safe_ops = { > + .enable = mux_safe_enable, > + .disable = mux_safe_disable, > + .get_parent = mux_safe_get_parent, > + .set_parent = mux_safe_set_parent, > + .determine_rate = __clk_mux_determine_rate_closest, > +}; > +EXPORT_SYMBOL_GPL(clk_regmap_mux_safe_ops); > diff --git a/drivers/clk/qcom/clk-regmap-mux.h b/drivers/clk/qcom/clk-regmap-mux.h > index db6f4cdd9586..f86c674ce139 100644 > --- a/drivers/clk/qcom/clk-regmap-mux.h > +++ b/drivers/clk/qcom/clk-regmap-mux.h > @@ -14,10 +14,13 @@ struct clk_regmap_mux { > u32 reg; > u32 shift; > u32 width; > + u8 safe_src_parent; > + u8 stored_parent_cfg; > const struct parent_map *parent_map; > struct clk_regmap clkr; > }; > > extern const struct clk_ops clk_regmap_mux_closest_ops; > +extern const struct clk_ops clk_regmap_mux_safe_ops; > > #endif > -- > 2.35.1 >