From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0011C433EF for ; Thu, 21 Apr 2022 09:36:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=9ozBIQERQP2bubTjy2eZg4O+W+TULO82VWrE6ArC9MQ=; b=1psgRNuPE6/kry +MYr3C84c5ovBmJwP2casx3wYD6Z7OwAcBQl36FTFaFUIdBwuPUZm7sOw1HiZ4hJ2VmDg4s4I0CET D/kJbemg3t8MxoQqvC2GtTD4hk5XhhMDm5cmyXTXFS3VBnyb9p0aqSK7QZcu6Q9r7SKA8VQKN5n9u xixsGl2mmpPJ7Ga6ZXASX5hpqyXCd8OmphmRMVAzPj1dWUOk/YKoRz9fdVNT4mv09w7amiTdVTaR2 B8w242Fa4ARCU+XGP8vSKK+xQsrn3Y0wbz6SKnskeDCxI6qj/Y540ZvdT5DmjaTAqmqZLVDNQJ05S LhOkEh+jP6Fhkdz524Eg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhTDT-00Cmga-60; Thu, 21 Apr 2022 09:35:11 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nhTDO-00Cmea-Hg for linux-arm-kernel@lists.infradead.org; Thu, 21 Apr 2022 09:35:08 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 00C5B1477; Thu, 21 Apr 2022 02:35:05 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.76.146]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D42483F766; Thu, 21 Apr 2022 02:35:03 -0700 (PDT) Date: Thu, 21 Apr 2022 10:35:01 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v4 2/8] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Message-ID: References: <20220419104329.188489-1-broonie@kernel.org> <20220419104329.188489-3-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220419104329.188489-3-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220421_023506_716955_F6CB1198 X-CRM114-Status: GOOD ( 22.16 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 19, 2022 at 11:43:23AM +0100, Mark Brown wrote: > The macros for accessing fields in ID_AA64ISAR0_EL1 omit the _EL1 from the > name of the register. In preparation for converting this register to be > automatically generated update the names to include an _EL1, there should > be no functional change. > > Signed-off-by: Mark Brown Doing this consistently makes sense to me, so FWIW: Acked-by: Mark RUtland Thanks, Mark. > --- > arch/arm64/include/asm/archrandom.h | 2 +- > arch/arm64/include/asm/sysreg.h | 34 ++++----- > arch/arm64/kernel/cpufeature.c | 70 +++++++++---------- > .../arm64/kvm/hyp/include/nvhe/fixed_config.h | 28 ++++---- > 4 files changed, 67 insertions(+), 67 deletions(-) > > diff --git a/arch/arm64/include/asm/archrandom.h b/arch/arm64/include/asm/archrandom.h > index d1bb5e71df25..3a6b6d38c5b8 100644 > --- a/arch/arm64/include/asm/archrandom.h > +++ b/arch/arm64/include/asm/archrandom.h > @@ -142,7 +142,7 @@ static inline bool __init __early_cpu_has_rndr(void) > { > /* Open code as we run prior to the first call to cpufeature. */ > unsigned long ftr = read_sysreg_s(SYS_ID_AA64ISAR0_EL1); > - return (ftr >> ID_AA64ISAR0_RNDR_SHIFT) & 0xf; > + return (ftr >> ID_AA64ISAR0_EL1_RNDR_SHIFT) & 0xf; > } > > static inline bool __init __must_check > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index ff7693902686..1911f36773e5 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -729,23 +729,23 @@ > #define MAIR_ATTRIDX(attr, idx) ((attr) << ((idx) * 8)) > > /* id_aa64isar0 */ > -#define ID_AA64ISAR0_RNDR_SHIFT 60 > -#define ID_AA64ISAR0_TLB_SHIFT 56 > -#define ID_AA64ISAR0_TS_SHIFT 52 > -#define ID_AA64ISAR0_FHM_SHIFT 48 > -#define ID_AA64ISAR0_DP_SHIFT 44 > -#define ID_AA64ISAR0_SM4_SHIFT 40 > -#define ID_AA64ISAR0_SM3_SHIFT 36 > -#define ID_AA64ISAR0_SHA3_SHIFT 32 > -#define ID_AA64ISAR0_RDM_SHIFT 28 > -#define ID_AA64ISAR0_ATOMICS_SHIFT 20 > -#define ID_AA64ISAR0_CRC32_SHIFT 16 > -#define ID_AA64ISAR0_SHA2_SHIFT 12 > -#define ID_AA64ISAR0_SHA1_SHIFT 8 > -#define ID_AA64ISAR0_AES_SHIFT 4 > - > -#define ID_AA64ISAR0_TLB_RANGE_NI 0x0 > -#define ID_AA64ISAR0_TLB_RANGE 0x2 > +#define ID_AA64ISAR0_EL1_RNDR_SHIFT 60 > +#define ID_AA64ISAR0_EL1_TLB_SHIFT 56 > +#define ID_AA64ISAR0_EL1_TS_SHIFT 52 > +#define ID_AA64ISAR0_EL1_FHM_SHIFT 48 > +#define ID_AA64ISAR0_EL1_DP_SHIFT 44 > +#define ID_AA64ISAR0_EL1_SM4_SHIFT 40 > +#define ID_AA64ISAR0_EL1_SM3_SHIFT 36 > +#define ID_AA64ISAR0_EL1_SHA3_SHIFT 32 > +#define ID_AA64ISAR0_EL1_RDM_SHIFT 28 > +#define ID_AA64ISAR0_EL1_ATOMICS_SHIFT 20 > +#define ID_AA64ISAR0_EL1_CRC32_SHIFT 16 > +#define ID_AA64ISAR0_EL1_SHA2_SHIFT 12 > +#define ID_AA64ISAR0_EL1_SHA1_SHIFT 8 > +#define ID_AA64ISAR0_EL1_AES_SHIFT 4 > + > +#define ID_AA64ISAR0_EL1_TLB_RANGE_NI 0x0 > +#define ID_AA64ISAR0_EL1_TLB_RANGE 0x2 > > /* id_aa64isar1 */ > #define ID_AA64ISAR1_I8MM_SHIFT 52 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index d72c4b4d389c..863a510d8944 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -191,20 +191,20 @@ static bool __system_matches_cap(unsigned int n); > * sync with the documentation of the CPU feature register ABI. > */ > static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RNDR_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TLB_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_TS_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_FHM_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_DP_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM4_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_AES_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TLB_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_TS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_DP_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_ATOMICS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_EL1_AES_SHIFT, 4, 0), > ARM64_FTR_END, > }; > > @@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64ISAR0_EL1, > - .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, > + .field_pos = ID_AA64ISAR0_EL1_ATOMICS_SHIFT, > .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 2, > @@ -2195,10 +2195,10 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64ISAR0_EL1, > - .field_pos = ID_AA64ISAR0_TLB_SHIFT, > + .field_pos = ID_AA64ISAR0_EL1_TLB_SHIFT, > .field_width = 4, > .sign = FTR_UNSIGNED, > - .min_field_value = ID_AA64ISAR0_TLB_RANGE, > + .min_field_value = ID_AA64ISAR0_EL1_TLB_RANGE, > }, > #ifdef CONFIG_ARM64_HW_AFDBM > { > @@ -2227,7 +2227,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64ISAR0_EL1, > - .field_pos = ID_AA64ISAR0_CRC32_SHIFT, > + .field_pos = ID_AA64ISAR0_EL1_CRC32_SHIFT, > .field_width = 4, > .min_field_value = 1, > }, > @@ -2382,7 +2382,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64ISAR0_EL1, > - .field_pos = ID_AA64ISAR0_RNDR_SHIFT, > + .field_pos = ID_AA64ISAR0_EL1_RNDR_SHIFT, > .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 1, > @@ -2514,22 +2514,22 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = { > #endif > > static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_PMULL), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_AES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AES), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA1_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA1), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_SM4_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM4), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_DP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDDP), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_FHM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDFHM), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FLAGM), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_TS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_FLAGM2), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_EL1_RNDR_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RNG), > HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_FP), > HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_FP_SHIFT, 4, FTR_SIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_FPHP), > HWCAP_CAP(SYS_ID_AA64PFR0_EL1, ID_AA64PFR0_ASIMD_SHIFT, 4, FTR_SIGNED, 0, CAP_HWCAP, KERNEL_HWCAP_ASIMD), > diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > index 5ad626527d41..6cda33d23287 100644 > --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > @@ -159,20 +159,20 @@ > * No restrictions on instructions implemented in AArch64. > */ > #define PVM_ID_AA64ISAR0_ALLOW (\ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_AES) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_SM4) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_DP) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_FHM) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_TS) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_TLB) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_RNDR) \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_AES) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA1) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA2) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_CRC32) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_ATOMICS) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RDM) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SHA3) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM3) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_SM4) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_DP) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_FHM) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TS) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_TLB) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_EL1_RNDR) \ > ) > > #define PVM_ID_AA64ISAR1_ALLOW (\ > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel