From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 735CCC43217 for ; Mon, 25 Apr 2022 16:34:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243466AbiDYQhS (ORCPT ); Mon, 25 Apr 2022 12:37:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47458 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232384AbiDYQhQ (ORCPT ); Mon, 25 Apr 2022 12:37:16 -0400 Received: from mail-oo1-f50.google.com (mail-oo1-f50.google.com [209.85.161.50]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 84D9ADE92F; Mon, 25 Apr 2022 09:34:11 -0700 (PDT) Received: by mail-oo1-f50.google.com with SMTP id x22-20020a4aca96000000b00338fbaf797bso2884396ooq.10; Mon, 25 Apr 2022 09:34:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=1loEjRTP/Q6tR950lkPpHaLcFJYgRPsFYzQY0su75F8=; b=ALsyO5G0xdI9zR41jbhvGKtYcsXvj/e15vOg7NjVF2Dgt2C9R/0+z7M8BzqD0qfsM2 eVUI2Nytc5npkKkEdQWbCZJaTzY57Qpv4LjcEtM8DKy3DeF8dPZCsBuGFd9s3lI3w+X+ RdX5Xfin1mqosJKI07UvFwPpCHU7sZzCsc3KRp5hMoLmgBDGH4Ttz37VCDvoAuqCQN2c M9kBFITX2Rm+Ji+uPLiXV0PE3ai64DZQLP43bKhZZx76RAQQycXz+kSA8AYn6JSJegtn BOWmMdWLYe5wa3HY8NM429JGtkjRDZ5ZqV0h08ao11KRzaYmk/4S76N7ea1VE7NAQW4e e13g== X-Gm-Message-State: AOAM531Ven9Zy+I0n2HI4EeJldAse71q609xlftQN5e0efcKi5iYsUk4 280wlGRXG0U+jupSOx+wXA== X-Google-Smtp-Source: ABdhPJzPAsEnmHRb12a7tBkVVEyHXJ2dEIu3UFJdjKhTaOJtwR20kd5qtparR6MVwRfloGCKxeNKgg== X-Received: by 2002:a4a:92d4:0:b0:33a:3d7d:fe5 with SMTP id j20-20020a4a92d4000000b0033a3d7d0fe5mr6675192ooh.83.1650904450714; Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bk35-20020a0568081a2300b003226178fe7bsm3964854oib.33.2022.04.25.09.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: (nullmailer pid 4018960 invoked by uid 1000); Mon, 25 Apr 2022 16:34:09 -0000 Date: Mon, 25 Apr 2022 11:34:09 -0500 From: Rob Herring To: Rex-BC Chen Cc: krzysztof.kozlowski+dt@linaro.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, nancy.lin@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH 5/5] dt-bindings: mediatek: add ethdr definition for mt8195 Message-ID: References: <20220419033237.23405-1-rex-bc.chen@mediatek.com> <20220419033237.23405-6-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220419033237.23405-6-rex-bc.chen@mediatek.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote: > From: "Nancy.Lin" > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno > --- > .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > new file mode 100644 > index 000000000000..e8303c28a361 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethdr Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + > +description: | No need for '|' unless you have formatting to preserve. > + ETHDR is designed for HDR video and graphics conversion in the external display path. > + It handles multiple HDR input types and performs tone mapping, color space/color > + format conversion, and then combine different layers, output the required HDR or > + SDR signal to the subsequent display path. This engine is composed of two video > + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two > + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed > + registers from DRAM and set them to HW in the v-blanking period. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-disp-ethdr blank line between DT properties. > + reg: > + maxItems: 7 > + reg-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + interrupts: > + minItems: 1 maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > + details. > + minItems: 1 > + maxItems: 2 > + clocks: > + items: > + - description: mixer clock > + - description: video frontend 0 clock > + - description: video frontend 1 clock > + - description: graphic frontend 0 clock > + - description: graphic frontend 1 clock > + - description: video backend clock > + - description: autodownload and menuload clock > + - description: video frontend 0 async clock > + - description: video frontend 1 async clock > + - description: graphic frontend 0 async clock > + - description: graphic frontend 1 async clock > + - description: video backend async clock > + - description: ethdr top clock > + clock-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + - const: ethdr_top > + power-domains: > + maxItems: 1 > + resets: > + maxItems: 5 Need to define what they are and order. > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce. > + There are 4 arguments in this property, gce node, subsys id, offset and > + register size. The subsys id is defined in the gce header of each chips > + include/include/dt-bindings/gce/-gce.h, mapping to the register of > + display function block. Need to define each cell: minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ... Seems odd this property is optional... > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ethdr@1c114000 { > + compatible = "mediatek,mt8195-disp-ethdr"; > + reg = <0 0x1c114000 0 0x1000>, > + <0 0x1c115000 0 0x1000>, > + <0 0x1c117000 0 0x1000>, > + <0 0x1c119000 0 0x1000>, > + <0 0x1c11a000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>; > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds"; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, > + <&vdosys1 CLK_VDO1_26M_SLOW>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, > + <&topckgen CLK_TOP_ETHDR>; > + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", > + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", > + "ethdr_top"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; > + interrupts = ; /* disp mixer */ > + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; > + }; > + }; > + > +... > -- > 2.18.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 8637EC433EF for ; Mon, 25 Apr 2022 16:34:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=dVMYyqbbJV/GbbD6/g5PItekKDcF79Rb8gGg7HExLRA=; b=eNzPdQ1RVfgP7N NK2jZ+m1yNsh4GyAJnnT5jqJnnYF5BkzSZEU+77gYdQfXmY8CV3jXlK3fP6+vg69bcGZvWetQE3B1 +b6y1FHyAWpFygwZZoAEQIpqYt59rA2Fl/0p46a5urp6Hph/KOZb4HK2gRGzL3KwHn0WGYCsRm6kj cLzjsC25Jpvsw+HxWWCl4sDxRDiH4A/UXvZWxpOm0SyXBHPfTl/J58iANiEWzV69T7bqpyLwjj5vZ nEu9mKDU15LfonrTeYm/0uHof1DTIbOJheoDbxTYbVyBlOr9fc1UJGkoz9zVn+6yKfAnplAV4RG6C 9HxdEGrNf7DfG+DZ4/eQ==; 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id bk35-20020a0568081a2300b003226178fe7bsm3964854oib.33.2022.04.25.09.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: (nullmailer pid 4018960 invoked by uid 1000); Mon, 25 Apr 2022 16:34:09 -0000 Date: Mon, 25 Apr 2022 11:34:09 -0500 From: Rob Herring To: Rex-BC Chen Cc: krzysztof.kozlowski+dt@linaro.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, nancy.lin@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH 5/5] dt-bindings: mediatek: add ethdr definition for mt8195 Message-ID: References: <20220419033237.23405-1-rex-bc.chen@mediatek.com> <20220419033237.23405-6-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220419033237.23405-6-rex-bc.chen@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_093412_583115_A4241494 X-CRM114-Status: GOOD ( 24.97 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote: > From: "Nancy.Lin" > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno > --- > .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > new file mode 100644 > index 000000000000..e8303c28a361 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethdr Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + > +description: | No need for '|' unless you have formatting to preserve. > + ETHDR is designed for HDR video and graphics conversion in the external display path. > + It handles multiple HDR input types and performs tone mapping, color space/color > + format conversion, and then combine different layers, output the required HDR or > + SDR signal to the subsequent display path. This engine is composed of two video > + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two > + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed > + registers from DRAM and set them to HW in the v-blanking period. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-disp-ethdr blank line between DT properties. > + reg: > + maxItems: 7 > + reg-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + interrupts: > + minItems: 1 maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > + details. > + minItems: 1 > + maxItems: 2 > + clocks: > + items: > + - description: mixer clock > + - description: video frontend 0 clock > + - description: video frontend 1 clock > + - description: graphic frontend 0 clock > + - description: graphic frontend 1 clock > + - description: video backend clock > + - description: autodownload and menuload clock > + - description: video frontend 0 async clock > + - description: video frontend 1 async clock > + - description: graphic frontend 0 async clock > + - description: graphic frontend 1 async clock > + - description: video backend async clock > + - description: ethdr top clock > + clock-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + - const: ethdr_top > + power-domains: > + maxItems: 1 > + resets: > + maxItems: 5 Need to define what they are and order. > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce. > + There are 4 arguments in this property, gce node, subsys id, offset and > + register size. The subsys id is defined in the gce header of each chips > + include/include/dt-bindings/gce/-gce.h, mapping to the register of > + display function block. Need to define each cell: minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ... Seems odd this property is optional... > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ethdr@1c114000 { > + compatible = "mediatek,mt8195-disp-ethdr"; > + reg = <0 0x1c114000 0 0x1000>, > + <0 0x1c115000 0 0x1000>, > + <0 0x1c117000 0 0x1000>, > + <0 0x1c119000 0 0x1000>, > + <0 0x1c11a000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>; > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds"; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, > + <&vdosys1 CLK_VDO1_26M_SLOW>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, > + <&topckgen CLK_TOP_ETHDR>; > + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", > + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", > + "ethdr_top"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; > + interrupts = ; /* disp mixer */ > + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; > + }; > + }; > + > +... > -- > 2.18.0 > > _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 99BE6C433FE for ; Mon, 25 Apr 2022 16:34:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CECC810EE40; Mon, 25 Apr 2022 16:34:13 +0000 (UTC) Received: from mail-oo1-f44.google.com (mail-oo1-f44.google.com [209.85.161.44]) by gabe.freedesktop.org (Postfix) with ESMTPS id A748C10EEAA for ; Mon, 25 Apr 2022 16:34:11 +0000 (UTC) Received: by mail-oo1-f44.google.com with SMTP id n22-20020a4ae1d6000000b0033a6eedbc7bso2880786oot.11 for ; Mon, 25 Apr 2022 09:34:11 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=1loEjRTP/Q6tR950lkPpHaLcFJYgRPsFYzQY0su75F8=; b=hEzDd0QPzct0UsAeafPdh7P6xEo86DWN7LWMMm8+bq6e7K/pFXON8SSvaUcxxzEz5q K94KNV7Htl8j12Vmg1XGWlGER89b8oRzEiMqap5fkIryc60kwP9ml9mT6PBEkZis4vHC ZoC9WKmgncnKWyMpXRsbv0CDZAN5uE3MxKJrY3ZCpFg1tXqfgXUaMPSovdmEEOGzgPG9 DJ8RNakxHDlG/kpaeaVQBPaOhj/sQEWCEC6NgNS/6EVmaYTY9w1YYcJTBKiKpU1PmgEG +AYe4ORPQ1yVGTDyXBwsT78t/7ijlZZXo60DIUucXlVuyrD7ipvIxdaOHYdVYJd0K01B PYxg== X-Gm-Message-State: AOAM530z3uBM0h0Z07mpnm4T4ieP3ejqlrPcS5qxQl6lzlGn19GA+6i0 XMpiOtVQUUSV9gzeI8xlUQ== X-Google-Smtp-Source: ABdhPJzPAsEnmHRb12a7tBkVVEyHXJ2dEIu3UFJdjKhTaOJtwR20kd5qtparR6MVwRfloGCKxeNKgg== X-Received: by 2002:a4a:92d4:0:b0:33a:3d7d:fe5 with SMTP id j20-20020a4a92d4000000b0033a3d7d0fe5mr6675192ooh.83.1650904450714; Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: from robh.at.kernel.org (66-90-144-107.dyn.grandenetworks.net. [66.90.144.107]) by smtp.gmail.com with ESMTPSA id bk35-20020a0568081a2300b003226178fe7bsm3964854oib.33.2022.04.25.09.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: (nullmailer pid 4018960 invoked by uid 1000); Mon, 25 Apr 2022 16:34:09 -0000 Date: Mon, 25 Apr 2022 11:34:09 -0500 From: Rob Herring To: Rex-BC Chen Subject: Re: [PATCH 5/5] dt-bindings: mediatek: add ethdr definition for mt8195 Message-ID: References: <20220419033237.23405-1-rex-bc.chen@mediatek.com> <20220419033237.23405-6-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220419033237.23405-6-rex-bc.chen@mediatek.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: chunkuang.hu@kernel.org, krzysztof.kozlowski+dt@linaro.org, devicetree@vger.kernel.org, airlied@linux.ie, jason-jh.lin@mediatek.com, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Project_Global_Chrome_Upstream_Group@mediatek.com, nancy.lin@mediatek.com, linux-mediatek@lists.infradead.org, matthias.bgg@gmail.com, linux-arm-kernel@lists.infradead.org, angelogioacchino.delregno@collabora.com Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote: > From: "Nancy.Lin" > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno > --- > .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > new file mode 100644 > index 000000000000..e8303c28a361 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethdr Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + > +description: | No need for '|' unless you have formatting to preserve. > + ETHDR is designed for HDR video and graphics conversion in the external display path. > + It handles multiple HDR input types and performs tone mapping, color space/color > + format conversion, and then combine different layers, output the required HDR or > + SDR signal to the subsequent display path. This engine is composed of two video > + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two > + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed > + registers from DRAM and set them to HW in the v-blanking period. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-disp-ethdr blank line between DT properties. > + reg: > + maxItems: 7 > + reg-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + interrupts: > + minItems: 1 maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > + details. > + minItems: 1 > + maxItems: 2 > + clocks: > + items: > + - description: mixer clock > + - description: video frontend 0 clock > + - description: video frontend 1 clock > + - description: graphic frontend 0 clock > + - description: graphic frontend 1 clock > + - description: video backend clock > + - description: autodownload and menuload clock > + - description: video frontend 0 async clock > + - description: video frontend 1 async clock > + - description: graphic frontend 0 async clock > + - description: graphic frontend 1 async clock > + - description: video backend async clock > + - description: ethdr top clock > + clock-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + - const: ethdr_top > + power-domains: > + maxItems: 1 > + resets: > + maxItems: 5 Need to define what they are and order. > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce. > + There are 4 arguments in this property, gce node, subsys id, offset and > + register size. The subsys id is defined in the gce header of each chips > + include/include/dt-bindings/gce/-gce.h, mapping to the register of > + display function block. Need to define each cell: minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ... Seems odd this property is optional... > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ethdr@1c114000 { > + compatible = "mediatek,mt8195-disp-ethdr"; > + reg = <0 0x1c114000 0 0x1000>, > + <0 0x1c115000 0 0x1000>, > + <0 0x1c117000 0 0x1000>, > + <0 0x1c119000 0 0x1000>, > + <0 0x1c11a000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>; > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds"; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, > + <&vdosys1 CLK_VDO1_26M_SLOW>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, > + <&topckgen CLK_TOP_ETHDR>; > + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", > + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", > + "ethdr_top"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; > + interrupts = ; /* disp mixer */ > + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; > + }; > + }; > + > +... > -- > 2.18.0 > > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 852C8C433F5 for ; Mon, 25 Apr 2022 16:35:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=M6qmH+CFSWAnOgV7nzfSigD0SJRRtJzrRiZnNq2pr9Q=; b=2knX1xLZBOlZDI hNyVAuI66xVx0C77onPtlKYy0o5OmfN2Ivu9Vs/qzcoybOXwQjQXoPKx2IuQ7TjimYHLKOB9UUgtH D6LnlBLb667HTOQC/+lRwXkiY4aqQ8GhC++ux7yV7d6/MXRd1du7w0ytyxpANU2M29hTBpTVtOtGt J40oSxpUUmfMpoS4UaWUtRd/7orRqC62IBf9flSc7aSKUaL14ylHKKBaDpeJdwViRTmPIEtRAAJwt rH+EnIy1ZH9babQOKyUbBezs1Ug6ic2McSdMmBVA7rNxi+2JlJzuDxTNYFYOnQH6/1rrM674Oy5OK nWOaV9nTMi9Xz0xzglCg==; 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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id bk35-20020a0568081a2300b003226178fe7bsm3964854oib.33.2022.04.25.09.34.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 25 Apr 2022 09:34:10 -0700 (PDT) Received: (nullmailer pid 4018960 invoked by uid 1000); Mon, 25 Apr 2022 16:34:09 -0000 Date: Mon, 25 Apr 2022 11:34:09 -0500 From: Rob Herring To: Rex-BC Chen Cc: krzysztof.kozlowski+dt@linaro.org, chunkuang.hu@kernel.org, p.zabel@pengutronix.de, airlied@linux.ie, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, jason-jh.lin@mediatek.com, nancy.lin@mediatek.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Project_Global_Chrome_Upstream_Group@mediatek.com Subject: Re: [PATCH 5/5] dt-bindings: mediatek: add ethdr definition for mt8195 Message-ID: References: <20220419033237.23405-1-rex-bc.chen@mediatek.com> <20220419033237.23405-6-rex-bc.chen@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220419033237.23405-6-rex-bc.chen@mediatek.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220425_093412_583115_A4241494 X-CRM114-Status: GOOD ( 24.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 19, 2022 at 11:32:37AM +0800, Rex-BC Chen wrote: > From: "Nancy.Lin" > > Add vdosys1 ETHDR definition. > > Signed-off-by: Nancy.Lin > Reviewed-by: Chun-Kuang Hu > Reviewed-by: AngeloGioacchino Del Regno > --- > .../display/mediatek/mediatek,ethdr.yaml | 158 ++++++++++++++++++ > 1 file changed, 158 insertions(+) > create mode 100644 Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > > diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > new file mode 100644 > index 000000000000..e8303c28a361 > --- /dev/null > +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ethdr.yaml > @@ -0,0 +1,158 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/display/mediatek/mediatek,ethdr.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: MediaTek Ethdr Device Tree Bindings > + > +maintainers: > + - Chun-Kuang Hu > + - Philipp Zabel > + > +description: | No need for '|' unless you have formatting to preserve. > + ETHDR is designed for HDR video and graphics conversion in the external display path. > + It handles multiple HDR input types and performs tone mapping, color space/color > + format conversion, and then combine different layers, output the required HDR or > + SDR signal to the subsequent display path. This engine is composed of two video > + frontends, two graphic frontends, one video backend and a mixer. ETHDR has two > + DMA function blocks, DS and ADL. These two function blocks read the pre-programmed > + registers from DRAM and set them to HW in the v-blanking period. > + > +properties: > + compatible: > + items: > + - const: mediatek,mt8195-disp-ethdr blank line between DT properties. > + reg: > + maxItems: 7 > + reg-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + interrupts: > + minItems: 1 maxItems: 1 > + iommus: > + description: The compatible property is DMA function blocks. > + Should point to the respective IOMMU block with master port as argument, > + see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for > + details. > + minItems: 1 > + maxItems: 2 > + clocks: > + items: > + - description: mixer clock > + - description: video frontend 0 clock > + - description: video frontend 1 clock > + - description: graphic frontend 0 clock > + - description: graphic frontend 1 clock > + - description: video backend clock > + - description: autodownload and menuload clock > + - description: video frontend 0 async clock > + - description: video frontend 1 async clock > + - description: graphic frontend 0 async clock > + - description: graphic frontend 1 async clock > + - description: video backend async clock > + - description: ethdr top clock > + clock-names: > + items: > + - const: mixer > + - const: vdo_fe0 > + - const: vdo_fe1 > + - const: gfx_fe0 > + - const: gfx_fe1 > + - const: vdo_be > + - const: adl_ds > + - const: vdo_fe0_async > + - const: vdo_fe1_async > + - const: gfx_fe0_async > + - const: gfx_fe1_async > + - const: vdo_be_async > + - const: ethdr_top > + power-domains: > + maxItems: 1 > + resets: > + maxItems: 5 Need to define what they are and order. > + mediatek,gce-client-reg: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + description: The register of display function block to be set by gce. > + There are 4 arguments in this property, gce node, subsys id, offset and > + register size. The subsys id is defined in the gce header of each chips > + include/include/dt-bindings/gce/-gce.h, mapping to the register of > + display function block. Need to define each cell: minItems: ?? maxItems: ?? items: items: - description: gce node - description: ... ... Seems odd this property is optional... > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + #include > + #include > + #include > + > + soc { > + #address-cells = <2>; > + #size-cells = <2>; > + > + disp_ethdr@1c114000 { > + compatible = "mediatek,mt8195-disp-ethdr"; > + reg = <0 0x1c114000 0 0x1000>, > + <0 0x1c115000 0 0x1000>, > + <0 0x1c117000 0 0x1000>, > + <0 0x1c119000 0 0x1000>, > + <0 0x1c11a000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>, > + <0 0x1c11b000 0 0x1000>; > + reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds"; > + mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x5000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x7000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0x9000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xa000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xb000 0x1000>, > + <&gce0 SUBSYS_1c11XXXX 0xc000 0x1000>; > + clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE>, > + <&vdosys1 CLK_VDO1_26M_SLOW>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>, > + <&topckgen CLK_TOP_ETHDR>; > + clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1", > + "vdo_be", "adl_ds", "vdo_fe0_async", "vdo_fe1_async", > + "gfx_fe0_async", "gfx_fe1_async","vdo_be_async", > + "ethdr_top"; > + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; > + iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>, > + <&iommu_vpp M4U_PORT_L3_HDR_ADL>; > + interrupts = ; /* disp mixer */ > + resets = <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE0_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_GFX_FE1_DL_ASYNC>, > + <&vdosys1 MT8195_VDOSYS1_SW1_RST_B_HDR_VDO_BE_DL_ASYNC>; > + }; > + }; > + > +... > -- > 2.18.0 > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel