From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CB4B3C433EF for ; Thu, 28 Apr 2022 13:38:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=KmSOY5pPM1+81tAY+4OBWdx3CmelWClMk5qzBseh78Q=; b=IEio65WbTSkaC6 amV1Qolws7TqYX1OvQ+TuqRgSH5rTezXegZA5GxD3BA/qUazLvqpBhNJrDkq88dgpP88/zKEwR0KR DqcWG1DhewslbSy/gXdsHi56haLavRF2Wg+XqNjTAWbcKvFO1nWUjFteNe3Cdnn5N5GCE+TktSfVo H2pOkwR8Qo/gBGFw0nsoHVSBJDJzmuE/uox1ctnCx82ltLZYpJGMo56rgqPBHquzvgmIM+ft/U0w0 RT9ToT/uq1NAihyGgZBpcBmT16i2hgEnAfDW1LZqi6FQBTN0qJ0CbK4tvvJB2l2LWk4jAdCryn/MN ExuJTPXeaksYw80Gfe+A==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nk4Kd-0076u8-5K; Thu, 28 Apr 2022 13:37:19 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nk4FF-0074LM-98 for linux-arm-kernel@lists.infradead.org; Thu, 28 Apr 2022 13:31:47 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DCF221477; Thu, 28 Apr 2022 06:31:43 -0700 (PDT) Received: from lakrids (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EDFC23F5A1; Thu, 28 Apr 2022 06:31:42 -0700 (PDT) Date: Thu, 28 Apr 2022 14:31:33 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , Marc Zyngier , Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Message-ID: References: <20220426181704.2583494-1-broonie@kernel.org> <20220426181704.2583494-7-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220426181704.2583494-7-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220428_063145_491004_25211E88 X-CRM114-Status: GOOD ( 18.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Apr 26, 2022 at 07:16:58PM +0100, Mark Brown wrote: > The architecture reference manual refers to the field in bits 23:20 of > ID_AA64ISAR0_EL1 with the name "atomic" but the kernel defines for this > bitfield use the name "atomics". Bring the two into sync to make it easier > to cross reference with the specification. > > Signed-off-by: Mark Brown Acked-by: Mark Rutland Mark. > --- > arch/arm64/include/asm/sysreg.h | 2 +- > arch/arm64/kernel/cpufeature.c | 6 +++--- > arch/arm64/kvm/hyp/include/nvhe/fixed_config.h | 2 +- > 3 files changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index 331e2521a81a..0bb259ec6ee8 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -749,7 +749,7 @@ > #define ID_AA64ISAR0_SM3_SHIFT 36 > #define ID_AA64ISAR0_SHA3_SHIFT 32 > #define ID_AA64ISAR0_RDM_SHIFT 28 > -#define ID_AA64ISAR0_ATOMICS_SHIFT 20 > +#define ID_AA64ISAR0_ATOMIC_SHIFT 20 > #define ID_AA64ISAR0_CRC32_SHIFT 16 > #define ID_AA64ISAR0_SHA2_SHIFT 12 > #define ID_AA64ISAR0_SHA1_SHIFT 8 > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index d72c4b4d389c..18833fe6d148 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -200,7 +200,7 @@ static const struct arm64_ftr_bits ftr_id_aa64isar0[] = { > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SM3_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA3_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_RDM_SHIFT, 4, 0), > - ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMICS_SHIFT, 4, 0), > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_ATOMIC_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_CRC32_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA2_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64ISAR0_SHA1_SHIFT, 4, 0), > @@ -2013,7 +2013,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .type = ARM64_CPUCAP_SYSTEM_FEATURE, > .matches = has_cpuid_feature, > .sys_reg = SYS_ID_AA64ISAR0_EL1, > - .field_pos = ID_AA64ISAR0_ATOMICS_SHIFT, > + .field_pos = ID_AA64ISAR0_ATOMIC_SHIFT, > .field_width = 4, > .sign = FTR_UNSIGNED, > .min_field_value = 2, > @@ -2520,7 +2520,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA2), > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA2_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_SHA512), > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_CRC32_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_CRC32), > - HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMICS_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), > + HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_ATOMIC_SHIFT, 4, FTR_UNSIGNED, 2, CAP_HWCAP, KERNEL_HWCAP_ATOMICS), > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_RDM_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ASIMDRDM), > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SHA3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SHA3), > HWCAP_CAP(SYS_ID_AA64ISAR0_EL1, ID_AA64ISAR0_SM3_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_SM3), > diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > index 5ad626527d41..63a114b9b2ed 100644 > --- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > +++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h > @@ -163,7 +163,7 @@ > ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA1) | \ > ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA2) | \ > ARM64_FEATURE_MASK(ID_AA64ISAR0_CRC32) | \ > - ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMICS) | \ > + ARM64_FEATURE_MASK(ID_AA64ISAR0_ATOMIC) | \ > ARM64_FEATURE_MASK(ID_AA64ISAR0_RDM) | \ > ARM64_FEATURE_MASK(ID_AA64ISAR0_SHA3) | \ > ARM64_FEATURE_MASK(ID_AA64ISAR0_SM3) | \ > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel