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[104.57.184.186]) by smtp.gmail.com with ESMTPSA id a8-20020a4ad5c8000000b0035eb4e5a6c6sm5096138oot.28.2022.05.03.10.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 10:27:48 -0700 (PDT) Date: Tue, 3 May 2022 12:27:43 -0500 From: Bjorn Andersson To: Robert Foss Cc: agross@kernel.org, mturquette@baylibre.com, sboyd@kernel.org, robh+dt@kernel.org, krzk+dt@kernel.org, jonathan@marek.ca, tdas@codeaurora.org, anischal@codeaurora.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov Subject: Re: [PATCH v2 8/8] arm64: dts: qcom: sm8350: Add DISPCC node Message-ID: References: <20220503130448.520470-1-robert.foss@linaro.org> <20220503130448.520470-8-robert.foss@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220503130448.520470-8-robert.foss@linaro.org> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Tue 03 May 08:04 CDT 2022, Robert Foss wrote: > Add the dispcc clock-controller DT node for sm8350. > > Signed-off-by: Robert Foss > Reviewed-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sm8350.dtsi | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi > index 52428b6df64e..94c2519e9f48 100644 > --- a/arch/arm64/boot/dts/qcom/sm8350.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi > @@ -3,7 +3,9 @@ > * Copyright (c) 2020, Linaro Limited > */ > > +#include This looks unrelated. Rest looks good. Regards, Bjorn > #include > +#include > #include > #include > #include > @@ -2525,6 +2527,31 @@ usb_2_dwc3: usb@a800000 { > }; > }; > > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8350-dispcc"; > + reg = <0 0x0af00000 0 0x10000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>, > + <0>; > + clock-names = "bi_tcxo", > + "dsi0_phy_pll_out_byteclk", > + "dsi0_phy_pll_out_dsiclk", > + "dsi1_phy_pll_out_byteclk", > + "dsi1_phy_pll_out_dsiclk", > + "dp_phy_pll_link_clk", > + "dp_phy_pll_vco_div_clk"; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + > + power-domains = <&rpmhpd SM8350_MMCX>; > + power-domain-names = "mmcx"; > + }; > + > adsp: remoteproc@17300000 { > compatible = "qcom,sm8350-adsp-pas"; > reg = <0 0x17300000 0 0x100>; > -- > 2.34.1 >