All of lore.kernel.org
 help / color / mirror / Atom feed
From: Johan Hovold <johan@kernel.org>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: "Andy Gross" <agross@kernel.org>,
	"Bjorn Andersson" <bjorn.andersson@linaro.org>,
	"Stephen Boyd" <swboyd@chromium.org>,
	"Michael Turquette" <mturquette@baylibre.com>,
	"Taniya Das" <quic_tdas@quicinc.com>,
	"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
	"Krzysztof Wilczyński" <kw@linux.com>,
	"Bjorn Helgaas" <bhelgaas@google.com>,
	"Prasad Malisetty" <quic_pmaliset@quicinc.com>,
	"Johan Hovold" <johan+linaro@kernel.org>,
	linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
	linux-pci@vger.kernel.org
Subject: Re: [PATCH v4 2/5] clk: qcom: regmap: add pipe clk implementation
Date: Mon, 9 May 2022 12:17:14 +0200	[thread overview]
Message-ID: <YnjqKnkgsK+Eki4z@hovoldconsulting.com> (raw)
In-Reply-To: <20220501192149.4128158-3-dmitry.baryshkov@linaro.org>

On Sun, May 01, 2022 at 10:21:46PM +0300, Dmitry Baryshkov wrote:
> On recent Qualcomm platforms the QMP PIPE clocks feed into a set of
> muxes which must be parked to the "safe" source (bi_tcxo) when
> corresponding GDSC is turned off and on again. Currently this is
> handcoded in the PCIe driver by reparenting the gcc_pipe_N_clk_src
> clock. However the same code sequence should be applied in the
> pcie-qcom endpoint, USB3 and UFS drivers.

I noticed that the vendor kernel does not implement this for UFS (yet),
and the PHY PLL is left muxed in for UFS by the boot firmware on the
platforms I have.

But supposedly it is needed, so perhaps this should be reflected in the
naming from the start by using a more generic name than "pipe". Maybe
something like struct clk_regmap_phy_mux?
 
> Rather than copying this sequence over and over again, follow the
> example of clk_rcg2_shared_ops and implement this parking in the
> enable() and disable() clock operations. Suppliement the regmap-mux with

typo: supplement

> the new regmap-pipe implementation, which hides multiplexer behind
> simple branch-like clock. 

Please rephrase the above. I understand what you mean, but that may not
be case with someone less familiar with the details. Perhaps explain it
along the lines of modelling the multiplexer as a gate.

And you shouldn't take the "hiding" too far and obfuscate the fact that
this is a multiplexer in the implementation.

Renaming some of the structures and fields should make the
implementation more obvious. I already suggested adding a suffix to the
use of "pipe" which really refers to the pipe mux.

Similarly, using another name for the enable/disable value fields may
make it easier to see what it's going on here.

> This is possible since each of this
> multiplexers has just two clock sources: working (pipe) and safe
> (bi_tcxo) clock sources. If the clock is running off the external pipe
> source, report it as enable and report it as disabled otherwise.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/clk/qcom/Makefile          |  1 +
>  drivers/clk/qcom/clk-regmap-pipe.c | 62 ++++++++++++++++++++++++++++++
>  drivers/clk/qcom/clk-regmap-pipe.h | 24 ++++++++++++
>  3 files changed, 87 insertions(+)
>  create mode 100644 drivers/clk/qcom/clk-regmap-pipe.c
>  create mode 100644 drivers/clk/qcom/clk-regmap-pipe.h
> 
> diff --git a/drivers/clk/qcom/Makefile b/drivers/clk/qcom/Makefile
> index 671cf5821af1..882c8ecc2e93 100644
> --- a/drivers/clk/qcom/Makefile
> +++ b/drivers/clk/qcom/Makefile
> @@ -11,6 +11,7 @@ clk-qcom-y += clk-branch.o
>  clk-qcom-y += clk-regmap-divider.o
>  clk-qcom-y += clk-regmap-mux.o
>  clk-qcom-y += clk-regmap-mux-div.o
> +clk-qcom-y += clk-regmap-pipe.o
>  clk-qcom-$(CONFIG_KRAIT_CLOCKS) += clk-krait.o
>  clk-qcom-y += clk-hfpll.o
>  clk-qcom-y += reset.o
> diff --git a/drivers/clk/qcom/clk-regmap-pipe.c b/drivers/clk/qcom/clk-regmap-pipe.c
> new file mode 100644
> index 000000000000..9a7c27cc644b
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-regmap-pipe.c
> @@ -0,0 +1,62 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (c) 2022, Linaro Ltd.
> + */
> +
> +#include <linux/kernel.h>
> +#include <linux/bitops.h>
> +#include <linux/regmap.h>
> +#include <linux/export.h>
> +
> +#include "clk-regmap-pipe.h"
> +
> +static inline struct clk_regmap_pipe *to_clk_regmap_pipe(struct clk_hw *hw)
> +{
> +	return container_of(to_clk_regmap(hw), struct clk_regmap_pipe, clkr);
> +}
> +
> +static int pipe_is_enabled(struct clk_hw *hw)
> +{
> +	struct clk_regmap_pipe *pipe = to_clk_regmap_pipe(hw);
> +	struct clk_regmap *clkr = to_clk_regmap(hw);
> +	unsigned int mask = GENMASK(pipe->width + pipe->shift - 1, pipe->shift);
> +	unsigned int val;
> +
> +	regmap_read(clkr->regmap, pipe->reg, &val);
> +	val = (val & mask) >> pipe->shift;
> +
> +	WARN_ON(unlikely(val != pipe->enable_val && val != pipe->disable_val));
> +
> +	return val == pipe->enable_val;
> +}
> +
> +static int pipe_enable(struct clk_hw *hw)
> +{
> +	struct clk_regmap_pipe *pipe = to_clk_regmap_pipe(hw);
> +	struct clk_regmap *clkr = to_clk_regmap(hw);
> +	unsigned int mask = GENMASK(pipe->width + pipe->shift - 1, pipe->shift);
> +	unsigned int val;
> +
> +	val = pipe->enable_val << pipe->shift;
> +
> +	return regmap_update_bits(clkr->regmap, pipe->reg, mask, val);

So the above would be more obvious as something like

	static int pipe_mux_enable() {
		...

		val = mux->pipe_clk_val << mux->shift;
		...
	}

instead making it look like it is a gate (or maybe phy_mux_enable()
etc).

> +}
> +
> +static void pipe_disable(struct clk_hw *hw)
> +{
> +	struct clk_regmap_pipe *pipe = to_clk_regmap_pipe(hw);
> +	struct clk_regmap *clkr = to_clk_regmap(hw);
> +	unsigned int mask = GENMASK(pipe->width + pipe->shift - 1, pipe->shift);
> +	unsigned int val;
> +
> +	val = pipe->disable_val << pipe->shift;

And similar by using something like xo_clk_val here.

> +
> +	regmap_update_bits(clkr->regmap, pipe->reg, mask, val);
> +}
> +
> +const struct clk_ops clk_regmap_pipe_ops = {
> +	.enable = pipe_enable,
> +	.disable = pipe_disable,
> +	.is_enabled = pipe_is_enabled,
> +};
> +EXPORT_SYMBOL_GPL(clk_regmap_pipe_ops);
> diff --git a/drivers/clk/qcom/clk-regmap-pipe.h b/drivers/clk/qcom/clk-regmap-pipe.h
> new file mode 100644
> index 000000000000..cfaa792a029b
> --- /dev/null
> +++ b/drivers/clk/qcom/clk-regmap-pipe.h
> @@ -0,0 +1,24 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */
> +/*
> + * Copyright (c) 2022, Linaru Ltd.
> + * Author: Dmitry Baryshkov
> + */
> +
> +#ifndef __QCOM_CLK_REGMAP_PIPE_H__
> +#define __QCOM_CLK_REGMAP_PIPE_H__
> +
> +#include <linux/clk-provider.h>
> +#include "clk-regmap.h"
> +
> +struct clk_regmap_pipe {
> +	u32			reg;
> +	u32			shift;
> +	u32			width;
> +	u32			enable_val;
> +	u32			disable_val;

So this could be
	
	pipe_clk_val
	xo_clk_val

and you wouldn't need to add comments in every mux definition.

> +	struct clk_regmap	clkr;
> +};
> +
> +extern const struct clk_ops clk_regmap_pipe_ops;
> +
> +#endif

Johan

  parent reply	other threads:[~2022-05-09 10:17 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-01 19:21 [PATCH v4 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Dmitry Baryshkov
2022-05-01 19:21 ` [PATCH v4 1/5] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-05-02 10:13   ` Manivannan Sadhasivam
2022-05-09  9:41   ` Johan Hovold
2022-05-01 19:21 ` [PATCH v4 2/5] clk: qcom: regmap: add pipe clk implementation Dmitry Baryshkov
2022-05-02 10:10   ` Manivannan Sadhasivam
2022-05-02 10:35     ` Dmitry Baryshkov
2022-05-02 11:10       ` Manivannan Sadhasivam
2022-05-02 11:18         ` Dmitry Baryshkov
2022-05-02 15:06           ` Manivannan Sadhasivam
2022-05-02 15:24             ` Dmitry Baryshkov
2022-05-06 12:54             ` Johan Hovold
2022-05-06 15:25             ` Manivannan Sadhasivam
2022-05-06 12:40           ` Johan Hovold
2022-05-06 13:00             ` Dmitry Baryshkov
2022-05-09 10:29               ` Johan Hovold
2022-05-11 14:17                 ` Dmitry Baryshkov
2022-05-13  8:22                   ` Johan Hovold
2022-05-11 14:34                 ` Manivannan Sadhasivam
2022-05-06 12:31   ` Johan Hovold
2022-05-06 12:40     ` Dmitry Baryshkov
2022-05-09 10:28       ` Johan Hovold
2022-05-09 10:17   ` Johan Hovold [this message]
2022-05-01 19:21 ` [PATCH v4 3/5] clk: qcom: gcc-sm8450: use new clk_regmap_pipe_ops for PCIe pipe clocks Dmitry Baryshkov
2022-05-01 19:21 ` [PATCH v4 4/5] clk: qcom: gcc-sc7280: " Dmitry Baryshkov
2022-05-01 19:21 ` [PATCH v4 5/5] PCI: qcom: Drop manual pipe_clk_src handling Dmitry Baryshkov
2022-05-09 10:24   ` Johan Hovold
2022-05-11 13:19 ` [PATCH v4 0/5] PCI: qcom: Rework pipe_clk/pipe_clk_src handling Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=YnjqKnkgsK+Eki4z@hovoldconsulting.com \
    --to=johan@kernel.org \
    --cc=agross@kernel.org \
    --cc=bhelgaas@google.com \
    --cc=bjorn.andersson@linaro.org \
    --cc=dmitry.baryshkov@linaro.org \
    --cc=johan+linaro@kernel.org \
    --cc=kw@linux.com \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-clk@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mturquette@baylibre.com \
    --cc=quic_pmaliset@quicinc.com \
    --cc=quic_tdas@quicinc.com \
    --cc=swboyd@chromium.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.