From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 406A7C433EF for ; Fri, 20 May 2022 15:27:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=ezX84ZRT6BlMUUgsTWkhIdV5fjIS/Rt8vKC+5IlVD9c=; b=CPDxlB6pjHNUWG e9an/zWty2Jzo3f+/YrU4/bCziin465hzQNMk66TYPfXM9ebTOttLGDpAZhDAT4f2yttbwS9FrW/r rgI2aOe1qEqk6S8Vbbt7kYWzQvw9Dtc7h9FQfT224yk/TGZy8u000rZp1Ucl2PQS6XVtj10Q41QGo nzWZStNjcfV67Id9As9wz3sHbjNbjsl0sHZXLns9XFGlI9hdoZTaKIayvocppeqzFHmKL+/CwNLLq xsyosEmWIi/xZkeoXSMW75FkqsqivX9LUS8GAsLrYcYl6RbpPEhd7c0kbgtR8iWn4lbCZEmv2ECxn 1lHtMAOWSlbzSEQvG3Ag==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4Wi-00DBYk-Sy; Fri, 20 May 2022 15:26:52 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ns4We-00DBVY-Qi for linux-arm-kernel@lists.infradead.org; Fri, 20 May 2022 15:26:50 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 62C531477; Fri, 20 May 2022 08:26:47 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.7.188]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 865943F73D; Fri, 20 May 2022 08:26:46 -0700 (PDT) Date: Fri, 20 May 2022 16:26:42 +0100 From: Mark Rutland To: Mark Brown Cc: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org Subject: Re: [PATCH v1 8/9] arm64/sysreg: Generate definitions for DCZID_EL0 Message-ID: References: <20220517182219.2171814-1-broonie@kernel.org> <20220517182219.2171814-9-broonie@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220517182219.2171814-9-broonie@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220520_082648_946154_203042CE X-CRM114-Status: GOOD ( 14.13 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, May 17, 2022 at 07:22:18PM +0100, Mark Brown wrote: > Convert DCZID_EL0 to automatic register generation as per DDI0487H.a, no > functional change. > > Signed-off-by: Mark Brown > --- > arch/arm64/include/asm/sysreg.h | 2 -- > arch/arm64/tools/sysreg | 6 ++++++ > 2 files changed, 6 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e8e9040227f6..09dc437030f5 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -461,8 +461,6 @@ > #define SMIDR_EL1_SMPS_SHIFT 15 > #define SMIDR_EL1_AFFINITY_SHIFT 0 > > -#define SYS_DCZID_EL0 sys_reg(3, 3, 0, 0, 7) > - > #define SYS_RNDR_EL0 sys_reg(3, 3, 2, 4, 0) > #define SYS_RNDRRS_EL0 sys_reg(3, 3, 2, 4, 1) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > index 543ba10f3dac..1cd1e4ea42e3 100644 > --- a/arch/arm64/tools/sysreg > +++ b/arch/arm64/tools/sysreg > @@ -292,6 +292,12 @@ Res0 13:4 > Field 3:0 IminLine > EndSysreg > > +Sysreg DCZID_EL0 3 3 0 0 7 > +Res0 63:5 > +Field 4 DZP > +Field 3:0 BS > +EndSysreg These all look correct to me per ARM DDI 0487H.a pages D13-5340 to D13-5341. However, we have existing DCZID_DZP_SHIFT and DCZID_BS_SHIFT definitions that should be converted over: arch/arm64/include/asm/sysreg.h:#define DCZID_DZP_SHIFT 4 arch/arm64/include/asm/sysreg.h:#define DCZID_BS_SHIFT 0 arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_EXACT, DCZID_DZP_SHIFT, 1, 1), arch/arm64/kernel/cpufeature.c: ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, DCZID_BS_SHIFT, 4, 0), Mark. > + > Sysreg SVCR 3 3 4 2 2 > Res0 63:2 > Field 1 ZA > -- > 2.30.2 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel