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Date:   Sat, 21 May 2022 20:39:02 +0200
From:   Andrew Lunn <andrew@lunn.ch>
To:     Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
Cc:     michael@amarulasolutions.com, alberto.bianchi@amarulasolutions.com,
        linux-amarula@amarulasolutions.com, linuxfancy@googlegroups.com,
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        "David S. Miller" <davem@davemloft.net>,
        Eric Dumazet <edumazet@google.com>,
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        linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3] net: phy: DP83822: enable rgmii mode if
 phy_interface_is_rgmii
Message-ID: <YokxxlyFTJZ8c+5y@lunn.ch>
References: <20220520235846.1919954-1-tommaso.merciai@amarulasolutions.com>
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On Sat, May 21, 2022 at 01:58:46AM +0200, Tommaso Merciai wrote:
> RGMII mode can be enable from dp83822 straps, and also writing bit 9
> of register 0x17 - RMII and Status Register (RCSR).
> When phy_interface_is_rgmii rgmii mode must be enabled, same for
> contrary, this prevents malconfigurations of hw straps
> 
> References:
>  - https://www.ti.com/lit/gpn/dp83822i p66
> 
> Signed-off-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>
> Co-developed-by: Michael Trimarchi <michael@amarulasolutions.com>
> Suggested-by: Alberto Bianchi <alberto.bianchi@amarulasolutions.com>
> Tested-by: Tommaso Merciai <tommaso.merciai@amarulasolutions.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

If you want to, you could go further. If bit 9 is clear, bit 5 defines
the mode, either RMII or MII. There are interface modes defined for
these, so you could get bit 5 as well.

    Andrew