From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A303C433EF for ; Mon, 23 May 2022 11:38:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234970AbiEWLil (ORCPT ); Mon, 23 May 2022 07:38:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50492 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234883AbiEWLig (ORCPT ); Mon, 23 May 2022 07:38:36 -0400 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id EB2F743AC2; Mon, 23 May 2022 04:38:35 -0700 (PDT) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A09DD11FB; Mon, 23 May 2022 04:38:35 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.9.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 297CE3F73D; Mon, 23 May 2022 04:38:34 -0700 (PDT) Date: Mon, 23 May 2022 12:38:28 +0100 From: Mark Rutland To: Kefeng Wang Cc: elver@google.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, arnd@arndb.de Subject: Re: [PATCH v4 1/2] asm-generic: Add memory barrier dma_mb() Message-ID: References: <20220523113126.171714-1-wangkefeng.wang@huawei.com> <20220523113126.171714-2-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220523113126.171714-2-wangkefeng.wang@huawei.com> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, May 23, 2022 at 07:31:25PM +0800, Kefeng Wang wrote: > The memory barrier dma_mb() is introduced by commit a76a37777f2c > ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"), > which is used to ensure that prior (both reads and writes) accesses > to memory by a CPU are ordered w.r.t. a subsequent MMIO write. > > Reviewed-by: Arnd Bergmann # for asm-generic > Signed-off-by: Kefeng Wang FWIW, this looks sane to me so: Acked-by: Mark Rutland I'll leave the final say to Will, as I assume this'll go via the arm64 tree and he'll be the one picking this. Mark. > --- > Documentation/memory-barriers.txt | 11 ++++++----- > include/asm-generic/barrier.h | 8 ++++++++ > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index b12df9137e1c..832b5d36e279 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -1894,6 +1894,7 @@ There are some more advanced barrier functions: > > (*) dma_wmb(); > (*) dma_rmb(); > + (*) dma_mb(); > > These are for use with consistent memory to guarantee the ordering > of writes or reads of shared memory accessible to both the CPU and a > @@ -1925,11 +1926,11 @@ There are some more advanced barrier functions: > The dma_rmb() allows us guarantee the device has released ownership > before we read the data from the descriptor, and the dma_wmb() allows > us to guarantee the data is written to the descriptor before the device > - can see it now has ownership. Note that, when using writel(), a prior > - wmb() is not needed to guarantee that the cache coherent memory writes > - have completed before writing to the MMIO region. The cheaper > - writel_relaxed() does not provide this guarantee and must not be used > - here. > + can see it now has ownership. The dma_mb() implies both a dma_rmb() and > + a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed > + to guarantee that the cache coherent memory writes have completed before > + writing to the MMIO region. The cheaper writel_relaxed() does not provide > + this guarantee and must not be used here. > > See the subsection "Kernel I/O barrier effects" for more information on > relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > index fd7e8fbaeef1..961f4d88f9ef 100644 > --- a/include/asm-generic/barrier.h > +++ b/include/asm-generic/barrier.h > @@ -38,6 +38,10 @@ > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > #endif > > +#ifdef __dma_mb > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > +#endif > + > #ifdef __dma_rmb > #define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0) > #endif > @@ -65,6 +69,10 @@ > #define wmb() mb() > #endif > > +#ifndef dma_mb > +#define dma_mb() mb() > +#endif > + > #ifndef dma_rmb > #define dma_rmb() rmb() > #endif > -- > 2.35.3 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 37DD7C433EF for ; Mon, 23 May 2022 12:12:33 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=J4zgeQJK30CWhvsUmvadTsoGy1FxnrG2WUGwxhjXZ8s=; b=ZsEC9QBDr+q6aa ASuj83tDskJ9TaGuHO5mET2qYfxVyOFYwXrVqTgDU47veL2yjSByWaXjAV++A8h6wT2GtoYvrRbmK 7hsIXCjutiVBNP8NnDMbRG8MmBd3/21u953igZlfpo6ReaP1Z2hi/SmsOpwihgXWVcSsdnDkKabLs T0itYbPRN9206EUce4GCGf9Cp8tXyWzFYK+5ghVmym/wqtMWEorYN4VpzwdO+OlP7N7nA1JLJ9977 It3cvzNTfWu06nNp7EaM1hU0wHYZruWoe0Q0TtZgqB1RamYw//FaWh5kz78SEgspkPkDGja/VqTkI jlJ5U0jxwNQdbudIDiGA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt6tv-0040cj-PM; Mon, 23 May 2022 12:11:07 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nt6OS-003m1d-Dx for linux-arm-kernel@lists.infradead.org; Mon, 23 May 2022 11:38:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id A09DD11FB; Mon, 23 May 2022 04:38:35 -0700 (PDT) Received: from FVFF77S0Q05N (unknown [10.57.9.63]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 297CE3F73D; Mon, 23 May 2022 04:38:34 -0700 (PDT) Date: Mon, 23 May 2022 12:38:28 +0100 From: Mark Rutland To: Kefeng Wang Cc: elver@google.com, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonathan Corbet , linux-doc@vger.kernel.org, arnd@arndb.de Subject: Re: [PATCH v4 1/2] asm-generic: Add memory barrier dma_mb() Message-ID: References: <20220523113126.171714-1-wangkefeng.wang@huawei.com> <20220523113126.171714-2-wangkefeng.wang@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20220523113126.171714-2-wangkefeng.wang@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220523_043836_598302_2E4B4222 X-CRM114-Status: GOOD ( 27.19 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, May 23, 2022 at 07:31:25PM +0800, Kefeng Wang wrote: > The memory barrier dma_mb() is introduced by commit a76a37777f2c > ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"), > which is used to ensure that prior (both reads and writes) accesses > to memory by a CPU are ordered w.r.t. a subsequent MMIO write. > > Reviewed-by: Arnd Bergmann # for asm-generic > Signed-off-by: Kefeng Wang FWIW, this looks sane to me so: Acked-by: Mark Rutland I'll leave the final say to Will, as I assume this'll go via the arm64 tree and he'll be the one picking this. Mark. > --- > Documentation/memory-barriers.txt | 11 ++++++----- > include/asm-generic/barrier.h | 8 ++++++++ > 2 files changed, 14 insertions(+), 5 deletions(-) > > diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt > index b12df9137e1c..832b5d36e279 100644 > --- a/Documentation/memory-barriers.txt > +++ b/Documentation/memory-barriers.txt > @@ -1894,6 +1894,7 @@ There are some more advanced barrier functions: > > (*) dma_wmb(); > (*) dma_rmb(); > + (*) dma_mb(); > > These are for use with consistent memory to guarantee the ordering > of writes or reads of shared memory accessible to both the CPU and a > @@ -1925,11 +1926,11 @@ There are some more advanced barrier functions: > The dma_rmb() allows us guarantee the device has released ownership > before we read the data from the descriptor, and the dma_wmb() allows > us to guarantee the data is written to the descriptor before the device > - can see it now has ownership. Note that, when using writel(), a prior > - wmb() is not needed to guarantee that the cache coherent memory writes > - have completed before writing to the MMIO region. The cheaper > - writel_relaxed() does not provide this guarantee and must not be used > - here. > + can see it now has ownership. The dma_mb() implies both a dma_rmb() and > + a dma_wmb(). Note that, when using writel(), a prior wmb() is not needed > + to guarantee that the cache coherent memory writes have completed before > + writing to the MMIO region. The cheaper writel_relaxed() does not provide > + this guarantee and must not be used here. > > See the subsection "Kernel I/O barrier effects" for more information on > relaxed I/O accessors and the Documentation/core-api/dma-api.rst file for > diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h > index fd7e8fbaeef1..961f4d88f9ef 100644 > --- a/include/asm-generic/barrier.h > +++ b/include/asm-generic/barrier.h > @@ -38,6 +38,10 @@ > #define wmb() do { kcsan_wmb(); __wmb(); } while (0) > #endif > > +#ifdef __dma_mb > +#define dma_mb() do { kcsan_mb(); __dma_mb(); } while (0) > +#endif > + > #ifdef __dma_rmb > #define dma_rmb() do { kcsan_rmb(); __dma_rmb(); } while (0) > #endif > @@ -65,6 +69,10 @@ > #define wmb() mb() > #endif > > +#ifndef dma_mb > +#define dma_mb() mb() > +#endif > + > #ifndef dma_rmb > #define dma_rmb() rmb() > #endif > -- > 2.35.3 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel