From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A9DFCCCA481 for ; Thu, 23 Jun 2022 11:17:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230229AbiFWLRk (ORCPT ); Thu, 23 Jun 2022 07:17:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38682 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229595AbiFWLRj (ORCPT ); Thu, 23 Jun 2022 07:17:39 -0400 Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 170094B437; Thu, 23 Jun 2022 04:17:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983058; x=1687519058; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=5Z1glAH6RldXiFGaCnDodkfVEScRoth80xEGCnd7XKU=; b=Sf1gCsZK8z5Vq40daXHSbngDHDKKFUxKoJaPfULPZt0C2Nr59TfSjfP9 g1CMz98bmRssyygGjgN2rfQCEejOtE3QhVpn4WIFyophkbqiuAHNmEs7W zhNkL2JCR0YdxCdOnY98b+OAfbH49tTuUhEL1mRmXjo3J+AwLe1tvOMdD I1FY/3+MQqLm5fTf0+UXX3UO9W1O2hRJZW29W4e5MBNls/GzvgdF6SVQD MnKyS3RiXvjF66UZCLynx6ll6JldECHlaSTTR07jTSULDn072sHs79sUP pvnma3hEFPZSKsFVKJ8lT4fq7o7A3l5YvkU3ELBUt03YMvYH+z/nTFltV g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="278241099" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="278241099" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:37 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644690773" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:32 -0700 Date: Thu, 23 Jun 2022 13:17:30 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Cc: Chris Wilson , Fei Yang , Thomas Hellstrom , Bruce Chang , Daniel Vetter , Dave Airlie , David Airlie , Jani Nikula , John Harrison , Joonas Lahtinen , Matt Roper , Matthew Brost , Rodrigo Vivi , Tejas Upadhyay , Tvrtko Ursulin , Umesh Nerlige Ramappa , dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com, Mika Kuoppala , Chris Wilson , stable@vger.kernel.org, Thomas =?iso-8859-15?Q?Hellstr=F6m?= Subject: Re: [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Message-ID: References: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mauro, On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Don't allow two engines to be reset in parallel, as they would both > try to select a reset bit (and send requests to common registers) > and wait on that register, at the same time. Serialize control of > the reset requests/acks using the uncore->lock, which will also ensure > that no other GT state changes at the same time as the actual reset. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mika Kuoppala > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Andi Shyti > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 48F11CCA480 for ; Thu, 23 Jun 2022 11:17:41 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1548010EF81; Thu, 23 Jun 2022 11:17:40 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E10B10EF11; Thu, 23 Jun 2022 11:17:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983058; x=1687519058; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=5Z1glAH6RldXiFGaCnDodkfVEScRoth80xEGCnd7XKU=; b=Sf1gCsZK8z5Vq40daXHSbngDHDKKFUxKoJaPfULPZt0C2Nr59TfSjfP9 g1CMz98bmRssyygGjgN2rfQCEejOtE3QhVpn4WIFyophkbqiuAHNmEs7W zhNkL2JCR0YdxCdOnY98b+OAfbH49tTuUhEL1mRmXjo3J+AwLe1tvOMdD I1FY/3+MQqLm5fTf0+UXX3UO9W1O2hRJZW29W4e5MBNls/GzvgdF6SVQD MnKyS3RiXvjF66UZCLynx6ll6JldECHlaSTTR07jTSULDn072sHs79sUP pvnma3hEFPZSKsFVKJ8lT4fq7o7A3l5YvkU3ELBUt03YMvYH+z/nTFltV g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="279459354" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="279459354" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:37 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644690773" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:32 -0700 Date: Thu, 23 Jun 2022 13:17:30 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Subject: Re: [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Message-ID: References: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , dri-devel@lists.freedesktop.org, Chris Wilson , Fei Yang , Matthew Brost , Mika Kuoppala , Chris Wilson , Dave Airlie , Thomas =?iso-8859-15?Q?Hellstr=F6m?= , intel-gfx@lists.freedesktop.org, Thomas Hellstrom , Rodrigo Vivi , Tvrtko Ursulin , mauro.chehab@linux.intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Bruce Chang , Tejas Upadhyay , Umesh Nerlige Ramappa , John Harrison Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi Mauro, On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Don't allow two engines to be reset in parallel, as they would both > try to select a reset bit (and send requests to common registers) > and wait on that register, at the same time. Serialize control of > the reset requests/acks using the uncore->lock, which will also ensure > that no other GT state changes at the same time as the actual reset. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mika Kuoppala > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Andi Shyti > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 64604CCA47C for ; Thu, 23 Jun 2022 11:17:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BB0E310EF11; Thu, 23 Jun 2022 11:17:39 +0000 (UTC) Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E10B10EF11; Thu, 23 Jun 2022 11:17:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1655983058; x=1687519058; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=5Z1glAH6RldXiFGaCnDodkfVEScRoth80xEGCnd7XKU=; b=Sf1gCsZK8z5Vq40daXHSbngDHDKKFUxKoJaPfULPZt0C2Nr59TfSjfP9 g1CMz98bmRssyygGjgN2rfQCEejOtE3QhVpn4WIFyophkbqiuAHNmEs7W zhNkL2JCR0YdxCdOnY98b+OAfbH49tTuUhEL1mRmXjo3J+AwLe1tvOMdD I1FY/3+MQqLm5fTf0+UXX3UO9W1O2hRJZW29W4e5MBNls/GzvgdF6SVQD MnKyS3RiXvjF66UZCLynx6ll6JldECHlaSTTR07jTSULDn072sHs79sUP pvnma3hEFPZSKsFVKJ8lT4fq7o7A3l5YvkU3ELBUt03YMvYH+z/nTFltV g==; X-IronPort-AV: E=McAfee;i="6400,9594,10386"; a="279459354" X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="279459354" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:37 -0700 X-IronPort-AV: E=Sophos;i="5.92,215,1650956400"; d="scan'208";a="644690773" Received: from hazegrou-mobl.ger.corp.intel.com (HELO intel.com) ([10.251.216.121]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jun 2022 04:17:32 -0700 Date: Thu, 23 Jun 2022 13:17:30 +0200 From: Andi Shyti To: Mauro Carvalho Chehab Message-ID: References: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <5ee647f243a774927ec328bfca8212abc4957909.1655306128.git.mchehab@kernel.org> Subject: Re: [Intel-gfx] [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: David Airlie , dri-devel@lists.freedesktop.org, Chris Wilson , Chris Wilson , Dave Airlie , Thomas =?iso-8859-15?Q?Hellstr=F6m?= , intel-gfx@lists.freedesktop.org, Thomas Hellstrom , Rodrigo Vivi , mauro.chehab@linux.intel.com, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Tejas Upadhyay Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" Hi Mauro, On Wed, Jun 15, 2022 at 04:27:39PM +0100, Mauro Carvalho Chehab wrote: > From: Chris Wilson > > Don't allow two engines to be reset in parallel, as they would both > try to select a reset bit (and send requests to common registers) > and wait on that register, at the same time. Serialize control of > the reset requests/acks using the uncore->lock, which will also ensure > that no other GT state changes at the same time as the actual reset. > > Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store") > > Reported-by: Mika Kuoppala > Signed-off-by: Chris Wilson > Cc: Mika Kuoppala > Cc: Andi Shyti > Cc: stable@vger.kernel.org > Acked-by: Thomas Hellström > Signed-off-by: Mauro Carvalho Chehab Reviewed-by: Andi Shyti Thanks, Andi