From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 73A07C43334 for ; Mon, 27 Jun 2022 02:52:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231913AbiF0Cwk (ORCPT ); Sun, 26 Jun 2022 22:52:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231855AbiF0Cwj (ORCPT ); Sun, 26 Jun 2022 22:52:39 -0400 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 247593894 for ; Sun, 26 Jun 2022 19:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1656298357; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=JakvLevS0YnBGyhibLY4QkJ72ieVyrb1/yRcRNc1BYw=; b=W8ML5LPRh1Dp19WIipWlhBzHAMl6U9R34xgQRkHshJRBzphD5jF9eewHINnC5IFZLUcIoj zewTjSvAUlzMQEfXS0n1sqln+EWezQ5MZPthIFTCN/Rqif7QmA6OSjxk6WNYA9QwNhbanv TdqBcOKuPM0HJy8io1UwvkuNw9iqp7M= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-3-3tZgnw0DPyKkAw1P9ym7bg-1; Sun, 26 Jun 2022 22:52:32 -0400 X-MC-Unique: 3tZgnw0DPyKkAw1P9ym7bg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8B95D811E75; Mon, 27 Jun 2022 02:52:31 +0000 (UTC) Received: from localhost (ovpn-13-65.pek2.redhat.com [10.72.13.65]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B0D6F40CFD05; Mon, 27 Jun 2022 02:52:29 +0000 (UTC) Date: Mon, 27 Jun 2022 10:52:26 +0800 From: Baoquan He To: Catalin Marinas Cc: Kefeng Wang , Zhen Lei , Ard Biesheuvel , Mark Rutland , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H . Peter Anvin" , Eric Biederman , Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Dave Young , Vivek Goyal , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Chen Zhou , John Donnelly , Dave Kleikamp , liushixin Subject: Re: [PATCH 5/5] arm64: kdump: Don't defer the reservation of crash high memory Message-ID: References: <20220613080932.663-1-thunder.leizhen@huawei.com> <20220613080932.663-6-thunder.leizhen@huawei.com> <3f66323d-f371-b931-65fb-edfae0f01c88@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.11.54.1 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/23/22 at 03:07pm, Catalin Marinas wrote: > On Wed, Jun 22, 2022 at 04:35:16PM +0800, Baoquan He wrote: > > On 06/21/22 at 07:04pm, Catalin Marinas wrote: > > > The problem with splitting is that you can end up with two entries in > > > the TLB for the same VA->PA mapping (e.g. one for a 4KB page and another > > > for a 2MB block). In the lucky case, the CPU will trigger a TLB conflict > > > abort (but can be worse like loss of coherency). > > > > Thanks for this explanation. Is this a drawback of arm64 design? X86 > > code do the same thing w/o issue, is there way to overcome this on > > arm64 from hardware or software side? > > It is a drawback of the arm64 implementations. Having multiple TLB > entries for the same VA would need additional logic in hardware to > detect, so the microarchitects have pushed back. In ARMv8.4, some > balanced was reached with FEAT_BBM so that the only visible side-effect > is a potential TLB conflict abort that could be resolved by software. I see, thx. > > > I ever got a arm64 server with huge memory, w or w/o crashkernel setting > > have different bootup time. And the more often TLB miss and flush will > > cause performance cost. It is really a pity if we have very powerful > > arm64 cpu and system capacity, but bottlenecked by this drawback. > > Is it only the boot time affected or the runtime performance as well? Sorry for late reply. What I observerd is the boot time serious latecy with huge memory. Since the timestamp is not available at that time, we can't tell the number. I didn't notice the runtime performance. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6EDEAC43334 for ; Mon, 27 Jun 2022 02:52:50 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=W7KiOdnXEUp5f98nu16t7OPRgQ8eCt1DAkvOx84fLoc=; b=zK0GBGfdfL44DO pqhu6Hurls6LVYYbUOROaGbdr92a7lbweVa9JhKVXh/uALixzh1pPVlq0De959hjC7666Txn5OeFd lBFhJXyxk5XPlnUjip7EBbNpu4YC0ttIg+Rtc/TCQqYdRo5ExIdh3AzmPzJKOf5XfeMZjQJqvAr4T RpxA+UMVRlK4AjcMJ7rWFYH5TzxFe3zXCxkqzck0jrHLHa+uA+4s8SIJq4HS+uESj+29GJR55ZMMs gF3+AbF05k97bMhm8ljnnlJgLJfC7iTRgmN4GkVgGEWLCkl6fTWHc3LcizuixziQ9Q7bPX2xkyEQ5 xRNU91OH1m8havZX6kAg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5erj-00EnKd-Kj; Mon, 27 Jun 2022 02:52:43 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5erd-00EnHo-NC for kexec@lists.infradead.org; Mon, 27 Jun 2022 02:52:39 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1656298356; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=JakvLevS0YnBGyhibLY4QkJ72ieVyrb1/yRcRNc1BYw=; b=jNCD/kYs9UsjI6vXvS20lyqAhrDHrtzj+h7FZqI1c+09SbtCU6xd2XWxTLjE4YFr7+XJDA e3UqdTdJ3uFvf52u5vLaARzjyyu330MPXc0AGpHalNszSX4C6ZM4NNa0YWAZG2tigpBIPs KaIARRyAp0ZT14ycgoWqWlURPCf5CCA= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-3-3tZgnw0DPyKkAw1P9ym7bg-1; Sun, 26 Jun 2022 22:52:32 -0400 X-MC-Unique: 3tZgnw0DPyKkAw1P9ym7bg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8B95D811E75; Mon, 27 Jun 2022 02:52:31 +0000 (UTC) Received: from localhost (ovpn-13-65.pek2.redhat.com [10.72.13.65]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B0D6F40CFD05; Mon, 27 Jun 2022 02:52:29 +0000 (UTC) Date: Mon, 27 Jun 2022 10:52:26 +0800 From: Baoquan He To: Catalin Marinas Cc: Kefeng Wang , Zhen Lei , Ard Biesheuvel , Mark Rutland , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H . Peter Anvin" , Eric Biederman , Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Dave Young , Vivek Goyal , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Chen Zhou , John Donnelly , Dave Kleikamp , liushixin Subject: Re: [PATCH 5/5] arm64: kdump: Don't defer the reservation of crash high memory Message-ID: References: <20220613080932.663-1-thunder.leizhen@huawei.com> <20220613080932.663-6-thunder.leizhen@huawei.com> <3f66323d-f371-b931-65fb-edfae0f01c88@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.11.54.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220626_195237_952001_3CE44843 X-CRM114-Status: GOOD ( 26.36 ) X-BeenThere: kexec@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "kexec" Errors-To: kexec-bounces+kexec=archiver.kernel.org@lists.infradead.org On 06/23/22 at 03:07pm, Catalin Marinas wrote: > On Wed, Jun 22, 2022 at 04:35:16PM +0800, Baoquan He wrote: > > On 06/21/22 at 07:04pm, Catalin Marinas wrote: > > > The problem with splitting is that you can end up with two entries in > > > the TLB for the same VA->PA mapping (e.g. one for a 4KB page and another > > > for a 2MB block). In the lucky case, the CPU will trigger a TLB conflict > > > abort (but can be worse like loss of coherency). > > > > Thanks for this explanation. Is this a drawback of arm64 design? X86 > > code do the same thing w/o issue, is there way to overcome this on > > arm64 from hardware or software side? > > It is a drawback of the arm64 implementations. Having multiple TLB > entries for the same VA would need additional logic in hardware to > detect, so the microarchitects have pushed back. In ARMv8.4, some > balanced was reached with FEAT_BBM so that the only visible side-effect > is a potential TLB conflict abort that could be resolved by software. I see, thx. > > > I ever got a arm64 server with huge memory, w or w/o crashkernel setting > > have different bootup time. And the more often TLB miss and flush will > > cause performance cost. It is really a pity if we have very powerful > > arm64 cpu and system capacity, but bottlenecked by this drawback. > > Is it only the boot time affected or the runtime performance as well? Sorry for late reply. What I observerd is the boot time serious latecy with huge memory. Since the timestamp is not available at that time, we can't tell the number. I didn't notice the runtime performance. _______________________________________________ kexec mailing list kexec@lists.infradead.org http://lists.infradead.org/mailman/listinfo/kexec From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 73564C433EF for ; Mon, 27 Jun 2022 02:53:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References: Message-ID:Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=5PY999LIFjc0g4Go2FK/Xw/LFRgtXPSNiacQFvyd+ks=; b=h5NOHLsRmO8t7R yMwT0S8lICBUcXfapB/Wy0al6hNaT39dDx9qPiH+sNkMD76L4vUkRjyYYagsQIMjuqPK0d+Dk0sOF kMQVwojuYQrxNPLvTlLpRCOhwDh6oAsOL4JQhQHIDTn/msauzqe/8ewea8envNflbHL/MjG1uhI1L ifW1cZgpzZe2C5s2SNFFTaKKEmUcpBrbQNMMfz/TpmkuMsGuyzAZFsmKB1yW/7NsyJSwkJZ7Y6Jpt 1qFRRERFZtBM30+JNvQlasUtxLgg27DwbhhjZmUVVnB+VdYi1DUFWP8pP7qKicZKjBxtaonc9Q7Jm mZ86qWkGqyV3MO7Df//w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5erl-00EnN5-GX; Mon, 27 Jun 2022 02:52:45 +0000 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1o5ere-00EnIL-9B for linux-arm-kernel@lists.infradead.org; Mon, 27 Jun 2022 02:52:40 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1656298357; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: in-reply-to:in-reply-to:references:references; bh=JakvLevS0YnBGyhibLY4QkJ72ieVyrb1/yRcRNc1BYw=; b=W8ML5LPRh1Dp19WIipWlhBzHAMl6U9R34xgQRkHshJRBzphD5jF9eewHINnC5IFZLUcIoj zewTjSvAUlzMQEfXS0n1sqln+EWezQ5MZPthIFTCN/Rqif7QmA6OSjxk6WNYA9QwNhbanv TdqBcOKuPM0HJy8io1UwvkuNw9iqp7M= Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-3-3tZgnw0DPyKkAw1P9ym7bg-1; Sun, 26 Jun 2022 22:52:32 -0400 X-MC-Unique: 3tZgnw0DPyKkAw1P9ym7bg-1 Received: from smtp.corp.redhat.com (int-mx01.intmail.prod.int.rdu2.redhat.com [10.11.54.1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 8B95D811E75; Mon, 27 Jun 2022 02:52:31 +0000 (UTC) Received: from localhost (ovpn-13-65.pek2.redhat.com [10.72.13.65]) by smtp.corp.redhat.com (Postfix) with ESMTPS id B0D6F40CFD05; Mon, 27 Jun 2022 02:52:29 +0000 (UTC) Date: Mon, 27 Jun 2022 10:52:26 +0800 From: Baoquan He To: Catalin Marinas Cc: Kefeng Wang , Zhen Lei , Ard Biesheuvel , Mark Rutland , Thomas Gleixner , Ingo Molnar , Borislav Petkov , x86@kernel.org, "H . Peter Anvin" , Eric Biederman , Rob Herring , Frank Rowand , devicetree@vger.kernel.org, Dave Young , Vivek Goyal , kexec@lists.infradead.org, linux-kernel@vger.kernel.org, Will Deacon , linux-arm-kernel@lists.infradead.org, Jonathan Corbet , linux-doc@vger.kernel.org, Randy Dunlap , Feng Zhou , Chen Zhou , John Donnelly , Dave Kleikamp , liushixin Subject: Re: [PATCH 5/5] arm64: kdump: Don't defer the reservation of crash high memory Message-ID: References: <20220613080932.663-1-thunder.leizhen@huawei.com> <20220613080932.663-6-thunder.leizhen@huawei.com> <3f66323d-f371-b931-65fb-edfae0f01c88@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Scanned-By: MIMEDefang 2.84 on 10.11.54.1 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220626_195238_424724_3D5DEC4D X-CRM114-Status: GOOD ( 27.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 06/23/22 at 03:07pm, Catalin Marinas wrote: > On Wed, Jun 22, 2022 at 04:35:16PM +0800, Baoquan He wrote: > > On 06/21/22 at 07:04pm, Catalin Marinas wrote: > > > The problem with splitting is that you can end up with two entries in > > > the TLB for the same VA->PA mapping (e.g. one for a 4KB page and another > > > for a 2MB block). In the lucky case, the CPU will trigger a TLB conflict > > > abort (but can be worse like loss of coherency). > > > > Thanks for this explanation. Is this a drawback of arm64 design? X86 > > code do the same thing w/o issue, is there way to overcome this on > > arm64 from hardware or software side? > > It is a drawback of the arm64 implementations. Having multiple TLB > entries for the same VA would need additional logic in hardware to > detect, so the microarchitects have pushed back. In ARMv8.4, some > balanced was reached with FEAT_BBM so that the only visible side-effect > is a potential TLB conflict abort that could be resolved by software. I see, thx. > > > I ever got a arm64 server with huge memory, w or w/o crashkernel setting > > have different bootup time. And the more often TLB miss and flush will > > cause performance cost. It is really a pity if we have very powerful > > arm64 cpu and system capacity, but bottlenecked by this drawback. > > Is it only the boot time affected or the runtime performance as well? Sorry for late reply. What I observerd is the boot time serious latecy with huge memory. Since the timestamp is not available at that time, we can't tell the number. I didn't notice the runtime performance. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel