From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF646C19F2D for ; Tue, 9 Aug 2022 21:06:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229881AbiHIVGH (ORCPT ); Tue, 9 Aug 2022 17:06:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43234 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbiHIVFy (ORCPT ); Tue, 9 Aug 2022 17:05:54 -0400 Received: from mail-oa1-x29.google.com (mail-oa1-x29.google.com [IPv6:2001:4860:4864:20::29]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C72C4599E for ; Tue, 9 Aug 2022 14:05:49 -0700 (PDT) Received: by mail-oa1-x29.google.com with SMTP id 586e51a60fabf-10dc1b16c12so15488900fac.6 for ; Tue, 09 Aug 2022 14:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc; bh=46DbGyQMRqNHGkxsacJCotXRTrnXUBQPUgKwQCTQR8k=; b=hKJ9CRNm64FZ36uHItRlkf0idiXTuCMHIGEr6dAZWogMfifrszy0oFCa8H7K6Cah9D 55TjcK/iPn+BvOBQtb3mTI/51rUKzCQKkeAftF7q4oAP41j2EtShrtivvHKSpR5bfZer kKomkfpi78zEBQWdUTGBQsWZoO1hLcqLrubVg3hbnYziSqG7Np8t99DOzJt15uvfu4DH lIl3P/v4VaAuXaU2DVxn1GSS9n3BdSp8H0AaoYSW06MbcdfjeAjzYF6jJv0KLF0567nM IvcbioXxyho8pz1HTFTb4zgU+MfEOO3JI1a95UB3T4VXsLIsG9LxbQS1K6baKYW1BMBZ sV8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc; bh=46DbGyQMRqNHGkxsacJCotXRTrnXUBQPUgKwQCTQR8k=; b=oif4NDFmxvaIdaTQ7TSf9b0bciw9ND+LjQZrFEKZBJNe03WZjBUSNHvQ7f8a07iTb8 ha4OIghhqPuwZjXXpc3pyWbcDJk/lZ0Jz3kgM0JK4ullSAYIiKpmAMUUg9M8zJ1VHUxl CoV5PDDYCIHNZoUqn1P9zvDx/7bp30uvOzy/243NEblvGIANCEahyh5Cd27xnB+gV00g cFvmR3saMgE8QiVXGIbZamyUQ/caETwMa0pmMuvV+jaDNQdvYbyloMlauQwRQ2ytMEgi mwTO0DOr/faFC+At95QUApCnMDWE5cqpnTt2L+ptxOZ4mCTf+L/QxZwIPf9vgPsCNlpR ETew== X-Gm-Message-State: ACgBeo0J+hdFDLRN6uzHt4oWdQaRNnu+yd3hIpOm2/CRriVYksiHBkSx ptZiZuSk88u3ezWacB3wgpG9PQ== X-Google-Smtp-Source: AA6agR7/jfhQKdcyS9t/lnwAnJxheoLryGMKECjJwkUJ1IJiQ9e3xVupz1MV7wbT5OutnB3H7N+IWA== X-Received: by 2002:a05:6870:5818:b0:116:a478:7f6a with SMTP id r24-20020a056870581800b00116a4787f6amr170549oap.204.1660079148210; Tue, 09 Aug 2022 14:05:48 -0700 (PDT) Received: from baldur ([2600:380:785a:7aa8:200:ff:fe00:0]) by smtp.gmail.com with ESMTPSA id s70-20020acaa949000000b0032e3cca8561sm214842oie.21.2022.08.09.14.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 14:05:47 -0700 (PDT) Date: Tue, 9 Aug 2022 16:05:43 -0500 From: Bjorn Andersson To: Akhil P Oommen Cc: freedreno , dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, Rob Clark , Stephen Boyd , Douglas Anderson , Andy Gross , Konrad Dybcio , Krzysztof Kozlowski , Michael Turquette , Philipp Zabel , Rob Herring , Stephen Boyd , devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface Message-ID: References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Sat 30 Jul 04:17 CDT 2022, Akhil P Oommen wrote: > > Some clients like adreno gpu driver would like to ensure that its gdsc > is collapsed at hardware during a gpu reset sequence. This is because it > has a votable gdsc which could be ON due to a vote from another subsystem > like tz, hyp etc or due to an internal hardware signal. To allow > this, gpucc driver can expose an interface to the client driver using > reset framework. Using this the client driver can trigger a polling within > the gdsc driver. > > This series is rebased on top of linus's master branch. > > Related discussion: https://patchwork.freedesktop.org/patch/493144/ > Forgive me if I'm assuming too much, but isn't this an extension of: 85a3d920d30a ("clk: qcom: Add a dummy enable function for GX gdsc") With the additional requirement that disable should really ensure that the GDSC is turned off? Regards, Bjorn > > Akhil P Oommen (5): > dt-bindings: clk: qcom: Support gpu cx gdsc reset > clk: qcom: Allow custom reset ops > clk: qcom: gpucc-sc7280: Add cx collapse reset support > clk: qcom: gdsc: Add a reset op to poll gdsc collapse > arm64: dts: qcom: sc7280: Add Reset support for gpu > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ > drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- > drivers/clk/qcom/gdsc.h | 7 +++++++ > drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++ > drivers/clk/qcom/reset.c | 6 ++++++ > drivers/clk/qcom/reset.h | 2 ++ > include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ > 7 files changed, 46 insertions(+), 4 deletions(-) > > -- > 2.7.4 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5E247C19F2D for ; Tue, 9 Aug 2022 21:06:06 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 429EFC83B1; Tue, 9 Aug 2022 21:06:00 +0000 (UTC) Received: from mail-oa1-x33.google.com (mail-oa1-x33.google.com [IPv6:2001:4860:4864:20::33]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8CCD3C83DC for ; Tue, 9 Aug 2022 21:05:49 +0000 (UTC) Received: by mail-oa1-x33.google.com with SMTP id 586e51a60fabf-10cf9f5b500so15509784fac.2 for ; Tue, 09 Aug 2022 14:05:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:from:to:cc; bh=46DbGyQMRqNHGkxsacJCotXRTrnXUBQPUgKwQCTQR8k=; b=hKJ9CRNm64FZ36uHItRlkf0idiXTuCMHIGEr6dAZWogMfifrszy0oFCa8H7K6Cah9D 55TjcK/iPn+BvOBQtb3mTI/51rUKzCQKkeAftF7q4oAP41j2EtShrtivvHKSpR5bfZer kKomkfpi78zEBQWdUTGBQsWZoO1hLcqLrubVg3hbnYziSqG7Np8t99DOzJt15uvfu4DH lIl3P/v4VaAuXaU2DVxn1GSS9n3BdSp8H0AaoYSW06MbcdfjeAjzYF6jJv0KLF0567nM IvcbioXxyho8pz1HTFTb4zgU+MfEOO3JI1a95UB3T4VXsLIsG9LxbQS1K6baKYW1BMBZ sV8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-disposition:mime-version:references:message-id :subject:cc:to:from:date:x-gm-message-state:from:to:cc; bh=46DbGyQMRqNHGkxsacJCotXRTrnXUBQPUgKwQCTQR8k=; b=2dZA5Hy01PmupJaEp6borLoh/pMbHi8xdcvymD6nlwTO9+crhTFvxjKv8OGpvnXXrs 1y4284KueoFvD7z/9NxiJH4enj45u51gjyQViHcOhysOgOP0hTEqRtMwMuPBDY8D0jAs 7EFb6sSI9n0/gn6D/uyBsdK+F30idDsgWKzfHGpJ7+7ld34i2itQw4+aVX1OSgu/ZWn+ b420iMxlVNT8tb9cchh66CM3SGCp3FcYJqgXKNMDmdW6u1fUvD1MnAiqKGr5y6EmMo+n CQCQPAJuWqDITmjsKDbIHgetxC7OSQmBBuYO2oBbYqP1RWOZoAEVy4RXFBPGtOccCS8C Wurw== X-Gm-Message-State: ACgBeo0U9liD1pIXrRHsVUQxGFXuu/dBlhCYM9kpSzPmIBy9B9AFdtz5 +PTU/o1Kx1yeMWoURrafFZfBrg== X-Google-Smtp-Source: AA6agR7/jfhQKdcyS9t/lnwAnJxheoLryGMKECjJwkUJ1IJiQ9e3xVupz1MV7wbT5OutnB3H7N+IWA== X-Received: by 2002:a05:6870:5818:b0:116:a478:7f6a with SMTP id r24-20020a056870581800b00116a4787f6amr170549oap.204.1660079148210; Tue, 09 Aug 2022 14:05:48 -0700 (PDT) Received: from baldur ([2600:380:785a:7aa8:200:ff:fe00:0]) by smtp.gmail.com with ESMTPSA id s70-20020acaa949000000b0032e3cca8561sm214842oie.21.2022.08.09.14.05.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 09 Aug 2022 14:05:47 -0700 (PDT) Date: Tue, 9 Aug 2022 16:05:43 -0500 From: Bjorn Andersson To: Akhil P Oommen Subject: Re: [PATCH 0/5] clk/qcom: Support gdsc collapse polling using 'reset' inteface Message-ID: References: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1659172664-10345-1-git-send-email-quic_akhilpo@quicinc.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Stephen Boyd , linux-arm-msm@vger.kernel.org, Michael Turquette , Konrad Dybcio , Douglas Anderson , dri-devel@lists.freedesktop.org, Stephen Boyd , Rob Herring , Andy Gross , Krzysztof Kozlowski , freedreno , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Sat 30 Jul 04:17 CDT 2022, Akhil P Oommen wrote: > > Some clients like adreno gpu driver would like to ensure that its gdsc > is collapsed at hardware during a gpu reset sequence. This is because it > has a votable gdsc which could be ON due to a vote from another subsystem > like tz, hyp etc or due to an internal hardware signal. To allow > this, gpucc driver can expose an interface to the client driver using > reset framework. Using this the client driver can trigger a polling within > the gdsc driver. > > This series is rebased on top of linus's master branch. > > Related discussion: https://patchwork.freedesktop.org/patch/493144/ > Forgive me if I'm assuming too much, but isn't this an extension of: 85a3d920d30a ("clk: qcom: Add a dummy enable function for GX gdsc") With the additional requirement that disable should really ensure that the GDSC is turned off? Regards, Bjorn > > Akhil P Oommen (5): > dt-bindings: clk: qcom: Support gpu cx gdsc reset > clk: qcom: Allow custom reset ops > clk: qcom: gpucc-sc7280: Add cx collapse reset support > clk: qcom: gdsc: Add a reset op to poll gdsc collapse > arm64: dts: qcom: sc7280: Add Reset support for gpu > > arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +++ > drivers/clk/qcom/gdsc.c | 23 +++++++++++++++++++---- > drivers/clk/qcom/gdsc.h | 7 +++++++ > drivers/clk/qcom/gpucc-sc7280.c | 6 ++++++ > drivers/clk/qcom/reset.c | 6 ++++++ > drivers/clk/qcom/reset.h | 2 ++ > include/dt-bindings/clock/qcom,gpucc-sc7280.h | 3 +++ > 7 files changed, 46 insertions(+), 4 deletions(-) > > -- > 2.7.4 >