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From: Robert Richter <rrichter@amd.com>
To: Dan Williams <dan.j.williams@intel.com>
Cc: Alison Schofield <alison.schofield@intel.com>,
	Vishal Verma <vishal.l.verma@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Ben Widawsky <bwidawsk@kernel.org>, <linux-cxl@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	Bjorn Helgaas <bhelgaas@google.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	Len Brown <lenb@kernel.org>
Subject: Re: [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block()
Date: Fri, 9 Sep 2022 14:19:11 +0200	[thread overview]
Message-ID: <YxsvPwzxoYBMnN2y@rric.localdomain> (raw)
In-Reply-To: <6319824968fa7_580162946f@dwillia2-xfh.jf.intel.com.notmuch>

On 07.09.22 22:48:57, Dan Williams wrote:
> Robert Richter wrote:
> > The physical base address of a CXL range can be invalid and is then
> > set to CXL_RESOURCE_NONE. Early check this case before mapping a
> > memory block in devm_cxl_iomap_block().
> > 
> > Signed-off-by: Robert Richter <rrichter@amd.com>
> > ---
> >  drivers/cxl/core/regs.c | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/drivers/cxl/core/regs.c b/drivers/cxl/core/regs.c
> > index 39a129c57d40..f216c017a474 100644
> > --- a/drivers/cxl/core/regs.c
> > +++ b/drivers/cxl/core/regs.c
> > @@ -165,6 +165,9 @@ void __iomem *devm_cxl_iomap_block(struct device *dev, resource_size_t addr,
> >  	void __iomem *ret_val;
> >  	struct resource *res;
> >  
> > +	if (addr == CXL_RESOURCE_NONE)
> > +		return NULL;
> > +
> >  	res = devm_request_mem_region(dev, addr, length, dev_name(dev));
> >  	if (!res) {
> >  		resource_size_t end = addr + length - 1;
> > -- 
> > 2.30.2
> > 
> 
> devm_request_mem_region() succeeds for you when this happens? More
> details about the failure scenario please.

No, CXL_RESOURCE_NONE (all FFs) is used as address. A broken range is
calculated that even overflows. I only vaguely remember the exact
error message.

This may happen e.g. if the Component Register Block is missing in the
DVSEC. cxl_find_regblock() may fail then and returns
CXL_RESOURCE_NONE. There are a couple of code paths there
component_reg_phys is set to CXL_RESOURCE_NONE without exiting
immediately.

I saw it during code development, when I pre-inititalized a port with
component_reg_phys set to CXL_RESOURCE_NONE. Since that case can
generally happen, I think it must be checked.

-Robert

  reply	other threads:[~2022-09-09 12:21 UTC|newest]

Thread overview: 102+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-08-31  8:15 [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Robert Richter
2022-08-31  8:15 ` [PATCH 01/15] cxl/core: Remove duplicate declaration of devm_cxl_iomap_block() Robert Richter
2022-08-31  8:54   ` Jonathan Cameron
2022-09-01  5:21     ` Robert Richter
2022-08-31  9:39   ` kernel test robot
2022-09-07 16:11   ` [PATCH 1/15] " Davidlohr Bueso
2022-09-09 10:38     ` Robert Richter
2022-09-08  5:44   ` [PATCH 01/15] " Dan Williams
2022-09-08 14:51     ` Robert Richter
2022-09-08 19:47       ` Dan Williams
2022-08-31  8:15 ` [PATCH 02/15] cxl/core: Check physical address before mapping it in devm_cxl_iomap_block() Robert Richter
2022-08-31  8:56   ` Jonathan Cameron
2022-09-01  5:31     ` Robert Richter
2022-09-08  5:48   ` Dan Williams
2022-09-09 12:19     ` Robert Richter [this message]
2022-09-16 18:04       ` Dan Williams
2022-09-28 10:28         ` Robert Richter
2022-09-30 19:07           ` Dan Williams
2022-08-31  8:15 ` [PATCH 03/15] cxl: Unify debug messages when calling devm_cxl_add_port() Robert Richter
2022-08-31  9:59   ` Jonathan Cameron
2022-09-01  5:36     ` Robert Richter
2022-09-06  7:30     ` Robert Richter
2022-09-06  8:52       ` Jonathan Cameron
2022-09-07 16:21   ` [PATCH 3/15] " Davidlohr Bueso
2022-09-08  5:53   ` [PATCH 03/15] " Dan Williams
2022-09-28 10:32     ` Robert Richter
2022-08-31  8:15 ` [PATCH 04/15] cxl: Unify debug messages when calling devm_cxl_add_dport() Robert Richter
2022-09-07 16:29   ` [PATCH 4/15] " Davidlohr Bueso
2022-09-08  5:55   ` [PATCH 04/15] " Dan Williams
2022-08-31  8:15 ` [PATCH 05/15] cxl/acpi: Add probe function to detect restricted CXL hosts in RCD mode Robert Richter
2022-08-31 10:08   ` Jonathan Cameron
2022-09-01  6:01     ` Robert Richter
2022-09-01 10:10       ` Jonathan Cameron
2022-09-06  7:19         ` Robert Richter
2022-09-06  8:53           ` Jonathan Cameron
2022-09-07 18:22   ` Bjorn Helgaas
2022-09-08  6:00   ` Dan Williams
2022-09-08  6:11   ` Dan Williams
2022-08-31  8:15 ` [PATCH 06/15] PCI/ACPI: Link host bridge to its ACPI fw node Robert Richter
2022-08-31 10:11   ` Jonathan Cameron
2022-09-07 18:37   ` Bjorn Helgaas
2022-09-07 20:15     ` Rafael J. Wysocki
2022-09-08  6:05   ` Dan Williams
2022-09-08 13:06     ` Rafael J. Wysocki
2022-09-08 19:45       ` Dan Williams
2022-09-09 10:20         ` Robert Richter
2022-09-14 22:11           ` Bjorn Helgaas
2022-09-16 23:16             ` Dan Williams
2022-09-08 13:04   ` Rafael J. Wysocki
2022-08-31  8:15 ` [PATCH 07/15] cxl/acpi: Check RCH's PCIe Host Bridge ACPI ID Robert Richter
2022-08-31 10:20   ` Jonathan Cameron
2022-09-01  6:16     ` Robert Richter
2022-09-01 10:14       ` Jonathan Cameron
2022-09-08  6:11   ` Dan Williams
2022-08-31  8:15 ` [PATCH 08/15] cxl/acpi: Check RCH's CXL DVSEC capabilities Robert Richter
2022-08-31 10:52   ` Jonathan Cameron
2022-08-31 11:12     ` Jonathan Cameron
2022-09-01  6:38       ` Robert Richter
2022-09-01 10:37         ` Jonathan Cameron
2022-09-06 10:20           ` Robert Richter
2022-09-01  6:30     ` Robert Richter
2022-09-01 10:23       ` Jonathan Cameron
2022-09-08  6:18   ` Dan Williams
2022-08-31  8:15 ` [PATCH 09/15] cxl/acpi: Determine PCI host bridge's ACPI UID Robert Richter
2022-08-31 11:00   ` Jonathan Cameron
2022-09-01  6:53     ` Robert Richter
2022-09-01 10:41       ` Jonathan Cameron
2022-09-08  6:18   ` Dan Williams
2022-09-08 20:47   ` Jonathan Zhang (Infra)
2022-09-08 21:10     ` Dan Williams
2022-09-08 21:35       ` Jonathan Zhang (Infra)
2022-09-08 22:31         ` Dan Williams
2022-09-08 22:41           ` Jonathan Zhang (Infra)
2022-08-31  8:15 ` [PATCH 10/15] cxl/acpi: Extract the RCH's RCRB base address from CEDT Robert Richter
2022-08-31 11:09   ` Jonathan Cameron
2022-09-01  7:04     ` Robert Richter
2022-08-31  8:15 ` [PATCH 11/15] cxl/acpi: Extract the host's component register base address from RCRB Robert Richter
2022-08-31 11:56   ` Jonathan Cameron
2022-09-01  7:38     ` Robert Richter
2022-09-01 11:00       ` Jonathan Cameron
2022-09-06 11:32         ` Robert Richter
2022-09-08 20:59   ` Jonathan Zhang (Infra)
2022-08-31  8:16 ` [PATCH 12/15] cxl/acpi: Skip devm_cxl_port_enumerate_dports() when in RCD mode Robert Richter
2022-08-31 11:58   ` Jonathan Cameron
2022-09-01  7:40     ` Robert Richter
2022-08-31  8:16 ` [PATCH 13/15] cxl/acpi: Rework devm_cxl_enumerate_ports() to support " Robert Richter
2022-08-31 12:11   ` Jonathan Cameron
2022-09-01  7:50     ` Robert Richter
2022-08-31  8:16 ` [PATCH 14/15] cxl/acpi: Enumerate ports in RCD mode to enable RCHs and RCDs Robert Richter
2022-08-31 12:16   ` Jonathan Cameron
2022-09-01  7:54     ` Robert Richter
2022-08-31  8:16 ` [PATCH 15/15] cxl/acpi: Specify module load order dependency for the cxl_acpi module Robert Richter
2022-09-16 18:12   ` Dan Williams
2022-08-31 12:23 ` [PATCH 00/15] cxl: Add support for Restricted CXL hosts (RCD mode) Jonathan Cameron
2022-09-01  8:19   ` Robert Richter
2022-09-08  6:41     ` Dan Williams
2022-09-08  5:43 ` Dan Williams
2022-09-08 18:52   ` Jonathan Zhang (Infra)
2022-09-08 19:51     ` Dan Williams
2022-09-08 20:36       ` Jonathan Zhang (Infra)
2022-09-08 21:02         ` Dan Williams
2022-09-16 18:16 ` Dan Williams

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