Hi,

> v2->v3:
>  * Renamed the variable new_clock_margin->new_upper_limit in renesas_sdhi_clk_
>    update()
>  * Moved setting of new_upper_limit outside for loop.
>  * Updated the comment section to mention the rounding errors and merged with
>    existing comment out side the for loop.
>  * Updated commit description. 

I really like the new variable names.

> +	 * To fix rounding errors, eg:- (533333333 Hz / 4 * 4 = 533333332 Hz <

(What is the '-' after 'eg:' for?)

> +	 * 533333333 Hz) add an upper limit of 1/1024 rate higher to the clock
> +	 * rate.

I know Geert suggesgted this. I think, however, this description is too
short. It should be mentioned IMHO that this rounding error can lead to
the selection of a clock which is way off (the 400MHz one). I liked this
example from v2. Geert, what do you say?

Happy hacking,

   Wolfram