Re: [PATCH] drm/fourcc: add Vivante tile status modifiers

["Guido Günther" <agx@sigxcpu.org>]

Hi,
On Fri, Sep 09, 2022 at 11:30:00AM +0200, Lucas Stach wrote:
> The tile status modifiers can be combined with all of the usual
> color buffer modifiers. When they are present an additional plane
> is added to the surfaces to share the tile status buffer. The
> TS modifiers describe the interpretation of the tag bits in this
> buffer.
> 
> Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
> ---
>  include/uapi/drm/drm_fourcc.h | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 0980678d502d..93b022498900 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -718,6 +718,35 @@ extern "C" {
>   */
>  #define DRM_FORMAT_MOD_VIVANTE_SPLIT_SUPER_TILED fourcc_mod_code(VIVANTE, 4)
>  
> +/*
> + * Vivante TS (tile-status) buffer modifiers. They can be combined with all of
> + * the color buffer tiling modifiers defined above. When TS is present it's a
> + * separate buffer containing the clear/compression status of each tile. The
> + * modifiers are defined as VIVANTE_MOD_TS_c_s, where c is the color buffer
> + * tile size in bytes covered by one entry in the status buffer and s is the
> + * number of status bits per entry.
> + * We reserve the top 8 bits of the Vivante modifier space for tile status
> + * clear/compression modifiers, as future cores might add some more TS layout
> + * variations.
> + */
> +#define VIVANTE_MOD_TS_64_4               (1ULL << 48)
> +#define VIVANTE_MOD_TS_64_2               (2ULL << 48)
> +#define VIVANTE_MOD_TS_128_4              (3ULL << 48)
> +#define VIVANTE_MOD_TS_256_4              (4ULL << 48)
> +#define VIVANTE_MOD_TS_MASK               (0xfULL << 48)
> +
> +/*
> + * Vivante compression modifiers. Those depend on a TS modifier being present
> + * as the TS bits get reinterpreted as compression tags instead of simple
> + * clear markers when compression is enabled.
> + */
> +#define VIVANTE_MOD_COMP_DEC400           (1ULL << 52)
> +#define VIVANTE_MOD_COMP_MASK             (0xfULL << 52)
> +
> +/* Masking out the extension bits will yield the base modifier. */
> +#define VIVANTE_MOD_EXT_MASK              (VIVANTE_MOD_TS_MASK | \
> +                                           VIVANTE_MOD_COMP_MASK)
> +
>  /* NVIDIA frame buffer modifiers */
>  
>  /*


Reviewed-by: Guido Günther <agx@sigxcpu.org>

Cheers,
 -- Guido