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[82.30.61.225]) by smtp.gmail.com with ESMTPSA id t1-20020a0560001a4100b0022cd539ce5esm166490wry.50.2022.09.29.12.16.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Sep 2022 12:16:50 -0700 (PDT) Date: Thu, 29 Sep 2022 20:16:48 +0100 From: "Dr. David Alan Gilbert" To: Palmer Dabbelt Cc: qemu-devel@nongnu.org Subject: Re: [PATCH] RISC-V: Add support for Ztso Message-ID: References: <20220902034412.8918-1-palmer@rivosinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20220902034412.8918-1-palmer@rivosinc.com> User-Agent: Mutt/2.2.7 (2022-08-07) Received-SPF: pass client-ip=170.10.129.124; envelope-from=dgilbert@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.08, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" * Palmer Dabbelt (palmer@rivosinc.com) wrote: > Ztso, the RISC-V extension that provides the TSO memory model, was > recently frozen. This provides support for Ztso on targets that are > themselves TSO. > > Signed-off-by: Palmer Dabbelt > > --- > > diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h > index 00fcbe297d..2a43d54fcd 100644 > --- a/tcg/i386/tcg-target.h > +++ b/tcg/i386/tcg-target.h > @@ -236,6 +236,7 @@ static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, > #include "tcg/tcg-mo.h" > > #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) > +#define TCG_TARGET_SUPPORTS_MCTCG_RVTSO 1 Is x86's brand of memory ordering strong enough for Ztso? I thought x86 had an optimisation where it was allowed to store forward within the current CPU causing stores not to be quite strictly ordered. Dave > #define TCG_TARGET_HAS_MEMORY_BSWAP have_movbe > > diff --git a/tcg/s390x/tcg-target.h b/tcg/s390x/tcg-target.h > index 23e2063667..f423c124a0 100644 > --- a/tcg/s390x/tcg-target.h > +++ b/tcg/s390x/tcg-target.h > @@ -171,6 +171,7 @@ extern uint64_t s390_facilities[3]; > #define TCG_TARGET_HAS_MEMORY_BSWAP 1 > > #define TCG_TARGET_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) > +#define TCG_TARGET_SUPPORTS_MCTCG_RVTSO 1 > > static inline void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_rx, > uintptr_t jmp_rw, uintptr_t addr) > -- > 2.34.1 > > -- Dr. David Alan Gilbert / dgilbert@redhat.com / Manchester, UK