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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Cup7iCCv+D8jjiBRaDVfmBtZ75A8oOE06AUNfxTjfq3f4CBtxiGO6vMYz/XU?= =?us-ascii?Q?mPaKN/0ThXpYDG99IFqhxLP136PmlRKuJmzvs+mbZNlsBmuw/raMLg8gGpyt?= =?us-ascii?Q?Lv7+h3uk1BEAUXyQ1rOa4HcljK5ho2x+GyPxrpCjDQMlZCA3SaT269l2KDYm?= =?us-ascii?Q?25IbsuKLrAwTzr8uPhsLjVvjZcGGMOSDVJ1VqkL3CZTC38Eg/XKvqe9fLrcF?= =?us-ascii?Q?N/NQVeZCLptw1yP04sOBXdIh2/Rs+1n0KXRXH5eHPjshTBDsRldX1knrcWu2?= =?us-ascii?Q?Z3vQAg1ZDQCbO2JrXEvv9bz1RlxRLPnOJLYPo+w1/iH4PSP+NcINwLC5i9tL?= =?us-ascii?Q?FGweNuWJBOxrUuFYHwH3XBT4yZmAdiWA0o5y+/Ldh52LKfiFlKIutc3IBVMG?= =?us-ascii?Q?0h5UcYhYPTVW7yMvuCD4OZjG4pLsvjfvARq7pZZExRhFGJBsmae72NP24ixB?= =?us-ascii?Q?mwGZldbV1bIJuUY3hLBUZbS4pjF4gbFl4g6nAORpWj4NP8kIX1xqpUurl3IA?= =?us-ascii?Q?7mYG6UClejyhf1gG9VYVbi2+dBI8npWbU8nhfeFgatIrVE+PeQEe/YLisoZ8?= =?us-ascii?Q?W/ShH0NzgLLpy/qrwH9pqGpbVpHLRfxtnXQmjal+7csyjsX5dIp9k+Bm049+?= =?us-ascii?Q?nfOKD9uEIvaVe+znMmLOVmULFfxNQtHJ8n7JxMwRt0pXheqYWZdxDn30G7Wo?= =?us-ascii?Q?Gk2IdXHGNcnMZ/T68LkpoW4D+4YCUu1KLaJ1ce5f238N09P1bOfe81xzk4Yv?= =?us-ascii?Q?NE+MN4d+/fvcb25vaGmcyBa8nlvQ+fKMhHjgHQ+OTc7qfviAsSqCTUFSBDoF?= =?us-ascii?Q?1uUJOMKpwDZbzXN13p2+ilQEClucRoZWl53WUOSH+DHn0FvCUIj1vnlYXVYa?= =?us-ascii?Q?G+by8/SrSu2iXZGwgrFHESIkzYYSSSRdF+cKYooppV45JihkAv/FDBp7BtpM?= =?us-ascii?Q?9Dqm/Cse9zhSfcXIFRXHLEH5e0SdfL2r7f7tc1lcapLMm45GAfEsYK0F00mj?= =?us-ascii?Q?9nyGVEvZlrzU3HUGu+yxlqS7MwGIYYSVOWHw1rLl4KEIAKChMZpg1kEsiKhG?= =?us-ascii?Q?s8Hw0V/pi1lkfntBMvPzWMZ0ZnqUbxq5YdDbVKfQzMlTze+9j002+veQH8xT?= =?us-ascii?Q?pqJ0Znp51QQuivy2uZdfWe4CwvStxAO/WyW/7LeHHJQiUiz2cLvNrdB5hFpx?= =?us-ascii?Q?ScNg2kSTwYj1GmuKFfmeW5hmQ1xQdMV6D5xsySRZeoIr21bZuPpmYuGmW19P?= =?us-ascii?Q?yywDUw6cYCLKrQ3WwSuMKll+6O9injDCT2zyE2HlZ/HnwfoWP3M2193tQRxC?= =?us-ascii?Q?lvwenE65nZxdXiE6FKB7iNHs647rAv7CmKR193iBis4JElPvhSmikVueQDCv?= =?us-ascii?Q?YkYS3o4GhcTOOQkWPTkKjzY/sB2B/KkkMHZjVulthn7ivaXAA4VXLrtrZ2UW?= =?us-ascii?Q?WDtuX2zSjQdvEMmJen+LYlNSfC7q+odBEMd+so4xbkYfv1Wc/MtEYFgRNgDH?= =?us-ascii?Q?Oxh0irGZa6iQ+dpSdDUUYH9PxW2rEGdKSfFEEns5RTyoNPXIYJhW5hr5KLzj?= =?us-ascii?Q?cKV37urFuE2fcjt1Y83FfsyL7UiP+VF+hI0GeR3E?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5d0f7fb8-bed3-4d59-e51f-08db2bb26823 X-MS-Exchange-CrossTenant-AuthSource: BN8PR12MB3108.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 23 Mar 2023 15:22:25.6756 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: TaWpWs6bCLQLBWJaXdLF2YmlgWEjlmvnnuvjbBkfl1KZ2OdMTIs4PJSas5oXWsBZDhTZja4gooQs8f8xbVMJgQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7537 On Fri, Mar 17, 2023 at 10:20:40AM -0700, Tony Luck wrote: > From: Smita Koralahalli > > Intel and AMD need to take different actions when a storm begins or > ends. Prepare for the storm code moving from intel.c into core.c by > adding a function that checks CPU vendor to pick the right action. > > No functional changes. > > [Tony: Changed from function pointer to regular function] > > Signed-off-by: Smita Koralahalli > Signed-off-by: Tony Luck > --- > arch/x86/kernel/cpu/mce/internal.h | 3 +++ > arch/x86/kernel/cpu/mce/core.c | 9 +++++++++ > arch/x86/kernel/cpu/mce/intel.c | 12 ++++++++++-- > 3 files changed, 22 insertions(+), 2 deletions(-) > > diff --git a/arch/x86/kernel/cpu/mce/internal.h b/arch/x86/kernel/cpu/mce/internal.h > index 72fbec8f6c3c..f37816b4d4cf 100644 > --- a/arch/x86/kernel/cpu/mce/internal.h > +++ b/arch/x86/kernel/cpu/mce/internal.h > @@ -43,12 +43,14 @@ extern mce_banks_t mce_banks_ce_disabled; > void track_cmci_storm(int bank, u64 status); > > #ifdef CONFIG_X86_MCE_INTEL > +void mce_intel_handle_storm(int bank, bool on); > void cmci_disable_bank(int bank); > void intel_init_cmci(void); > void intel_init_lmce(void); > void intel_clear_lmce(void); > bool intel_filter_mce(struct mce *m); > #else > +static inline void mce_intel_handle_storm(int bank, bool on) { } > static inline void cmci_disable_bank(int bank) { } > static inline void intel_init_cmci(void) { } > static inline void intel_init_lmce(void) { } > @@ -57,6 +59,7 @@ static inline bool intel_filter_mce(struct mce *m) { return false; } > #endif > > void mce_timer_kick(bool storm); > +void mce_handle_storm(int bank, bool on); > > #ifdef CONFIG_ACPI_APEI > int apei_write_mce(struct mce *m); > diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c > index 776d4724b1e0..f4d2a7ba29f7 100644 > --- a/arch/x86/kernel/cpu/mce/core.c > +++ b/arch/x86/kernel/cpu/mce/core.c > @@ -1985,6 +1985,15 @@ static void mce_zhaoxin_feature_clear(struct cpuinfo_x86 *c) > intel_clear_lmce(); > } > > +void mce_handle_storm(int bank, bool on) > +{ > + switch (boot_cpu_data.x86_vendor) { > + case X86_VENDOR_INTEL: > + mce_intel_handle_storm(bank, on); > + break; > + } > +} > + > static void __mcheck_cpu_init_vendor(struct cpuinfo_x86 *c) > { > switch (c->x86_vendor) { > diff --git a/arch/x86/kernel/cpu/mce/intel.c b/arch/x86/kernel/cpu/mce/intel.c > index 4106877de028..4238b73c2143 100644 > --- a/arch/x86/kernel/cpu/mce/intel.c > +++ b/arch/x86/kernel/cpu/mce/intel.c > @@ -152,6 +152,14 @@ static void cmci_set_threshold(int bank, int thresh) > raw_spin_unlock_irqrestore(&cmci_discover_lock, flags); > } > > +void mce_intel_handle_storm(int bank, bool on) > +{ > + if (on) > + cmci_set_threshold(bank, cmci_threshold[bank]); > + else > + cmci_set_threshold(bank, CMCI_STORM_THRESHOLD); I think these conditions are reversed. When storm handling is 'on' we should use CMCI_STORM_THRESHOLD, and when off use the saved bank threshold. > +} > + > static void cmci_storm_begin(int bank) > { > __set_bit(bank, this_cpu_ptr(mce_poll_banks)); > @@ -211,13 +219,13 @@ void track_cmci_storm(int bank, u64 status) > if (history & GENMASK_ULL(STORM_END_POLL_THRESHOLD - 1, 0)) > return; > pr_notice("CPU%d BANK%d CMCI storm subsided\n", smp_processor_id(), bank); > - cmci_set_threshold(bank, cmci_threshold[bank]); > + mce_handle_storm(bank, true); Should be 'false' when the storm subsides. > cmci_storm_end(bank); > } else { > if (hweight64(history) < STORM_BEGIN_THRESHOLD) > return; > pr_notice("CPU%d BANK%d CMCI storm detected\n", smp_processor_id(), bank); > - cmci_set_threshold(bank, CMCI_STORM_THRESHOLD); > + mce_handle_storm(bank, false); Should be 'true' when the storm starts. > cmci_storm_begin(bank); > } > } > -- Thanks, Yazen