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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by DM6NAM11FT108.mail.protection.outlook.com (10.13.172.95) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6298.33 via Frontend Transport; Fri, 14 Apr 2023 11:58:09 +0000 Received: from rric.localdomain (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Fri, 14 Apr 2023 06:58:06 -0500 Date: Fri, 14 Apr 2023 13:58:03 +0200 From: Robert Richter To: Jonathan Cameron CC: Bjorn Helgaas , Terry Bowman , , , , , , , , , , Oliver O'Halloran , Mahesh J Salgaonkar , , Subject: Re: [PATCH v3 6/6] PCI/AER: Unmask RCEC internal errors to enable RCH downstream port error handling Message-ID: References: <20230411180302.2678736-7-terry.bowman@amd.com> <20230412212901.GA81099@bhelgaas> <20230413180508.00003f13@Huawei.com> MIME-Version: 1.0 Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 11:58:09.9712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96925c5b-7eb7-45ba-4ff1-08db3cdf91ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5132 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13.04.23 18:05:08, Jonathan Cameron wrote: > On Thu, 13 Apr 2023 15:38:07 +0200 > Robert Richter wrote: > > > On 12.04.23 16:29:01, Bjorn Helgaas wrote: > > > On Tue, Apr 11, 2023 at 01:03:02PM -0500, Terry Bowman wrote: > > > With the exception of this function, this patch looks like all CXL > > > code that maybe could be with other CXL code. Would require making > > > pcie_walk_rcec() available outside drivers/pci, I guess. > > > > Even this is CXL code, it implements AER support and fits better here > > around AER code. Export of pcie_walk_rcec() (and others?) is not the > > main issue here. CXL drivers can come as modules and would need to > > register a hook at the aer handler. This would add even more > > complexity here. In contrast, current solution just adds two functions > > for enablement and handling which are empty stubs if code is disabled. > > > > I could move that code to aer_cxl.c similar to aer_inject.c. Since the > > CXL part is small compared to the remaining aer code I left it in > > aer.c. Also, it is guarded by #ifdef which additionally encapsulates > > it. > > > > To throw another option in there (what Bjorn suggested IIRC for the more > general case..) > > Just enable internal errors always. No need to know if they are CXL > or something else. > > There will/might be fallout and it will be fun. I left the fun part to others. :-) If some PCI root port goes crazy it tears down the whole system, would avoid that. Since internal error are implementation specific, I would only enable them once a handler exists. What's why enablement is limited to CXL RCECs only. -Robert From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.ozlabs.org (lists.ozlabs.org [112.213.38.117]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 740FCC77B72 for ; Fri, 14 Apr 2023 11:59:35 +0000 (UTC) Received: from boromir.ozlabs.org (localhost [IPv6:::1]) by lists.ozlabs.org (Postfix) with ESMTP id 4PyZkF5tFMz3fCJ for ; Fri, 14 Apr 2023 21:59:33 +1000 (AEST) Authentication-Results: lists.ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256 header.s=selector1 header.b=M7nJTo0d; dkim-atps=neutral Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=amd.com (client-ip=2a01:111:f400:7e83::626; helo=nam02-dm3-obe.outbound.protection.outlook.com; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Apr 2023 11:58:09.9712 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 96925c5b-7eb7-45ba-4ff1-08db3cdf91ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT108.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5132 X-BeenThere: linuxppc-dev@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Linux on PowerPC Developers Mail List List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alison.schofield@intel.com, dave.jiang@intel.com, Terry Bowman , vishal.l.verma@intel.com, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, linux-cxl@vger.kernel.org, Mahesh J Salgaonkar , bhelgaas@google.com, Bjorn Helgaas , linux-pci@vger.kernel.org, bwidawsk@kernel.org, Oliver O'Halloran , dan.j.williams@intel.com, ira.weiny@intel.com Errors-To: linuxppc-dev-bounces+linuxppc-dev=archiver.kernel.org@lists.ozlabs.org Sender: "Linuxppc-dev" On 13.04.23 18:05:08, Jonathan Cameron wrote: > On Thu, 13 Apr 2023 15:38:07 +0200 > Robert Richter wrote: > > > On 12.04.23 16:29:01, Bjorn Helgaas wrote: > > > On Tue, Apr 11, 2023 at 01:03:02PM -0500, Terry Bowman wrote: > > > With the exception of this function, this patch looks like all CXL > > > code that maybe could be with other CXL code. Would require making > > > pcie_walk_rcec() available outside drivers/pci, I guess. > > > > Even this is CXL code, it implements AER support and fits better here > > around AER code. Export of pcie_walk_rcec() (and others?) is not the > > main issue here. CXL drivers can come as modules and would need to > > register a hook at the aer handler. This would add even more > > complexity here. In contrast, current solution just adds two functions > > for enablement and handling which are empty stubs if code is disabled. > > > > I could move that code to aer_cxl.c similar to aer_inject.c. Since the > > CXL part is small compared to the remaining aer code I left it in > > aer.c. Also, it is guarded by #ifdef which additionally encapsulates > > it. > > > > To throw another option in there (what Bjorn suggested IIRC for the more > general case..) > > Just enable internal errors always. No need to know if they are CXL > or something else. > > There will/might be fallout and it will be fun. I left the fun part to others. :-) If some PCI root port goes crazy it tears down the whole system, would avoid that. Since internal error are implementation specific, I would only enable them once a handler exists. What's why enablement is limited to CXL RCECs only. -Robert