From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65FECC7EE29 for ; Sun, 4 Jun 2023 10:25:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230282AbjFDKZk (ORCPT ); Sun, 4 Jun 2023 06:25:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49574 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230354AbjFDKZe (ORCPT ); Sun, 4 Jun 2023 06:25:34 -0400 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A645E0 for ; Sun, 4 Jun 2023 03:25:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1685874332; x=1717410332; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; 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charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi On Sun, Jun 04, 2023 at 07:02:33AM +0300, Mika Penttilä wrote: > Hi, > > On 3.6.2023 23.07, Thomas Gleixner wrote: > > Putting CPUs into INIT is a safer place during kexec() to park CPUs. > > > > Split the INIT assert/deassert sequence out so it can be reused. > > > > Signed-off-by: Thomas Gleixner > > --- > > arch/x86/kernel/smpboot.c | 51 +++++++++++++++++++--------------------------- > > 1 file changed, 22 insertions(+), 29 deletions(-) > > > > --- a/arch/x86/kernel/smpboot.c > > +++ b/arch/x86/kernel/smpboot.c > > @@ -853,47 +853,40 @@ wakeup_secondary_cpu_via_nmi(int apicid, > > return (send_status | accept_status); > > } > > -static int > > -wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) > > +static void send_init_sequence(int phys_apicid) > > { > > - unsigned long send_status = 0, accept_status = 0; > > - int maxlvt, num_starts, j; > > - > > - maxlvt = lapic_get_maxlvt(); > > + int maxlvt = lapic_get_maxlvt(); > > - /* > > - * Be paranoid about clearing APIC errors. > > - */ > > + /* Be paranoid about clearing APIC errors. */ > > if (APIC_INTEGRATED(boot_cpu_apic_version)) { > > - if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ > > + /* Due to the Pentium erratum 3AP. */ > > + if (maxlvt > 3) > > apic_write(APIC_ESR, 0); > > apic_read(APIC_ESR); > > } > > - pr_debug("Asserting INIT\n"); > > - > > - /* > > - * Turn INIT on target chip > > - */ > > - /* > > - * Send IPI > > - */ > > - apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, > > - phys_apicid); > > - > > - pr_debug("Waiting for send to finish...\n"); > > - send_status = safe_apic_wait_icr_idle(); > > + /* Assert INIT on the target CPU */ > > + apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, phys_apicid); > > + safe_apic_wait_icr_idle(); > > udelay(init_udelay); > > - pr_debug("Deasserting INIT\n"); > > - > > - /* Target chip */ > > - /* Send IPI */ > > + /* Deassert INIT on the target CPU */ > > apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); > > + safe_apic_wait_icr_idle(); > > +} > > + > > +/* > > + * Wake up AP by INIT, INIT, STARTUP sequence. > > + */ > > +static int wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) > > +{ > > + unsigned long send_status = 0, accept_status = 0; > > + int maxlvt, num_starts, j; Also maxlvt used uninitialized. > > + > > + preempt_disable(); > > This seems like an unbalanced preempt disable.. > > > - pr_debug("Waiting for send to finish...\n"); > > - send_status = safe_apic_wait_icr_idle(); > > + send_init_sequence(phys_apicid); > > mb(); > > > > > --Mika >