From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3262A2562C for ; Mon, 19 Feb 2024 10:17:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.17 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708337855; cv=none; b=nRCD/c2J7YP+HTUUKEpYbDmwTMoYNWi/LUUSoJlJcvhbHbcjeFKf1zTw+hHFWLQE5dFKZaHT8HORDDmdFudcIje8Rohhd6XcZPv5hpNTmqV8bUJOHUo/UCp96GABQ6XWbJCv/u7baDG218LvPmNClsWmafj7zLI26mJPJ+zBSNw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1708337855; c=relaxed/simple; bh=Wo/cNfnRrJVS7u+9kX0Gzt5RyUK2/nq8mBV3ntj6ZzU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=rpuYZJ3vdki+pMtu+GSEelH2PrveiiJNG5low5Svx7Err2AqqBrNlkvTo1DXwwKyq1GH7yr9CKSRO9Yg0VpQTlANYJSuR9MhdxwRLVF1G2ZQRnb60ti0VjHaVEbPXuahzmabrDnkmAvc78t2y79jebk8H5yKt07H79B+OSpqWdI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MQBrq7jh; arc=none smtp.client-ip=198.175.65.17 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MQBrq7jh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1708337854; x=1739873854; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=Wo/cNfnRrJVS7u+9kX0Gzt5RyUK2/nq8mBV3ntj6ZzU=; b=MQBrq7jhFydFjm2Y8ZzWNlzYfu+kqzf0BcQ5bYEzRPd7jFAv8LkPfo9h g6rsAZxaDdsjnzHjaipe9V0LkmRvLhAjzY2brdEp+5A+ubBkdhByByVn4 caS8NbKI5Ro9I2ma9exufT/3Xp0iKViA0uToLMnYRliUqQ6VM5FJlSaUJ nzNCwCqeDrwunYA9LzXD1APpmrFaLGoEv7LDRRvHtx54t1ZB8nCscfTXG LJGhTgO2vyeeUF3V3FYLUkaJ+SVpa37cRiaVcoH9fNqWXbJb3w2UW+3RP Xhc1F4yUqr9yHLBuNCiEfRebvom3ImHtKZidsVhHF47LqyLIHXnaZ+UAu Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10988"; a="2533692" X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="2533692" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 02:17:33 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.06,170,1705392000"; d="scan'208";a="4609644" Received: from samathah-mobl1.ger.corp.intel.com (HELO intel.com) ([10.246.48.149]) by fmviesa008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2024 02:17:31 -0800 Date: Mon, 19 Feb 2024 11:17:28 +0100 From: Andi Shyti To: Matt Roper Cc: Andi Shyti , intel-gfx , dri-devel , Chris Wilson , Joonas Lahtinen , stable@vger.kernel.org, Andi Shyti Subject: Re: [PATCH 1/2] drm/i915/gt: Disable HW load balancing for CCS Message-ID: References: <20240215135924.51705-1-andi.shyti@linux.intel.com> <20240215135924.51705-2-andi.shyti@linux.intel.com> <20240215165541.GJ718896@mdroper-desk1.amr.corp.intel.com> Precedence: bulk X-Mailing-List: stable@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240215165541.GJ718896@mdroper-desk1.amr.corp.intel.com> Hi Matt, On Thu, Feb 15, 2024 at 08:55:41AM -0800, Matt Roper wrote: > On Thu, Feb 15, 2024 at 02:59:23PM +0100, Andi Shyti wrote: > > The hardware should not dynamically balance the load between CCS > > engines. Wa_16016805146 recommends disabling it across all > > Is this the right workaround number? When I check the database, this > workaround was rejected on both DG2-G10 and DG2-G11, and doesn't even > have an entry for DG2-G12. > > There are other workarounds that sound somewhat related to load > balancing (e.g., part 3 of Wa_14019159160), but what's asked there is > more involved than just setting one register bit and conflicts a bit > with the second patch of this series. thanks for checking it. Indeed the WA I mentioned is limited to a specific platform. This recommendation comes in different WA, e.g. this one: Wa_14019186972 (3rd point). Will start using that as a reference. Thank you. Andi > > > Matt > > > platforms. > > > > Fixes: d2eae8e98d59 ("drm/i915/dg2: Drop force_probe requirement") > > Signed-off-by: Andi Shyti > > Cc: Chris Wilson > > Cc: Joonas Lahtinen > > Cc: Matt Roper > > Cc: # v6.2+ > > --- > > drivers/gpu/drm/i915/gt/intel_gt_regs.h | 1 + > > drivers/gpu/drm/i915/gt/intel_workarounds.c | 6 ++++++ > > 2 files changed, 7 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_regs.h b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > index 50962cfd1353..cf709f6c05ae 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > +++ b/drivers/gpu/drm/i915/gt/intel_gt_regs.h > > @@ -1478,6 +1478,7 @@ > > > > #define GEN12_RCU_MODE _MMIO(0x14800) > > #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) > > +#define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) > > > > #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) > > #define CHV_FGT_DISABLE_SS0 (1 << 10) > > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > index d67d44611c28..7f42c8015f71 100644 > > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c > > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c > > @@ -2988,6 +2988,12 @@ general_render_compute_wa_init(struct intel_engine_cs *engine, struct i915_wa_li > > wa_mcr_masked_en(wal, GEN8_HALF_SLICE_CHICKEN1, > > GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); > > } > > + > > + /* > > + * Wa_16016805146: disable the CCS load balancing > > + * indiscriminately for all the platforms > > + */ > > + wa_masked_en(wal, GEN12_RCU_MODE, XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE); > > } > > > > static void > > -- > > 2.43.0 > > > > -- > Matt Roper > Graphics Software Engineer > Linux GPU Platform Enablement > Intel Corporation