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Thu, 21 Mar 2024 09:56:12 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 42L9uAWl011238 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 21 Mar 2024 09:56:10 GMT Received: from hu-varada-blr.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Thu, 21 Mar 2024 02:56:05 -0700 Date: Thu, 21 Mar 2024 15:26:01 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski CC: , , , , , , , , , , , , Subject: Re: [PATCH 2/2] clk: qcom: add IPQ9574 interconnect clocks support Message-ID: References: <20240321043149.2739204-1-quic_varada@quicinc.com> <20240321043149.2739204-3-quic_varada@quicinc.com> <4079ddcf-425d-4194-93b8-ee113864541e@linaro.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <4079ddcf-425d-4194-93b8-ee113864541e@linaro.org> X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qY1bNhBsnuPMxIGmJnK4l7gsQ10KCnqw X-Proofpoint-ORIG-GUID: qY1bNhBsnuPMxIGmJnK4l7gsQ10KCnqw X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-03-21_06,2024-03-18_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=755 clxscore=1015 suspectscore=0 mlxscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2403140001 definitions=main-2403210068 On Thu, Mar 21, 2024 at 08:25:15AM +0100, Krzysztof Kozlowski wrote: > On 21/03/2024 05:31, Varadarajan Narayanan wrote: > > Unlike MSM platforms that manage NoC related clocks and scaling > > from RPM, IPQ SoCs dont involve RPM in managing NoC related > > clocks and there is no NoC scaling. > > If these are clocks, expose them as clocks, not as interconnects. Earlier IPQ9574 PCIe patches were NAK-ed when these were exposed as clocks. Please refer to the following discussions https://lore.kernel.org/linux-arm-msm/CAA8EJpq0uawrOBHA8XHygEpGYF--HyxJWxKG44iiFdAZZz7O2w@mail.gmail.com/ https://lore.kernel.org/linux-arm-msm/CAA8EJppabK8j9T40waMv=t-1aksXfqJibWuS41GhruzLhpatrg@mail.gmail.com/ Dmitry had said I'd kindly suggest implementing the NoC attachment properly. In the end, other Qualcomm platforms use ICC drivers, so by following this pattern we will have more common code paths. Hence posted these patches to get feedback. > > However, there is a requirement to enable some NoC interface > > clocks for accessing the peripheral controllers present on > > these NoCs. > > > > Hence adding a minimalistic interconnect driver that can enable > > the relevant clocks. This is similar to msm8996-cbf's usage of > > icc-clk framework. > > > > Signed-off-by: Varadarajan Narayanan > > --- > > arch/arm64/boot/dts/qcom/ipq9574.dtsi | 2 + > > DTS is always, ALWAYS, separate. Ok. > > > drivers/clk/qcom/gcc-ipq9574.c | 75 ++++++++++++++++++++++++++- > > 2 files changed, 76 insertions(+), 1 deletion(-) > > > > diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > index 7f2e5cbf3bbb..efffbd085715 100644 > > --- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > +++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi > > @@ -11,6 +11,7 @@ > > #include > > #include > > #include > > +#include > > Keep the order, Ok. Thanks Varada