From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-177132.yeah.net (mail-177132.yeah.net [123.58.177.132]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CBD7E14294 for ; Thu, 28 Mar 2024 14:11:13 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=123.58.177.132 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711635076; cv=none; b=UiRqByaTHJNSa/ZencVGsOB17xHcP53qfx3VkCN/RLGiz+w/Tm90ViwOGSDdA2H4R6j7BplzsKB0fsxvRHfMC6jsZgi/kkC/8KkLTot4h2FRLSF+ztTkf6HlGoNtn1XN8mafl32Cqa8JMClaEEHrXRnKxyD6Lr7/PCEXL+V3jA8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1711635076; c=relaxed/simple; bh=/ST9c7ah1zJQ/+6Zv31rMPGfOa55LO5wYb9NpYAsWEw=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=oCyoJNm+1bH6UvL3ldnLMfMOg+DdtCO/KBmXRzbijc/g3Lr/idJocU+xGBD3yheq60k6xw1RJPQmM33IsAl8CsN4S6Eo/K/wXFGe2I4eN4yQztNtymz+YMNzJ8tBr7Xn/ExQwhPp4DkNODbkxFfS3bHtGHfN/6yqFhB22wG1Big= ARC-Authentication-Results:i=1; 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Thu, 28 Mar 2024 22:10:52 +0800 (CST) Date: Thu, 28 Mar 2024 22:10:51 +0800 From: Shawn Guo To: Frank Li Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , open list Subject: Re: [PATCH 1/1] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif[0,1] and sai[4,5] Message-ID: References: <20240226192130.259288-1-Frank.Li@nxp.com> Precedence: bulk X-Mailing-List: imx@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20240226192130.259288-1-Frank.Li@nxp.com> X-CM-TRANSID:C1UQrAC3HhhregVmdY9aAg--.12946S3 X-Coremail-Antispam: 1Uf129KBjvJXoW3ZrWftF4UWFykCF4xArWUArb_yoWDuryUpF 97KFW5Ga4xtF129w1YgF4kGF1kW3s8CFyj93ZxWay8CF9Fgr9rtr4xGr4kWFyYyr12vw1U XF15Xr1akwnxK3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jO8nOUUUUU= X-CM-SenderInfo: pvkd40hjxrjqh1hdxhhqhw/1tbiBQ6vZVsVCaj6-gAAsq On Mon, Feb 26, 2024 at 02:21:29PM -0500, Frank Li wrote: > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for > imx8 audio subsystem. > > Signed-off-by: Frank Li > --- > .../boot/dts/freescale/imx8-ss-audio.dtsi | 306 ++++++++++++++++++ > 1 file changed, 306 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > index 07afeb78ed564..6d78d6c0d9002 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > @@ -6,6 +6,7 @@ > > #include > #include > +#include > #include > > audio_ipg_clk: clock-audio-ipg { > @@ -481,4 +482,309 @@ acm: acm@59e00000 { > "sai3_rx_bclk", > "sai4_rx_bclk"; > }; > + > + asrc0: asrc@59000000 { We want to sort nodes in unit-address, right? > + compatible = "fsl,imx8qm-asrc"; > + reg = <0x59000000 0x10000>; > + interrupts = , > + ; > + clocks = <&asrc0_lpcg 0>, > + <&asrc0_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "ipg", "mem", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas = <&edma0 0 0 0>, > + <&edma0 1 0 0>, > + <&edma0 2 0 0>, > + <&edma0 3 0 FSL_EDMA_RX>, > + <&edma0 4 0 FSL_EDMA_RX>, > + <&edma0 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; > + fsl,asrc-rate = <8000>; One space around = > + fsl,asrc-width = <16>; > + fsl,asrc-clk-map = <0>; > + power-domains = <&pd IMX_SC_R_ASRC_0>; > + status = "disabled"; > + }; > + > + esai0: esai@59010000 { > + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; > + reg = <0x59010000 0x10000>; > + interrupts = ; > + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>; > + clock-names = "core", "extal", "fsys", "spba"; > + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_ESAI_0>; > + status = "disabled"; > + }; > + > + spdif0: spdif@59020000 { > + compatible = "fsl,imx8qm-spdif"; > + reg = <0x59020000 0x10000>; > + interrupts = , /* rx */ Ditto > + ; /* tx */ > + clocks = <&spdif0_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif0_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SPDIF_0>; > + status = "disabled"; > + }; > + > + spdif1: spdif@59030000 { > + compatible = "fsl,imx8qm-spdif"; > + reg = <0x59030000 0x10000>; > + interrupts = , /* rx */ Ditto Shawn > + ; /* tx */ > + clocks = <&spdif1_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif1_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SPDIF_1>; > + status = "disabled"; > + }; > + > + asrc1: asrc@59800000 { > + compatible = "fsl,imx8qm-asrc"; > + reg = <0x59800000 0x10000>; > + interrupts = , > + ; > + clocks = <&asrc1_lpcg 0>, > + <&asrc1_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "ipg", "mem", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas = <&edma1 0 0 0>, > + <&edma1 1 0 0>, > + <&edma1 2 0 0>, > + <&edma1 3 0 FSL_EDMA_RX>, > + <&edma1 4 0 FSL_EDMA_RX>, > + <&edma1 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names = "txa", "txb", "txc", "rxa", "rxb", "rxc"; > + fsl,asrc-rate = <8000>; > + fsl,asrc-width = <16>; > + fsl,asrc-clk-map = <1>; > + power-domains = <&pd IMX_SC_R_ASRC_1>; > + status = "disabled"; > + }; > + > + sai4: sai@59820000 { > + compatible = "fsl,imx8qm-sai"; > + reg = <0x59820000 0x10000>; > + interrupts = ; > + clocks = <&sai4_lpcg 1>, > + <&clk_dummy>, > + <&sai4_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SAI_4>; > + status = "disabled"; > + }; > + > + sai5: sai@59830000 { > + compatible = "fsl,imx8qm-sai"; > + reg = <0x59830000 0x10000>; > + interrupts = ; > + clocks = <&sai5_lpcg 1>, > + <&clk_dummy>, > + <&sai5_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 10 0 0>; > + dma-names = "tx"; > + power-domains = <&pd IMX_SC_R_SAI_5>; > + status = "disabled"; > + }; > + > + amix: amix@59840000 { > + compatible = "fsl,imx8qm-audmix"; > + reg = <0x59840000 0x10000>; > + clocks = <&amix_lpcg 0>; > + clock-names = "ipg"; > + power-domains = <&pd IMX_SC_R_AMIX>; > + dais = <&sai4>, <&sai5>; > + status = "disabled"; > + }; > + > + mqs: mqs@59850000 { > + compatible = "fsl,imx8qm-mqs"; > + reg = <0x59850000 0x10000>; > + clocks = <&mqs0_lpcg 1>, > + <&mqs0_lpcg 0>; > + clock-names = "core", "mclk"; > + power-domains = <&pd IMX_SC_R_MQS_0>; > + status = "disabled"; > + }; > + > + asrc0_lpcg: clock-controller@59400000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59400000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "asrc0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ASRC_0>; > + }; > + > + esai0_lpcg: clock-controller@59410000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59410000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "esai0_lpcg_extal_clk", > + "esai0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ESAI_0>; > + }; > + > + spdif0_lpcg: clock-controller@59420000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59420000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "spdif0_lpcg_tx_clk", > + "spdif0_lpcg_gclkw"; > + power-domains = <&pd IMX_SC_R_SPDIF_0>; > + }; > + > + spdif1_lpcg: clock-controller@59430000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59430000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "spdif1_lpcg_tx_clk", > + "spdif1_lpcg_gclkw"; > + power-domains = <&pd IMX_SC_R_SPDIF_1>; > + status = "disabled"; > + }; > + > + asrc1_lpcg: clock-controller@59c00000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c00000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "asrc1_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ASRC_1>; > + }; > + > + sai4_lpcg: clock-controller@59c20000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c20000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "sai4_lpcg_mclk", > + "sai4_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_SAI_4>; > + }; > + > + sai5_lpcg: clock-controller@59c30000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c30000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "sai5_lpcg_mclk", > + "sai5_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_SAI_5>; > + }; > + > + amix_lpcg: clock-controller@59c40000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c40000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "amix_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_AMIX>; > + }; > + > + mqs0_lpcg: clock-controller@59c50000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c50000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "mqs0_lpcg_mclk", > + "mqs0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_MQS_0>; > + }; > }; > -- > 2.34.1 > From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 587FFC54E67 for ; Thu, 28 Mar 2024 14:11:24 +0000 (UTC) DKIM-Signature: v=1; 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Thu, 28 Mar 2024 14:11:11 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yeah.net; s=s110527; h=Date:From:Subject:Message-ID:MIME-Version: Content-Type; bh=9wIZc962l46yPuHvVREzBXZG1fmGa5fztlhnsqKpiUU=; b=gQVcQj6cd0ODZmK/ARzB82ixPy+CUwbipuGuMN5nm3C9AxyFwoJWyyLjAA457V U8Eam1ZnkDMnbhQuETeCEt3vNVovl1bP29xSwVXHMd9R2nPpLM71ssgBUW+uBSbM SLbRaMquYRYWC778LkDzKVVxIi5erkXBhi3ZcunHkvfR8= Received: from dragon (unknown [183.213.196.225]) by smtp2 (Coremail) with SMTP id C1UQrAC3HhhregVmdY9aAg--.12946S3; Thu, 28 Mar 2024 22:10:52 +0800 (CST) Date: Thu, 28 Mar 2024 22:10:51 +0800 From: Shawn Guo To: Frank Li Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "open list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , open list Subject: Re: [PATCH 1/1] arm64: dts: imx8qxp: add asrc[0,1], esai0, spdif[0,1] and sai[4,5] Message-ID: References: <20240226192130.259288-1-Frank.Li@nxp.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20240226192130.259288-1-Frank.Li@nxp.com> X-CM-TRANSID: C1UQrAC3HhhregVmdY9aAg--.12946S3 X-Coremail-Antispam: 1Uf129KBjvJXoW3ZrWftF4UWFykCF4xArWUArb_yoWDuryUpF 97KFW5Ga4xtF129w1YgF4kGF1kW3s8CFyj93ZxWay8CF9Fgr9rtr4xGr4kWFyYyr12vw1U XF15Xr1akwnxK3DanT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDUYxBIdaVFxhVjvjDU0xZFpf9x07jO8nOUUUUU= X-Originating-IP: [183.213.196.225] X-CM-SenderInfo: pvkd40hjxrjqh1hdxhhqhw/1tbiBQ6vZVsVCaj6-gAAsq X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20240328_071109_986426_408C38C3 X-CRM114-Status: GOOD ( 15.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Feb 26, 2024 at 02:21:29PM -0500, Frank Li wrote: > Add asrc[0,1], esai0, spdif[0,1], sai[4,5] and related lpcg node for > imx8 audio subsystem. > > Signed-off-by: Frank Li > --- > .../boot/dts/freescale/imx8-ss-audio.dtsi | 306 ++++++++++++++++++ > 1 file changed, 306 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > index 07afeb78ed564..6d78d6c0d9002 100644 > --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi > @@ -6,6 +6,7 @@ > > #include > #include > +#include > #include > > audio_ipg_clk: clock-audio-ipg { > @@ -481,4 +482,309 @@ acm: acm@59e00000 { > "sai3_rx_bclk", > "sai4_rx_bclk"; > }; > + > + asrc0: asrc@59000000 { We want to sort nodes in unit-address, right? > + compatible = "fsl,imx8qm-asrc"; > + reg = <0x59000000 0x10000>; > + interrupts = , > + ; > + clocks = <&asrc0_lpcg 0>, > + <&asrc0_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "ipg", "mem", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas = <&edma0 0 0 0>, > + <&edma0 1 0 0>, > + <&edma0 2 0 0>, > + <&edma0 3 0 FSL_EDMA_RX>, > + <&edma0 4 0 FSL_EDMA_RX>, > + <&edma0 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; > + fsl,asrc-rate = <8000>; One space around = > + fsl,asrc-width = <16>; > + fsl,asrc-clk-map = <0>; > + power-domains = <&pd IMX_SC_R_ASRC_0>; > + status = "disabled"; > + }; > + > + esai0: esai@59010000 { > + compatible = "fsl,imx8qm-esai", "fsl,imx6ull-esai"; > + reg = <0x59010000 0x10000>; > + interrupts = ; > + clocks = <&esai0_lpcg 1>, <&esai0_lpcg 0>, <&esai0_lpcg 1>, <&clk_dummy>; > + clock-names = "core", "extal", "fsys", "spba"; > + dmas = <&edma0 6 0 FSL_EDMA_RX>, <&edma0 7 0 0>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_ESAI_0>; > + status = "disabled"; > + }; > + > + spdif0: spdif@59020000 { > + compatible = "fsl,imx8qm-spdif"; > + reg = <0x59020000 0x10000>; > + interrupts = , /* rx */ Ditto > + ; /* tx */ > + clocks = <&spdif0_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif0_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas = <&edma0 8 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 9 0 FSL_EDMA_MULTI_FIFO>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SPDIF_0>; > + status = "disabled"; > + }; > + > + spdif1: spdif@59030000 { > + compatible = "fsl,imx8qm-spdif"; > + reg = <0x59030000 0x10000>; > + interrupts = , /* rx */ Ditto Shawn > + ; /* tx */ > + clocks = <&spdif1_lpcg 1>, /* core */ > + <&clk_dummy>, /* rxtx0 */ > + <&spdif1_lpcg 0>, /* rxtx1 */ > + <&clk_dummy>, /* rxtx2 */ > + <&clk_dummy>, /* rxtx3 */ > + <&clk_dummy>, /* rxtx4 */ > + <&audio_ipg_clk>, /* rxtx5 */ > + <&clk_dummy>, /* rxtx6 */ > + <&clk_dummy>, /* rxtx7 */ > + <&clk_dummy>; /* spba */ > + clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3", "rxtx4", > + "rxtx5", "rxtx6", "rxtx7", "spba"; > + dmas = <&edma0 10 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>, > + <&edma0 11 0 FSL_EDMA_MULTI_FIFO>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SPDIF_1>; > + status = "disabled"; > + }; > + > + asrc1: asrc@59800000 { > + compatible = "fsl,imx8qm-asrc"; > + reg = <0x59800000 0x10000>; > + interrupts = , > + ; > + clocks = <&asrc1_lpcg 0>, > + <&asrc1_lpcg 0>, > + <&aud_pll_div0_lpcg 0>, > + <&aud_pll_div1_lpcg 0>, > + <&acm IMX_ADMA_ACM_AUD_CLK0_SEL>, > + <&acm IMX_ADMA_ACM_AUD_CLK1_SEL>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "ipg", "mem", > + "asrck_0", "asrck_1", "asrck_2", "asrck_3", > + "asrck_4", "asrck_5", "asrck_6", "asrck_7", > + "asrck_8", "asrck_9", "asrck_a", "asrck_b", > + "asrck_c", "asrck_d", "asrck_e", "asrck_f", > + "spba"; > + dmas = <&edma1 0 0 0>, > + <&edma1 1 0 0>, > + <&edma1 2 0 0>, > + <&edma1 3 0 FSL_EDMA_RX>, > + <&edma1 4 0 FSL_EDMA_RX>, > + <&edma1 5 0 FSL_EDMA_RX>; > + /* tx* is output channel of asrc, it is rx channel for eDMA */ > + dma-names = "txa", "txb", "txc", "rxa", "rxb", "rxc"; > + fsl,asrc-rate = <8000>; > + fsl,asrc-width = <16>; > + fsl,asrc-clk-map = <1>; > + power-domains = <&pd IMX_SC_R_ASRC_1>; > + status = "disabled"; > + }; > + > + sai4: sai@59820000 { > + compatible = "fsl,imx8qm-sai"; > + reg = <0x59820000 0x10000>; > + interrupts = ; > + clocks = <&sai4_lpcg 1>, > + <&clk_dummy>, > + <&sai4_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 8 0 FSL_EDMA_RX>, <&edma1 9 0 0>; > + dma-names = "rx", "tx"; > + power-domains = <&pd IMX_SC_R_SAI_4>; > + status = "disabled"; > + }; > + > + sai5: sai@59830000 { > + compatible = "fsl,imx8qm-sai"; > + reg = <0x59830000 0x10000>; > + interrupts = ; > + clocks = <&sai5_lpcg 1>, > + <&clk_dummy>, > + <&sai5_lpcg 0>, > + <&clk_dummy>, > + <&clk_dummy>; > + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; > + dmas = <&edma1 10 0 0>; > + dma-names = "tx"; > + power-domains = <&pd IMX_SC_R_SAI_5>; > + status = "disabled"; > + }; > + > + amix: amix@59840000 { > + compatible = "fsl,imx8qm-audmix"; > + reg = <0x59840000 0x10000>; > + clocks = <&amix_lpcg 0>; > + clock-names = "ipg"; > + power-domains = <&pd IMX_SC_R_AMIX>; > + dais = <&sai4>, <&sai5>; > + status = "disabled"; > + }; > + > + mqs: mqs@59850000 { > + compatible = "fsl,imx8qm-mqs"; > + reg = <0x59850000 0x10000>; > + clocks = <&mqs0_lpcg 1>, > + <&mqs0_lpcg 0>; > + clock-names = "core", "mclk"; > + power-domains = <&pd IMX_SC_R_MQS_0>; > + status = "disabled"; > + }; > + > + asrc0_lpcg: clock-controller@59400000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59400000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "asrc0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ASRC_0>; > + }; > + > + esai0_lpcg: clock-controller@59410000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59410000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_ESAI0_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "esai0_lpcg_extal_clk", > + "esai0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ESAI_0>; > + }; > + > + spdif0_lpcg: clock-controller@59420000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59420000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "spdif0_lpcg_tx_clk", > + "spdif0_lpcg_gclkw"; > + power-domains = <&pd IMX_SC_R_SPDIF_0>; > + }; > + > + spdif1_lpcg: clock-controller@59430000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59430000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "spdif1_lpcg_tx_clk", > + "spdif1_lpcg_gclkw"; > + power-domains = <&pd IMX_SC_R_SPDIF_1>; > + status = "disabled"; > + }; > + > + asrc1_lpcg: clock-controller@59c00000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c00000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "asrc1_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_ASRC_1>; > + }; > + > + sai4_lpcg: clock-controller@59c20000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c20000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SAI4_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "sai4_lpcg_mclk", > + "sai4_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_SAI_4>; > + }; > + > + sai5_lpcg: clock-controller@59c30000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c30000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_SAI5_MCLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "sai5_lpcg_mclk", > + "sai5_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_SAI_5>; > + }; > + > + amix_lpcg: clock-controller@59c40000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c40000 0x10000>; > + #clock-cells = <1>; > + clocks = <&audio_ipg_clk>; > + clock-indices = ; > + clock-output-names = "amix_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_AMIX>; > + }; > + > + mqs0_lpcg: clock-controller@59c50000 { > + compatible = "fsl,imx8qxp-lpcg"; > + reg = <0x59c50000 0x10000>; > + #clock-cells = <1>; > + clocks = <&acm IMX_ADMA_ACM_MQS_TX_CLK_SEL>, > + <&audio_ipg_clk>; > + clock-indices = , ; > + clock-output-names = "mqs0_lpcg_mclk", > + "mqs0_lpcg_ipg_clk"; > + power-domains = <&pd IMX_SC_R_MQS_0>; > + }; > }; > -- > 2.34.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel