From: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
To: Palmer Dabbelt <palmer@sifive.com>
Cc: sagark@eecs.berkeley.edu, richard.henderson@linaro.org,
qemu-devel@nongnu.org, peer.adelt@hni.uni-paderborn.de,
Alistair Francis <Alistair.Francis@wdc.com>,
Michael Clark <mjc@sifive.com>
Subject: Re: [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree
Date: Fri, 26 Oct 2018 12:53:11 +0200 [thread overview]
Message-ID: <a0916ce9-da94-7a38-52d6-61be33e3c67d@mail.uni-paderborn.de> (raw)
In-Reply-To: <mhng-a68ddfc1-c1f3-4c28-97a5-bf5dfc9db931@palmer-si-x1c4>
On 10/25/18 12:21 AM, Palmer Dabbelt wrote:
> On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
> kbastian@mail.uni-paderborn.de wrote:
>> Hi,
>>
>> this patchset converts the RISC-V decoder to decodetree in three
>> major steps:
>>
>> 1) Convert 32-bit instructions to decodetree [Patch 1-14]:
>> Many of the gen_* functions are called by the decode functions
>> for 16-bit
>> and 32-bit functions. If we move translation code from the gen_*
>> functions to the generated trans_* functions of decode-tree, we
>> get a lot of
>> duplication. Therefore, we mostly generate calls to the old gen_*
>> function
>> which are properly replaced after step 2).
>>
>> Each of the trans_ functions are grouped into files corresponding
>> to their
>> ISA extension, e.g. addi which is in RV32I is translated in the file
>> 'trans_rvi.inc.c'.
>>
>> 2) Convert 16-bit instructions to decodetree [Patch 15-17]:
>> All 16 bit instructions have a direct mapping to a 32 bit
>> instruction. Thus,
>> we convert the arguments in the 16 bit trans_ function to the
>> arguments of
>> the corresponding 32 bit instruction and call the 32 bit trans_
>> function.
>>
>> 3) Remove old manual decoding in gen_* function [Patch 17-28]:
>> this move all manual translation code into the trans_*
>> instructions of
>> decode tree, such that we can remove the old decode_* functions.
>>
>> the full tree can be found here:
>> https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
>
> Thanks!
>
> I dropped this on top of master and it appears I'm getting a bunch of
> oops when trying to boot Linux. They're fairly far into the boot
> process and may be a mistake on my end, I was just wondering if you'd
> booted Linux?
Are there non fatal oops in booting Linux? I only checked whether I
could get a terminal on Fedora Linux.
Cheers,
Bastian
next prev parent reply other threads:[~2018-10-26 10:53 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-20 7:14 [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 01/29] target/riscv: Move CPURISCVState pointer to DisasContext Bastian Koppelmann
2018-10-25 16:38 ` Palmer Dabbelt
2018-10-25 16:54 ` Peter Maydell
2018-10-25 17:05 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 02/29] targer/riscv: Activate decodetree and implemnt LUI & AUIPC Bastian Koppelmann
2018-10-20 19:32 ` Richard Henderson
2018-10-25 16:58 ` Palmer Dabbelt
2018-10-26 10:49 ` Bastian Koppelmann
2018-10-26 13:58 ` Richard Henderson
2018-10-26 14:53 ` Bastian Koppelmann
2018-10-26 15:42 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 03/29] target/riscv: Convert RVXI branch insns to decodetree Bastian Koppelmann
2018-10-20 19:34 ` Richard Henderson
2018-10-25 20:24 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 04/29] target/riscv: Convert RVXI load/store " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 05/29] target/riscv: Convert RVXI arithmetic " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 06/29] target/riscv: Convert RVXI fence " Bastian Koppelmann
2018-10-21 14:05 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 07/29] target/riscv: Convert RVXI csr " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 08/29] target/riscv: Convert RVXM " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 09/29] target/riscv: Convert RV32A " Bastian Koppelmann
2018-10-23 8:19 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 10/29] target/riscv: Convert RV64A " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 11/29] target/riscv: Convert RV32F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 12/29] target/riscv: Convert RV64F " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 13/29] target/riscv: Convert RV32D " Bastian Koppelmann
2018-10-23 8:21 ` Richard Henderson
2018-10-31 10:44 ` Bastian Koppelmann
2018-10-31 10:47 ` Bastian Koppelmann
2018-10-31 17:21 ` Palmer Dabbelt
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 14/29] target/riscv: Convert RV64D " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 15/29] target/riscv: Convert RV priv " Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 16/29] target/riscv: Convert quadrant 0 of RVXC " Bastian Koppelmann
2018-10-23 8:31 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 17/29] target/riscv: Convert quadrant 1 " Bastian Koppelmann
2018-10-23 8:35 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 18/29] target/riscv: Convert quadrant 2 " Bastian Koppelmann
2018-10-23 8:39 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 19/29] target/riscv: Remove gen_jalr() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 20/29] target/riscv: Remove manual decoding from gen_branch() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 21/29] target/riscv: Remove manual decoding from gen_load() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 22/29] target/riscv: Remove manual decoding from gen_store() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 23/29] target/riscv: Move gen_arith_imm() decoding into trans_* functions Bastian Koppelmann
2018-10-23 8:46 ` Richard Henderson
2018-10-24 9:07 ` Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 24/29] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists Bastian Koppelmann
2018-10-23 8:53 ` Richard Henderson
2018-10-23 8:55 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 25/29] target/riscv: Remove shift and slt insn manual decoding Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 26/29] target/riscv: Remove manual decoding of RV32/64M insn Bastian Koppelmann
2018-10-23 9:02 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 27/29] target/riscv: Remove gen_system() Bastian Koppelmann
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 28/29] target/riscv: Remove decode_RV32_64G() Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-20 7:14 ` [Qemu-devel] [PATCH v2 29/29] target/riscv: Rename trans_arith to gen_arith Bastian Koppelmann
2018-10-23 9:04 ` Richard Henderson
2018-10-24 22:21 ` [Qemu-devel] [PATCH v2 00/29] target/riscv: Convert to decodetree Palmer Dabbelt
2018-10-26 10:53 ` Bastian Koppelmann [this message]
2018-10-27 6:20 ` Palmer Dabbelt
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