From: Tom Lendacky <thomas.lendacky@amd.com> To: Joerg Roedel <joro@8bytes.org>, x86@kernel.org Cc: Joerg Roedel <jroedel@suse.de>, Brijesh Singh <brijesh.singh@amd.com>, hpa@zytor.com, Andy Lutomirski <luto@kernel.org>, Dave Hansen <dave.hansen@linux.intel.com>, Peter Zijlstra <peterz@infradead.org>, Jiri Slaby <jslaby@suse.cz>, Dan Williams <dan.j.williams@intel.com>, Juergen Gross <jgross@suse.com>, Kees Cook <keescook@chromium.org>, David Rientjes <rientjes@google.com>, Cfir Cohen <cfir@google.com>, Erdem Aktas <erdemaktas@google.com>, Masami Hiramatsu <mhiramat@kernel.org>, Mike Stunes <mstunes@vmware.com>, Sean Christopherson <seanjc@google.com>, Martin Radev <martin.b.radev@gmail.com>, Arvind Sankar <nivedita@alum.mit.edu>, linux-coco@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, virtualization@lists.linux-foundation.org Subject: Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Date: Tue, 22 Jun 2021 11:19:27 -0500 [thread overview] Message-ID: <a0d38ffa-e5dc-7e50-fc18-fc10ff19309f@amd.com> (raw) In-Reply-To: <20210622144825.27588-3-joro@8bytes.org> On 6/22/21 9:48 AM, Joerg Roedel wrote: > From: Brijesh Singh <brijesh.singh@amd.com> > > Add the necessary defines for supporting the GHCB version 2 protocol. > This includes defines for: > > - MSR-based AP hlt request/response > - Hypervisor Feature request/response > > This is the bare minimum of requests that need to be supported by a GHCB > version 2 implementation. There are more requests in the specification, > but those depend on Secure Nested Paging support being available. > > These defines are shared between SEV host and guest support, so they are > submitted as an individual patch without users yet to avoid merge > conflicts in the future. > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> > Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 1cc9e7dd8107..4e6c4c7cb294 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -47,6 +47,21 @@ > (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ > (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) > > +/* AP Reset Hold */ > +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 > +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) > + > +/* GHCB Hypervisor Feature Request/Response */ > +#define GHCB_MSR_HV_FT_REQ 0x080 > +#define GHCB_MSR_HV_FT_RESP 0x081 > +#define GHCB_MSR_HV_FT_POS 12 > +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) > + > +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ > + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) This should shift down first and then mask or else the mask should be from 12 to 63. Thanks, Tom > + > #define GHCB_MSR_TERM_REQ 0x100 > #define GHCB_MSR_TERM_REASON_SET_POS 12 > #define GHCB_MSR_TERM_REASON_SET_MASK 0xf >
WARNING: multiple messages have this Message-ID (diff)
From: Tom Lendacky via Virtualization <virtualization@lists.linux-foundation.org> To: Joerg Roedel <joro@8bytes.org>, x86@kernel.org Cc: Brijesh Singh <brijesh.singh@amd.com>, kvm@vger.kernel.org, Peter Zijlstra <peterz@infradead.org>, Dave Hansen <dave.hansen@linux.intel.com>, virtualization@lists.linux-foundation.org, Arvind Sankar <nivedita@alum.mit.edu>, hpa@zytor.com, Jiri Slaby <jslaby@suse.cz>, David Rientjes <rientjes@google.com>, Martin Radev <martin.b.radev@gmail.com>, Joerg Roedel <jroedel@suse.de>, Kees Cook <keescook@chromium.org>, Cfir Cohen <cfir@google.com>, linux-coco@lists.linux.dev, Andy Lutomirski <luto@kernel.org>, Dan Williams <dan.j.williams@intel.com>, Juergen Gross <jgross@suse.com>, Mike Stunes <mstunes@vmware.com>, Sean Christopherson <seanjc@google.com>, linux-kernel@vger.kernel.org, Masami Hiramatsu <mhiramat@kernel.org>, Erdem Aktas <erdemaktas@google.com> Subject: Re: [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Date: Tue, 22 Jun 2021 11:19:27 -0500 [thread overview] Message-ID: <a0d38ffa-e5dc-7e50-fc18-fc10ff19309f@amd.com> (raw) In-Reply-To: <20210622144825.27588-3-joro@8bytes.org> On 6/22/21 9:48 AM, Joerg Roedel wrote: > From: Brijesh Singh <brijesh.singh@amd.com> > > Add the necessary defines for supporting the GHCB version 2 protocol. > This includes defines for: > > - MSR-based AP hlt request/response > - Hypervisor Feature request/response > > This is the bare minimum of requests that need to be supported by a GHCB > version 2 implementation. There are more requests in the specification, > but those depend on Secure Nested Paging support being available. > > These defines are shared between SEV host and guest support, so they are > submitted as an individual patch without users yet to avoid merge > conflicts in the future. > > Signed-off-by: Brijesh Singh <brijesh.singh@amd.com> > Co-developed-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Tom Lendacky <thomas.lendacky@amd.com> > Signed-off-by: Joerg Roedel <jroedel@suse.de> > --- > arch/x86/include/asm/sev-common.h | 15 +++++++++++++++ > 1 file changed, 15 insertions(+) > > diff --git a/arch/x86/include/asm/sev-common.h b/arch/x86/include/asm/sev-common.h > index 1cc9e7dd8107..4e6c4c7cb294 100644 > --- a/arch/x86/include/asm/sev-common.h > +++ b/arch/x86/include/asm/sev-common.h > @@ -47,6 +47,21 @@ > (((unsigned long)reg & GHCB_MSR_CPUID_REG_MASK) << GHCB_MSR_CPUID_REG_POS) | \ > (((unsigned long)fn) << GHCB_MSR_CPUID_FUNC_POS)) > > +/* AP Reset Hold */ > +#define GHCB_MSR_AP_RESET_HOLD_REQ 0x006 > +#define GHCB_MSR_AP_RESET_HOLD_RESP 0x007 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_POS 12 > +#define GHCB_MSR_AP_RESET_HOLD_RESULT_MASK GENMASK_ULL(51, 0) > + > +/* GHCB Hypervisor Feature Request/Response */ > +#define GHCB_MSR_HV_FT_REQ 0x080 > +#define GHCB_MSR_HV_FT_RESP 0x081 > +#define GHCB_MSR_HV_FT_POS 12 > +#define GHCB_MSR_HV_FT_MASK GENMASK_ULL(51, 0) > + > +#define GHCB_MSR_HV_FT_RESP_VAL(v) \ > + (((unsigned long)((v) & GHCB_MSR_HV_FT_MASK) >> GHCB_MSR_HV_FT_POS)) This should shift down first and then mask or else the mask should be from 12 to 63. Thanks, Tom > + > #define GHCB_MSR_TERM_REQ 0x100 > #define GHCB_MSR_TERM_REASON_SET_POS 12 > #define GHCB_MSR_TERM_REASON_SET_MASK 0xf > _______________________________________________ Virtualization mailing list Virtualization@lists.linux-foundation.org https://lists.linuxfoundation.org/mailman/listinfo/virtualization
next prev parent reply other threads:[~2021-06-22 16:19 UTC|newest] Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-06-22 14:48 [PATCH 0/3] x86/sev: Minor updates for SEV guest support Joerg Roedel 2021-06-22 14:48 ` Joerg Roedel 2021-06-22 14:48 ` [PATCH 1/3] x86/sev: Add Comments to existing GHCB MSR protocol defines Joerg Roedel 2021-06-22 14:48 ` Joerg Roedel 2021-06-22 14:48 ` [PATCH 2/3] x86/sev: Add defines for GHCB version 2 MSR protocol requests Joerg Roedel 2021-06-22 14:48 ` Joerg Roedel 2021-06-22 16:19 ` Tom Lendacky [this message] 2021-06-22 16:19 ` Tom Lendacky via Virtualization 2021-06-22 16:34 ` Brijesh Singh 2021-06-22 16:34 ` Brijesh Singh via Virtualization 2021-06-23 6:40 ` Joerg Roedel 2021-06-23 6:40 ` Joerg Roedel 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:32 ` Borislav Petkov 2021-06-23 9:49 ` Joerg Roedel 2021-06-23 9:49 ` Joerg Roedel 2021-06-23 12:33 ` Brijesh Singh 2021-06-23 12:33 ` Brijesh Singh via Virtualization 2021-06-23 13:12 ` Tom Lendacky 2021-06-23 13:12 ` Tom Lendacky via Virtualization 2021-06-23 13:32 ` [tip: x86/sev] " tip-bot2 for Brijesh Singh 2021-06-22 14:48 ` [PATCH 3/3] x86/sev: Use "SEV: " prefix for messages from sev.c Joerg Roedel 2021-06-22 14:48 ` Joerg Roedel 2021-06-23 13:32 ` [tip: x86/sev] " tip-bot2 for Joerg Roedel
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