From mboxrd@z Thu Jan 1 00:00:00 1970 From: Paolo Bonzini Subject: Re: [PATCH v5 2/4] i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg Date: Wed, 22 Jun 2016 19:08:36 +0200 Message-ID: References: <20160622065624.25291-1-haozhong.zhang@intel.com> <20160622065624.25291-3-haozhong.zhang@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Cc: Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj To: Haozhong Zhang , qemu-devel@nongnu.org Return-path: Received: from mail-wm0-f68.google.com ([74.125.82.68]:36752 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751549AbcFVRIk (ORCPT ); Wed, 22 Jun 2016 13:08:40 -0400 Received: by mail-wm0-f68.google.com with SMTP id c82so3165605wme.3 for ; Wed, 22 Jun 2016 10:08:39 -0700 (PDT) In-Reply-To: <20160622065624.25291-3-haozhong.zhang@intel.com> Sender: kvm-owner@vger.kernel.org List-ID: On 22/06/2016 08:56, Haozhong Zhang wrote: > + > + val = g_malloc(sizeof(*val)); > + *val = feature_control_bits | FEATURE_CONTROL_LOCKED; As noticed by Laszlo, you need to use cpu_to_le64 here. The maintainer can fix it, I think. Paolo > + fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); > +} From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40049) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFldr-000781-Tl for qemu-devel@nongnu.org; Wed, 22 Jun 2016 13:08:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bFldn-0004Rj-N1 for qemu-devel@nongnu.org; Wed, 22 Jun 2016 13:08:42 -0400 Received: from mail-wm0-x242.google.com ([2a00:1450:400c:c09::242]:35171) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bFldn-0004Rd-Fr for qemu-devel@nongnu.org; Wed, 22 Jun 2016 13:08:39 -0400 Received: by mail-wm0-x242.google.com with SMTP id a66so3169336wme.2 for ; Wed, 22 Jun 2016 10:08:39 -0700 (PDT) Sender: Paolo Bonzini References: <20160622065624.25291-1-haozhong.zhang@intel.com> <20160622065624.25291-3-haozhong.zhang@intel.com> From: Paolo Bonzini Message-ID: Date: Wed, 22 Jun 2016 19:08:36 +0200 MIME-Version: 1.0 In-Reply-To: <20160622065624.25291-3-haozhong.zhang@intel.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v5 2/4] i386: publish advised value of MSR_IA32_FEATURE_CONTROL via fw_cfg List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Haozhong Zhang , qemu-devel@nongnu.org Cc: Richard Henderson , Eduardo Habkost , "Michael S . Tsirkin" , Marcelo Tosatti , kvm@vger.kernel.org, Boris Petkov , Tony Luck , Andi Kleen , rkrcmar@redhat.com, Ashok Raj On 22/06/2016 08:56, Haozhong Zhang wrote: > + > + val = g_malloc(sizeof(*val)); > + *val = feature_control_bits | FEATURE_CONTROL_LOCKED; As noticed by Laszlo, you need to use cpu_to_le64 here. The maintainer can fix it, I think. Paolo > + fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); > +}