All of lore.kernel.org
 help / color / mirror / Atom feed
From: Marc Zyngier <maz@kernel.org>
To: Mark Rutland <mark.rutland@arm.com>, Brad Larson <brad@pensando.io>
Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
	linus.walleij@linaro.org, bgolaszewski@baylibre.com,
	broonie@kernel.org, fancer.lancer@gmail.com,
	adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net,
	linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support
Date: Mon, 25 Oct 2021 12:15:04 +0100	[thread overview]
Message-ID: <a20805de16e1196c2ed46dd949473c9a@kernel.org> (raw)
In-Reply-To: <20211025091731.GA2001@C02TD0UTHF1T.local>

On 2021-10-25 10:17, Mark Rutland wrote:
> Hi,
> 
> On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote:
>> Add Pensando common and Elba SoC specific device nodes
>> 
>> Signed-off-by: Brad Larson <brad@pensando.io>
> 
> [...]
> 
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>;
>> +	};
> 
> The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you
> have GICv3, where this is not valid, so this should go.
> 
> Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which
> doesn't mak sense for the 16 CPUs you have.
> 
>> +		gic: interrupt-controller@800000 {
>> +			compatible = "arm,gic-v3";
>> +			#interrupt-cells = <3>;
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +			interrupt-controller;
>> +			reg = <0x0 0x800000 0x0 0x200000>,	/* GICD */
>> +			      <0x0 0xa00000 0x0 0x200000>;	/* GICR */

This is missing the GICv2 compat regions that the CPUs implement.

>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			gic_its: msi-controller@820000 {
>> +				compatible = "arm,gic-v3-its";
>> +				msi-controller;
>> +				#msi-cells = <1>;
>> +				reg = <0x0 0x820000 0x0 0x10000>;
>> +				socionext,synquacer-pre-its =
>> +							<0xc00000 0x1000000>;
>> +			};
>> +		};
> 
> Is there any shared lineage with Synquacer? The commit message didn't
> describe this quirk.

Funny, it looks like there is a sudden outburst of stupid copy/paste
among HW designers. TI did the exact same thing recently.

This totally negates all the advantages of having an ITS and makes
sure that you have all the overhead. Facepalm...

         M.
-- 
Jazz is not dead. It just smells funny...

WARNING: multiple messages have this Message-ID (diff)
From: Marc Zyngier <maz@kernel.org>
To: Mark Rutland <mark.rutland@arm.com>, Brad Larson <brad@pensando.io>
Cc: linux-arm-kernel@lists.infradead.org, arnd@arndb.de,
	linus.walleij@linaro.org, bgolaszewski@baylibre.com,
	broonie@kernel.org, fancer.lancer@gmail.com,
	adrian.hunter@intel.com, ulf.hansson@linaro.org, olof@lixom.net,
	linux-gpio@vger.kernel.org, linux-spi@vger.kernel.org,
	linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support
Date: Mon, 25 Oct 2021 12:15:04 +0100	[thread overview]
Message-ID: <a20805de16e1196c2ed46dd949473c9a@kernel.org> (raw)
In-Reply-To: <20211025091731.GA2001@C02TD0UTHF1T.local>

On 2021-10-25 10:17, Mark Rutland wrote:
> Hi,
> 
> On Sun, Oct 24, 2021 at 06:51:56PM -0700, Brad Larson wrote:
>> Add Pensando common and Elba SoC specific device nodes
>> 
>> Signed-off-by: Brad Larson <brad@pensando.io>
> 
> [...]
> 
>> +	timer {
>> +		compatible = "arm,armv8-timer";
>> +		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>,
>> +			     <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) |
>> +					IRQ_TYPE_LEVEL_LOW)>;
>> +	};
> 
> The GIC_CPU_MASK_SIMPLE() stuff is meant for GICv2, but as below you
> have GICv3, where this is not valid, so this should go.
> 
> Also, beware that GIC_CPU_MASK_SIMPLE(1) means a single CPU, which
> doesn't mak sense for the 16 CPUs you have.
> 
>> +		gic: interrupt-controller@800000 {
>> +			compatible = "arm,gic-v3";
>> +			#interrupt-cells = <3>;
>> +			#address-cells = <2>;
>> +			#size-cells = <2>;
>> +			ranges;
>> +			interrupt-controller;
>> +			reg = <0x0 0x800000 0x0 0x200000>,	/* GICD */
>> +			      <0x0 0xa00000 0x0 0x200000>;	/* GICR */

This is missing the GICv2 compat regions that the CPUs implement.

>> +			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
>> +
>> +			gic_its: msi-controller@820000 {
>> +				compatible = "arm,gic-v3-its";
>> +				msi-controller;
>> +				#msi-cells = <1>;
>> +				reg = <0x0 0x820000 0x0 0x10000>;
>> +				socionext,synquacer-pre-its =
>> +							<0xc00000 0x1000000>;
>> +			};
>> +		};
> 
> Is there any shared lineage with Synquacer? The commit message didn't
> describe this quirk.

Funny, it looks like there is a sudden outburst of stupid copy/paste
among HW designers. TI did the exact same thing recently.

This totally negates all the advantages of having an ITS and makes
sure that you have all the overhead. Facepalm...

         M.
-- 
Jazz is not dead. It just smells funny...

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2021-10-25 11:15 UTC|newest]

Thread overview: 90+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-10-25  1:51 [PATCH v3 00/11] Support Pensando Elba SoC Brad Larson
2021-10-25  1:51 ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 01/11] dt-bindings: arm: pensando: add Pensando boards Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-27 21:37   ` Rob Herring
2021-10-27 21:37     ` Rob Herring
2021-10-25  1:51 ` [PATCH v3 02/11] dt-bindings: Add vendor prefix for Pensando Systems Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-27 21:38   ` Rob Herring
2021-10-27 21:38     ` Rob Herring
2021-11-05  0:16     ` Brad Larson
2021-11-05  0:16       ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 03/11] dt-bindings: mmc: Add Pensando Elba SoC binding Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25 12:54   ` Rob Herring
2021-10-25 12:54     ` Rob Herring
2021-11-05  0:13     ` Brad Larson
2021-11-05  0:13       ` Brad Larson
2021-10-26 18:10   ` Rob Herring
2021-10-26 18:10     ` Rob Herring
2021-11-17  1:21     ` Brad Larson
2021-11-17  1:21       ` Brad Larson
2021-11-17  1:27       ` Brad Larson
2021-11-17  1:27         ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 04/11] dt-bindings: spi: Add compatible for Pensando Elba SoC Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-27 21:38   ` Rob Herring
2021-10-27 21:38     ` Rob Herring
2021-10-28  7:26   ` Serge Semin
2021-10-28  7:26     ` Serge Semin
2021-11-15 22:05     ` Brad Larson
2021-11-15 22:05       ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 05/11] spi: dw: Add Pensando Elba SoC SPI Controller bindings Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-27 21:42   ` Rob Herring
2021-10-27 21:42     ` Rob Herring
2021-10-28  7:49   ` Serge Semin
2021-10-28  7:49     ` Serge Semin
2021-10-28  7:52     ` Serge Semin
2021-10-28  7:52       ` Serge Semin
2021-11-15 22:24     ` Brad Larson
2021-11-15 22:24       ` Brad Larson
2021-11-16 11:29       ` Serge Semin
2021-11-16 11:29         ` Serge Semin
2021-11-16 23:11         ` Brad Larson
2021-11-16 23:11           ` Brad Larson
2021-11-17  8:19           ` Serge Semin
2021-11-17  8:19             ` Serge Semin
2021-11-17 21:35             ` Brad Larson
2021-11-17 21:35               ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 06/11] MAINTAINERS: Add entry for PENSANDO Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 07/11] arm64: Add config for Pensando SoC platforms Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 08/11] spi: cadence-quadspi: Add compatible for Pensando Elba SoC Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 09/11] mmc: sdhci-cadence: Add Pensando Elba SoC support Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25  1:51 ` [PATCH v3 10/11] spi: dw: Add support for Pensando Elba SoC Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-28  9:11   ` Serge Semin
2021-10-28  9:11     ` Serge Semin
2021-10-31 13:19   ` Andy Shevchenko
2021-10-31 13:19     ` Andy Shevchenko
2021-10-25  1:51 ` [PATCH v3 11/11] arm64: dts: Add Pensando Elba SoC support Brad Larson
2021-10-25  1:51   ` Brad Larson
2021-10-25  9:17   ` Mark Rutland
2021-10-25  9:17     ` Mark Rutland
2021-10-25 11:15     ` Marc Zyngier [this message]
2021-10-25 11:15       ` Marc Zyngier
2021-11-05  0:02       ` Brad Larson
2021-11-05  0:02         ` Brad Larson
2021-11-05 11:35         ` Marc Zyngier
2021-11-05 11:35           ` Marc Zyngier
2021-11-08 19:35           ` Brad Larson
2021-11-08 19:35             ` Brad Larson
2021-11-08 19:53             ` Marc Zyngier
2021-11-08 19:53               ` Marc Zyngier
2021-11-08 20:01               ` Brad Larson
2021-11-08 20:01                 ` Brad Larson
2021-11-04 22:53     ` Brad Larson
2021-11-04 22:53       ` Brad Larson
2021-11-08 10:25       ` Mark Rutland
2021-11-08 10:25         ` Mark Rutland
2021-11-08 19:02         ` Brad Larson
2021-11-08 19:02           ` Brad Larson
2021-10-27 21:37   ` Rob Herring
2021-10-27 21:37     ` Rob Herring
2021-11-11  2:08     ` Brad Larson
2021-11-11  2:08       ` Brad Larson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=a20805de16e1196c2ed46dd949473c9a@kernel.org \
    --to=maz@kernel.org \
    --cc=adrian.hunter@intel.com \
    --cc=arnd@arndb.de \
    --cc=bgolaszewski@baylibre.com \
    --cc=brad@pensando.io \
    --cc=broonie@kernel.org \
    --cc=devicetree@vger.kernel.org \
    --cc=fancer.lancer@gmail.com \
    --cc=linus.walleij@linaro.org \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-gpio@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mmc@vger.kernel.org \
    --cc=linux-spi@vger.kernel.org \
    --cc=mark.rutland@arm.com \
    --cc=olof@lixom.net \
    --cc=ulf.hansson@linaro.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.