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([2001:b07:6468:f312:a0f7:472a:1e7:7ef]) by smtp.gmail.com with ESMTPSA id j63sm22213815wmj.46.2019.11.11.07.02.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 11 Nov 2019 07:02:54 -0800 (PST) Subject: Re: [PATCH 2/2] KVM: nVMX: Update vmcs01 TPR_THRESHOLD if L2 changed L1 TPR To: Liran Alon , rkrcmar@redhat.com, kvm@vger.kernel.org Cc: sean.j.christopherson@intel.com, jmattson@google.com, vkuznets@redhat.com, Joao Martins References: <20191111123055.93270-1-liran.alon@oracle.com> <20191111123055.93270-3-liran.alon@oracle.com> From: Paolo Bonzini Openpgp: preference=signencrypt Message-ID: Date: Mon, 11 Nov 2019 16:02:56 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20191111123055.93270-3-liran.alon@oracle.com> Content-Language: en-US X-MC-Unique: RUdJfHKmPsmcJ92zzEoT6A-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Sender: kvm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 11/11/19 13:30, Liran Alon wrote: > When L1 don't use TPR-Shadow to run L2, L0 configures vmcs02 without > TPR-Shadow and install intercepts on CR8 access (load and store). >=20 > If L1 do not intercept L2 CR8 access, L0 intercepts on those accesses > will emulate load/store on L1's LAPIC TPR. If in this case L2 lowers > TPR such that there is now an injectable interrupt to L1, > apic_update_ppr() will request a KVM_REQ_EVENT which will trigger a call > to update_cr8_intercept() to update TPR-Threshold to highest pending IRR > priority. >=20 > However, this update to TPR-Threshold is done while active vmcs is > vmcs02 instead of vmcs01. Thus, when later at some point L0 will > emulate an exit from L2 to L1, L1 will still run with high > TPR-Threshold. This will result in every VMEntry to L1 to immediately > exit on TPR_BELOW_THRESHOLD and continue to do so infinitely until > some condition will cause KVM_REQ_EVENT to be set. > (Note that TPR_BELOW_THRESHOLD exit handler do not set KVM_REQ_EVENT > until apic_update_ppr() will notice a new injectable interrupt for PPR) >=20 > To fix this issue, change update_cr8_intercept() such that if L2 lowers > L1's TPR in a way that requires to lower L1's TPR-Threshold, save update > to TPR-Threshold and apply it to vmcs01 when L0 emulates an exit from > L2 to L1. Can you explain why the write shouldn't be done to vmcs02 as well? Paolo > -=09vmcs_write32(TPR_THRESHOLD, tpr_threshold); > + > +=09if (is_guest_mode(vcpu)) > +=09=09to_vmx(vcpu)->nested.l1_tpr_threshold =3D tpr_threshold; > +=09else > +=09=09vmcs_write32(TPR_THRESHOLD, tpr_threshold); > } > =20 > void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu) > diff --git a/arch/x86/kvm/vmx/vmx.h b/arch/x86/kvm/vmx/vmx.h > index bee16687dc0b..43331dfafffe 100644 > --- a/arch/x86/kvm/vmx/vmx.h > +++ b/arch/x86/kvm/vmx/vmx.h > @@ -167,6 +167,9 @@ struct nested_vmx { > =09u64 vmcs01_debugctl; > =09u64 vmcs01_guest_bndcfgs; > =20 > +=09/* to migrate it to L1 if L2 writes to L1's CR8 directly */ > +=09int l1_tpr_threshold; > + > =09u16 vpid02; > =09u16 last_vpid; > =20 >=20