From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C139C433ED for ; Wed, 5 May 2021 18:06:51 +0000 (UTC) Received: from lists.xenproject.org (lists.xenproject.org [192.237.175.120]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5C968610A6 for ; Wed, 5 May 2021 18:06:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 5C968610A6 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=xen.org Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from list by lists.xenproject.org with outflank-mailman.123265.232508 (Exim 4.92) (envelope-from ) id 1leLv1-0004fi-VO; Wed, 05 May 2021 18:06:43 +0000 X-Outflank-Mailman: Message body and most headers restored to incoming version Received: by outflank-mailman (output) from mailman id 123265.232508; Wed, 05 May 2021 18:06:43 +0000 Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leLv1-0004fb-S6; Wed, 05 May 2021 18:06:43 +0000 Received: by outflank-mailman (input) for mailman id 123265; Wed, 05 May 2021 18:06:43 +0000 Received: from mail.xenproject.org ([104.130.215.37]) by lists.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leLv1-0004fV-1C for xen-devel@lists.xenproject.org; Wed, 05 May 2021 18:06:43 +0000 Received: from xenbits.xenproject.org ([104.239.192.120]) by mail.xenproject.org with esmtp (Exim 4.92) (envelope-from ) id 1leLuz-0007Wa-Tp; Wed, 05 May 2021 18:06:41 +0000 Received: from [54.239.6.185] (helo=a483e7b01a66.ant.amazon.com) by xenbits.xenproject.org with esmtpsa (TLS1.3:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.92) (envelope-from ) id 1leLuz-0004WL-Nz; Wed, 05 May 2021 18:06:41 +0000 X-BeenThere: xen-devel@lists.xenproject.org List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xenproject.org Precedence: list Sender: "Xen-devel" DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=xen.org; s=20200302mail; h=Content-Transfer-Encoding:Content-Type:In-Reply-To: MIME-Version:Date:Message-ID:From:References:Cc:To:Subject; bh=tNAWVrdaQhtGTqwXr1cIycPbH/1Akop+EME/lo8dk5o=; b=cykerznRqq0MqqVIYAFbrxFvyG pxr/+UwH7GnSQ/LLPrqB+wkogXLoRcyEuqEPCX0CIVqtJChU4nANiAjN43ahmmNCk5W7qiFcH8DLm 2rQSFw+Bg6VRi4MrJrLlgOcovUSyFWT5zt89wXy0LKL+q/n48NiQDhygo0IYxG9uHihY=; Subject: Re: [PATCH v3 05/10] arm/gic: Get rid of READ/WRITE_SYSREG32 To: Michal Orzel , xen-devel@lists.xenproject.org Cc: Stefano Stabellini , Volodymyr Babchuk , bertrand.marquis@arm.com, wei.chen@arm.com References: <20210505074308.11016-1-michal.orzel@arm.com> <20210505074308.11016-6-michal.orzel@arm.com> From: Julien Grall Message-ID: Date: Wed, 5 May 2021 19:06:39 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.10.0 MIME-Version: 1.0 In-Reply-To: <20210505074308.11016-6-michal.orzel@arm.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Hi Michal, On 05/05/2021 08:43, Michal Orzel wrote: > AArch64 registers are 64bit whereas AArch32 registers > are 32bit or 64bit. MSR/MRS are expecting 64bit values thus > we should get rid of helpers READ/WRITE_SYSREG32 > in favour of using READ/WRITE_SYSREG. > We should also use register_t type when reading sysregs > which can correspond to uint64_t or uint32_t. > Even though many AArch64 registers have upper 32bit reserved > it does not mean that they can't be widen in the future. > > Modify types of following members of struct gic_v3 to register_t: > -vmcr > -sre_el1 > -apr0 > -apr1 > > Add new macro GICC_IAR_INTID_MASK containing the mask > for INTID field of ICC_IAR0/1_EL1 register as only the first 23-bits > of IAR contains the interrupt number. The rest are RES0. > Therefore, take the opportunity to mask the bits [23:31] as > they should be used for an IRQ number (we don't know how the top bits > will be used). > > Signed-off-by: Michal Orzel Acked-by: Julien Grall Cheers, -- Julien Grall