From: Alexandru Stefan ISAILA <aisaila@bitdefender.com>
To: Jan Beulich <JBeulich@suse.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
Tamas K Lengyel <tamas@tklengyel.com>,
Wei Liu <wei.liu2@citrix.com>,
Razvan Cojocaru <rcojocaru@bitdefender.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v3] arch/x86: Add registers to vm_event
Date: Thu, 25 Oct 2018 13:10:18 +0000 [thread overview]
Message-ID: <a2d6bd10-ca33-ad1c-2988-b85853e9a613@bitdefender.com> (raw)
In-Reply-To: <5BD1AF2B02000078001F49F2@prv1-mh.provo.novell.com>
On 25.10.2018 14:55, Jan Beulich wrote:
>>>> On 18.10.18 at 11:02, <aisaila@bitdefender.com> wrote:
>> --- a/xen/arch/x86/vm_event.c
>> +++ b/xen/arch/x86/vm_event.c
>> @@ -122,11 +122,60 @@ void vm_event_monitor_next_interrupt(struct vcpu *v)
>> v->arch.monitor.next_interrupt_enabled = true;
>> }
>>
>> +static void vm_event_pack_segment_register(enum x86_segment segment,
>> + struct vm_event_regs_x86 *reg)
>> +{
>> + struct segment_register seg;
>> +
>> + hvm_get_segment_register(current, segment, &seg);
>> +
>> + switch ( segment )
>> + {
>> + case x86_seg_ss:
>> + reg->ss.fields.base = seg.base;
>> + reg->ss.fields.limit = seg.g ? seg.limit >> 12 : seg.limit;
>> + reg->ss.fields.ar = seg.attr;
>> + reg->ss_sel = seg.sel;
>> + break;
>> + case x86_seg_fs:
>
> Blank lines between individual case blocks please.
Will add
(...)
>
> Either add ASSERT_UNREACHABLE() or drop the default case.
I will drop it in the next version.
>
>> @@ -157,6 +157,19 @@
>> #define VM_EVENT_X86_CR4 2
>> #define VM_EVENT_X86_XCR0 3
>>
>> +struct x86_selector_reg {
>> + union
>> + {
>> + uint64_t bytes;
>> + struct
>> + {
>> + uint32_t base;
>> + uint32_t limit : 20;
>> + uint32_t ar : 12;
>> + } fields;
>> + };
>> +};
>
> I don't understand why sel was moved out. Are you tight on
> space here, such that you can't tolerate the padding bytes?
It was dropped on Andrew's suggestion. We are ok with it in the
structure so if is ok by you I can add it back.
>
> I also question the need for a union here. You don't use
> .bytes anywhere afaics.
Right now there is no use for the .bytes field and it was put for
further usage. I can drop this in the next version.
>
> Finally - what meaning to the low (or high) 4 bits of "ar"
> carry?
If I correctly understand the question, we use ar bits to determine the
running mode of the guest.
>
>> @@ -193,7 +206,19 @@ struct vm_event_regs_x86 {
>> uint64_t msr_lstar;
>> uint64_t fs_base;
>> uint64_t gs_base;
>
> You previously removed them, and I think that was correct.
> The field in the union should be uint64_t. Right now you leave
> fs.base and gs.base uninitialized.
>
We want the structure to be tight so that is why .base is uint32. If we
move the fs/gs base in the new structure and make base to be uint64 then
there are some useless bits there.
The question is if we can leave the code like this and init de remaining
fields? From what I am seeing the fs/gs base should remain uint64.
Alex
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next prev parent reply other threads:[~2018-10-25 13:10 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-10-18 9:02 [PATCH v3] arch/x86: Add registers to vm_event Alexandru Stefan ISAILA
2018-10-18 19:56 ` Tamas K Lengyel
2018-10-23 8:36 ` PING: " Alexandru Stefan ISAILA
2018-10-24 16:48 ` Tamas K Lengyel
2018-10-25 7:16 ` Alexandru Stefan ISAILA
2018-10-25 11:55 ` Jan Beulich
2018-10-25 13:10 ` Alexandru Stefan ISAILA [this message]
2018-10-25 13:33 ` Razvan Cojocaru
2018-10-25 14:04 ` Jan Beulich
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