From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-pf0-f193.google.com ([209.85.192.193]:34302 "EHLO mail-pf0-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752932AbdGHRDG (ORCPT ); Sat, 8 Jul 2017 13:03:06 -0400 To: iommu@lists.linux-foundation.org, kvm@vger.kernel.org, linux-pci@vger.kernel.org From: valmiki Cc: jean-Philippe Brucker , tianyu.lan@intel.com, kevin.tian@intel.com, Alex Williamson , jacob.jun.pan@intel.com Subject: Support SVM without PASID Message-ID: Date: Sat, 8 Jul 2017 22:33:01 +0530 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Sender: linux-pci-owner@vger.kernel.org List-ID: Hi, In SMMUv3 architecture document i see "PASIDs are optional, configurable, and of a size determined by the minimum of the endpoint". So if PASID's are optional and not supported by PCIe end point, how SVM can be achieved ? How will the translation for a particular process virtual address is obtained ? Regards, Valmiki From mboxrd@z Thu Jan 1 00:00:00 1970 From: valmiki Subject: Support SVM without PASID Date: Sat, 8 Jul 2017 22:33:01 +0530 Message-ID: Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii"; Format="flowed" Content-Transfer-Encoding: 7bit Cc: tianyu.lan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, kevin.tian-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org, jacob.jun.pan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org To: iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, kvm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org Return-path: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org List-Id: kvm.vger.kernel.org Hi, In SMMUv3 architecture document i see "PASIDs are optional, configurable, and of a size determined by the minimum of the endpoint". So if PASID's are optional and not supported by PCIe end point, how SVM can be achieved ? How will the translation for a particular process virtual address is obtained ? Regards, Valmiki