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Tue, 06 Sep 2022 06:28:33 -0700 (PDT) Received: from [192.168.255.10] ([103.7.29.32]) by smtp.gmail.com with ESMTPSA id b14-20020a1709027e0e00b0017542c2ddabsm9793289plm.288.2022.09.06.06.28.31 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 06 Sep 2022 06:28:33 -0700 (PDT) Message-ID: Date: Tue, 6 Sep 2022 21:28:25 +0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:91.0) Gecko/20100101 Thunderbird/91.13.0 Subject: Re: [kvm-unit-tests PATCH v3 10/13] x86/pmu: Update testcases to cover Intel Arch PMU Version 1 Content-Language: en-US To: Sandipan Das Cc: kvm@vger.kernel.org, Sean Christopherson , Paolo Bonzini References: <20220819110939.78013-1-likexu@tencent.com> <20220819110939.78013-11-likexu@tencent.com> <895a4eab-5c1c-add1-35b7-8178b927fefd@amd.com> From: Like Xu In-Reply-To: <895a4eab-5c1c-add1-35b7-8178b927fefd@amd.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: kvm@vger.kernel.org On 6/9/2022 3:15 pm, Sandipan Das wrote: > Hi Like, > > On 8/19/2022 4:39 PM, Like Xu wrote: >> From: Like Xu >> >> For most unit tests, the basic framework and use cases which test >> any PMU counter do not require any changes, except for two things: >> >> - No access to registers introduced only in PMU version 2 and above; >> - Expanded tolerance for testing counter overflows >> due to the loss of uniform control of the gloabl_ctrl register >> >> Adding some pmu_version() return value checks can seamlessly support >> Intel Arch PMU Version 1, while opening the door for AMD PMUs tests. >> >> Signed-off-by: Like Xu >> --- >> x86/pmu.c | 64 +++++++++++++++++++++++++++++++++++++------------------ >> 1 file changed, 43 insertions(+), 21 deletions(-) >> >> diff --git a/x86/pmu.c b/x86/pmu.c >> index 25fafbe..826472c 100644 >> --- a/x86/pmu.c >> +++ b/x86/pmu.c >> [...] >> @@ -520,10 +544,13 @@ static void check_emulated_instr(void) >> "instruction count"); >> report(brnch_cnt.count - brnch_start >= EXPECTED_BRNCH, >> "branch count"); >> - // Additionally check that those counters overflowed properly. >> - status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); >> - report(status & 1, "instruction counter overflow"); >> - report(status & 2, "branch counter overflow"); >> + >> + if (pmu_version() > 1) { >> + // Additionally check that those counters overflowed properly. >> + status = rdmsr(MSR_CORE_PERF_GLOBAL_STATUS); >> + report(status & 1, "instruction counter overflow"); >> + report(status & 2, "branch counter overflow"); >> + } >> > > This should use status bit 1 for instructions and bit 0 for branches. Yes, this misleading statement stems from 20cf914 ("x86/pmu: Test PMU virtualization on emulated instructions") I will fix it as part of this patch set. Thanks. > >> report_prefix_pop(); >> } >> [...] > > - Sandipan