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[88.152.144.157]) by smtp.gmail.com with ESMTPSA id z6sm9603894wmp.1.2021.11.05.07.12.16 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 05 Nov 2021 07:12:17 -0700 (PDT) Message-ID: Date: Fri, 5 Nov 2021 15:12:16 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH 2/4] sunxi: gpio: Add per-bank drive and pull setters Content-Language: en-US To: Samuel Holland Cc: Andy Shevchenko , Icenowy Zheng , Jaehoon Chung , Jernej Skrabec , Peng Fan , Simon Glass , u-boot@lists.denx.de, Andre Przywara , Jagan Teki References: <20211021045258.30757-1-samuel@sholland.org> <20211021045258.30757-3-samuel@sholland.org> From: Heinrich Schuchardt In-Reply-To: <20211021045258.30757-3-samuel@sholland.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 10/21/21 06:52, Samuel Holland wrote: > The GPIO and pinctrl drivers need these setters for pin configuration. > Since they are DM drivers, they should not be using hardcoded base > addresses. Factor out variants of the setter functions which take a > pointer to the GPIO bank's MMIO registers. > > Signed-off-by: Samuel Holland > --- > > arch/arm/include/asm/arch-sunxi/gpio.h | 2 ++ > arch/arm/mach-sunxi/pinmux.c | 20 ++++++++++++++++---- > 2 files changed, 18 insertions(+), 4 deletions(-) > > diff --git a/arch/arm/include/asm/arch-sunxi/gpio.h b/arch/arm/include/asm/arch-sunxi/gpio.h > index 2b72b2263b..106605adf5 100644 > --- a/arch/arm/include/asm/arch-sunxi/gpio.h > +++ b/arch/arm/include/asm/arch-sunxi/gpio.h > @@ -227,7 +227,9 @@ void sunxi_gpio_set_cfgpin(u32 pin, u32 val); > int sunxi_gpio_get_cfgbank(struct sunxi_gpio *pio, int bank_offset); > int sunxi_gpio_get_cfgpin(u32 pin); > void sunxi_gpio_set_drv(u32 pin, u32 val); Please, add Sphinx style documentation for the new functions, preferably in the header file. Cf. https://www.kernel.org/doc/html/latest/doc-guide/kernel-doc.html#function-documentation > +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val); > void sunxi_gpio_set_pull(u32 pin, u32 val); > +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val); > int sunxi_name_to_gpio(const char *name); > > #if !defined CONFIG_SPL_BUILD && defined CONFIG_AXP_GPIO > diff --git a/arch/arm/mach-sunxi/pinmux.c b/arch/arm/mach-sunxi/pinmux.c > index cf9d9daf7c..b2093b623a 100644 > --- a/arch/arm/mach-sunxi/pinmux.c > +++ b/arch/arm/mach-sunxi/pinmux.c > @@ -48,19 +48,31 @@ int sunxi_gpio_get_cfgpin(u32 pin) > void sunxi_gpio_set_drv(u32 pin, u32 val) > { > u32 bank = GPIO_BANK(pin); > - u32 index = GPIO_DRV_INDEX(pin); > - u32 offset = GPIO_DRV_OFFSET(pin); > struct sunxi_gpio *pio = BANK_TO_GPIO(bank); > > + sunxi_gpio_set_drv_bank(pio, pin, val); > +} > + > +void sunxi_gpio_set_drv_bank(struct sunxi_gpio *pio, u32 bank_offset, u32 val) > +{ > + u32 index = GPIO_DRV_INDEX(bank_offset); > + u32 offset = GPIO_DRV_OFFSET(bank_offset); > + > clrsetbits_le32(&pio->drv[0] + index, 0x3 << offset, val << offset); > } > > void sunxi_gpio_set_pull(u32 pin, u32 val) > { > u32 bank = GPIO_BANK(pin); > - u32 index = GPIO_PULL_INDEX(pin); > - u32 offset = GPIO_PULL_OFFSET(pin); > struct sunxi_gpio *pio = BANK_TO_GPIO(bank); > > + sunxi_gpio_set_pull_bank(pio, pin, val); > +} > + > +void sunxi_gpio_set_pull_bank(struct sunxi_gpio *pio, int bank_offset, u32 val) > +{ > + u32 index = GPIO_PULL_INDEX(bank_offset); > + u32 offset = GPIO_PULL_OFFSET(bank_offset); > + > clrsetbits_le32(&pio->pull[0] + index, 0x3 << offset, val << offset); Please, simplify this: %s/&pio->pull[0] + index/&pio->pull[index]/ Otherwise the change looks correct to me. Best regards Heinrich > } >