From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:38781) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1byvWd-0004NC-Ok for qemu-devel@nongnu.org; Tue, 25 Oct 2016 02:47:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1byvWZ-0000ZP-Lt for qemu-devel@nongnu.org; Tue, 25 Oct 2016 02:47:55 -0400 Received: from mail-pf0-x241.google.com ([2607:f8b0:400e:c00::241]:33678) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1byvWZ-0000Z5-Du for qemu-devel@nongnu.org; Tue, 25 Oct 2016 02:47:51 -0400 Received: by mail-pf0-x241.google.com with SMTP id i85so18696465pfa.0 for ; Mon, 24 Oct 2016 23:47:51 -0700 (PDT) References: <1477285201-10244-1-git-send-email-david@gibson.dropbear.id.au> <1477285201-10244-8-git-send-email-david@gibson.dropbear.id.au> From: Alexey Kardashevskiy Message-ID: Date: Tue, 25 Oct 2016 17:47:43 +1100 MIME-Version: 1.0 In-Reply-To: <1477285201-10244-8-git-send-email-david@gibson.dropbear.id.au> Content-Type: text/plain; charset=koi8-r Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCHv5 07/12] libqos: Implement mmio accessors in terms of mem{read, write} List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: David Gibson , pbonzini@redhat.com, qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, lvivier@redhat.com, agraf@suse.de, stefanha@redhat.com, mst@redhat.com, mdroth@linux.vnet.ibm.com, groug@kaod.org, thuth@redhat.com On 24/10/16 15:59, David Gibson wrote: > In the libqos PCI code we now have accessors both for registers (byte > significance preserving) and for streaming data (byte address order > preserving). These exist in both the interface for qtest drivers and in > the machine specific backends. > > However, the register-style accessors aren't actually necessary in the > backend. They can be implemented in terms of the byte address order > preserving accessors by the libqos wrappers. This works because PCI is > always little endian. > > This does assume that the back end byte address order preserving accessors > will perform the equivalent of a single bus transaction for short lengths. > This is the case, and in fact they currently end up using the same > cpu_physical_memory_rw() implementation within the qtest accelerator. > > Signed-off-by: David Gibson > Reviewed-by: Laurent Vivier > Reviewed-by: Greg Kurz > --- > tests/libqos/pci-pc.c | 38 -------------------------------------- > tests/libqos/pci-spapr.c | 44 -------------------------------------------- > tests/libqos/pci.c | 20 ++++++++++++++------ > tests/libqos/pci.h | 8 -------- > 4 files changed, 14 insertions(+), 96 deletions(-) > [...] > diff --git a/tests/libqos/pci.h b/tests/libqos/pci.h > index 2b08362..ce6ed08 100644 > --- a/tests/libqos/pci.h > +++ b/tests/libqos/pci.h > @@ -27,18 +27,10 @@ struct QPCIBus { > uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr); > uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr); > > - uint8_t (*mmio_readb)(QPCIBus *bus, uint32_t addr); > - uint16_t (*mmio_readw)(QPCIBus *bus, uint32_t addr); > - uint32_t (*mmio_readl)(QPCIBus *bus, uint32_t addr); > - > void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value); > void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value); > void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value); > > - void (*mmio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value); > - void (*mmio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value); > - void (*mmio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value); > - > void (*memread)(QPCIBus *bus, uint32_t addr, void *buf, size_t len); > void (*memwrite)(QPCIBus *bus, uint32_t addr, const void *buf, size_t len); > > You added them in "libqos: Handle PCI IO de-multiplexing in common code" (few patched before) and removing them now - if you moved this patch earlier, it would reduce the series, or what do I miss? -- Alexey