From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.1 required=3.0 tests=DKIM_INVALID,DKIM_SIGNED, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 856A8C43603 for ; Tue, 17 Dec 2019 23:25:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 52B5121582 for ; Tue, 17 Dec 2019 23:25:34 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=fail reason="key not found in DNS" (0-bit key) header.d=mg.codeaurora.org header.i=@mg.codeaurora.org header.b="pEKyMxys" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726496AbfLQXZd (ORCPT ); Tue, 17 Dec 2019 18:25:33 -0500 Received: from mail26.static.mailgun.info ([104.130.122.26]:55832 "EHLO mail26.static.mailgun.info" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726072AbfLQXZc (ORCPT ); Tue, 17 Dec 2019 18:25:32 -0500 DKIM-Signature: a=rsa-sha256; v=1; c=relaxed/relaxed; d=mg.codeaurora.org; q=dns/txt; s=smtp; t=1576625132; h=Content-Transfer-Encoding: Content-Type: In-Reply-To: MIME-Version: Date: Message-ID: From: References: Cc: To: Subject: Sender; bh=YJEwly1+ltZDuvrkRrwDOT3yLn4EXIUPFyMApEtgGuc=; b=pEKyMxysmfBKyQC9dZAmvgCV3lBjsLFBWUUl5hADHxfcsLWvPsT7hbGbpPR0ZE0svKnyMwCa ZKod/Kol6gplkYZ0XeW+SQcvGU8220RnPqCJvehC6T6LRd4tz8E73bdtH7wSrb/HR1+Sj6am VaLLEB0kbVKb305dgl1OjgFADr8= X-Mailgun-Sending-Ip: 104.130.122.26 X-Mailgun-Sid: WyI0MWYwYSIsICJsaW51eC1rZXJuZWxAdmdlci5rZXJuZWwub3JnIiwgImJlOWU0YSJd Received: from smtp.codeaurora.org (ec2-35-166-182-171.us-west-2.compute.amazonaws.com [35.166.182.171]) by mxa.mailgun.org with ESMTP id 5df963eb.7fefd4384a08-smtp-out-n02; Tue, 17 Dec 2019 23:25:31 -0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1001) id A9800C447A3; Tue, 17 Dec 2019 23:25:29 +0000 (UTC) Received: from [10.46.161.159] (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: asutoshd) by smtp.codeaurora.org (Postfix) with ESMTPSA id 480D5C433CB; Tue, 17 Dec 2019 23:25:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 480D5C433CB Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=asutoshd@codeaurora.org Subject: Re: [PATCH v1 2/2] scsi: ufs: disable interrupt during clock-gating To: Stanley Chu , linux-scsi@vger.kernel.org, martin.petersen@oracle.com, avri.altman@wdc.com, alim.akhtar@samsung.com, pedrom.sousa@synopsys.com, jejb@linux.ibm.com, matthias.bgg@gmail.com Cc: linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, beanhuo@micron.com, kuohong.wang@mediatek.com, peter.wang@mediatek.com, chun-hung.wu@mediatek.com, andy.teng@mediatek.com References: <1575721321-8071-1-git-send-email-stanley.chu@mediatek.com> <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> From: "Asutosh Das (asd)" Message-ID: Date: Tue, 17 Dec 2019 15:25:27 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 12/7/2019 4:22 AM, Stanley Chu wrote: > Similar to suspend, ufshcd interrupt can be disabled since > there won't be any host controller transaction expected till > clocks ungated. > > Signed-off-by: Stanley Chu > --- > drivers/scsi/ufs/ufshcd.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c > index f80bd4e811cb..5de105e82c32 100644 > --- a/drivers/scsi/ufs/ufshcd.c > +++ b/drivers/scsi/ufs/ufshcd.c > @@ -1490,6 +1490,8 @@ static void ufshcd_ungate_work(struct work_struct *work) > spin_unlock_irqrestore(hba->host->host_lock, flags); > ufshcd_setup_clocks(hba, true); > > + ufshcd_enable_irq(hba); > + > /* Exit from hibern8 */ > if (ufshcd_can_hibern8_during_gating(hba)) { > /* Prevent gating in this path */ > @@ -1636,6 +1638,8 @@ static void ufshcd_gate_work(struct work_struct *work) > ufshcd_set_link_hibern8(hba); > } > > + ufshcd_disable_irq(hba); > + > if (!ufshcd_is_link_active(hba)) > ufshcd_setup_clocks(hba, false); > else > Hi, Does this save significant power? I see that gate/ungate of clocks happen far too frequently than suspend/resume. Have you considered how much latency this would add to the gating/ungating path? -asd -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3AC44C43603 for ; Tue, 17 Dec 2019 23:25:45 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0835121582 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=asutoshd@codeaurora.org Subject: Re: [PATCH v1 2/2] scsi: ufs: disable interrupt during clock-gating To: Stanley Chu , linux-scsi@vger.kernel.org, martin.petersen@oracle.com, avri.altman@wdc.com, alim.akhtar@samsung.com, pedrom.sousa@synopsys.com, jejb@linux.ibm.com, matthias.bgg@gmail.com References: <1575721321-8071-1-git-send-email-stanley.chu@mediatek.com> <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> From: "Asutosh Das (asd)" Message-ID: Date: Tue, 17 Dec 2019 15:25:27 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191217_152535_354229_A49F7675 X-CRM114-Status: GOOD ( 18.54 ) X-BeenThere: linux-mediatek@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andy.teng@mediatek.com, chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, peter.wang@mediatek.com, linux-arm-kernel@lists.infradead.org, beanhuo@micron.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "Linux-mediatek" Errors-To: linux-mediatek-bounces+linux-mediatek=archiver.kernel.org@lists.infradead.org On 12/7/2019 4:22 AM, Stanley Chu wrote: > Similar to suspend, ufshcd interrupt can be disabled since > there won't be any host controller transaction expected till > clocks ungated. > > Signed-off-by: Stanley Chu > --- > drivers/scsi/ufs/ufshcd.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c > index f80bd4e811cb..5de105e82c32 100644 > --- a/drivers/scsi/ufs/ufshcd.c > +++ b/drivers/scsi/ufs/ufshcd.c > @@ -1490,6 +1490,8 @@ static void ufshcd_ungate_work(struct work_struct *work) > spin_unlock_irqrestore(hba->host->host_lock, flags); > ufshcd_setup_clocks(hba, true); > > + ufshcd_enable_irq(hba); > + > /* Exit from hibern8 */ > if (ufshcd_can_hibern8_during_gating(hba)) { > /* Prevent gating in this path */ > @@ -1636,6 +1638,8 @@ static void ufshcd_gate_work(struct work_struct *work) > ufshcd_set_link_hibern8(hba); > } > > + ufshcd_disable_irq(hba); > + > if (!ufshcd_is_link_active(hba)) > ufshcd_setup_clocks(hba, false); > else > Hi, Does this save significant power? I see that gate/ungate of clocks happen far too frequently than suspend/resume. Have you considered how much latency this would add to the gating/ungating path? -asd -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project _______________________________________________ Linux-mediatek mailing list Linux-mediatek@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-mediatek From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5014AC2D0BF for ; Tue, 17 Dec 2019 23:25:51 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2515F21582 for ; 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dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: aws-us-west-2-caf-mail-1.web.codeaurora.org; spf=none smtp.mailfrom=asutoshd@codeaurora.org Subject: Re: [PATCH v1 2/2] scsi: ufs: disable interrupt during clock-gating To: Stanley Chu , linux-scsi@vger.kernel.org, martin.petersen@oracle.com, avri.altman@wdc.com, alim.akhtar@samsung.com, pedrom.sousa@synopsys.com, jejb@linux.ibm.com, matthias.bgg@gmail.com References: <1575721321-8071-1-git-send-email-stanley.chu@mediatek.com> <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> From: "Asutosh Das (asd)" Message-ID: Date: Tue, 17 Dec 2019 15:25:27 -0800 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:60.0) Gecko/20100101 Thunderbird/60.9.1 MIME-Version: 1.0 In-Reply-To: <1575721321-8071-3-git-send-email-stanley.chu@mediatek.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20191217_152535_333852_507C7B48 X-CRM114-Status: GOOD ( 19.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andy.teng@mediatek.com, chun-hung.wu@mediatek.com, kuohong.wang@mediatek.com, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, peter.wang@mediatek.com, linux-arm-kernel@lists.infradead.org, beanhuo@micron.com Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/7/2019 4:22 AM, Stanley Chu wrote: > Similar to suspend, ufshcd interrupt can be disabled since > there won't be any host controller transaction expected till > clocks ungated. > > Signed-off-by: Stanley Chu > --- > drivers/scsi/ufs/ufshcd.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/scsi/ufs/ufshcd.c b/drivers/scsi/ufs/ufshcd.c > index f80bd4e811cb..5de105e82c32 100644 > --- a/drivers/scsi/ufs/ufshcd.c > +++ b/drivers/scsi/ufs/ufshcd.c > @@ -1490,6 +1490,8 @@ static void ufshcd_ungate_work(struct work_struct *work) > spin_unlock_irqrestore(hba->host->host_lock, flags); > ufshcd_setup_clocks(hba, true); > > + ufshcd_enable_irq(hba); > + > /* Exit from hibern8 */ > if (ufshcd_can_hibern8_during_gating(hba)) { > /* Prevent gating in this path */ > @@ -1636,6 +1638,8 @@ static void ufshcd_gate_work(struct work_struct *work) > ufshcd_set_link_hibern8(hba); > } > > + ufshcd_disable_irq(hba); > + > if (!ufshcd_is_link_active(hba)) > ufshcd_setup_clocks(hba, false); > else > Hi, Does this save significant power? I see that gate/ungate of clocks happen far too frequently than suspend/resume. Have you considered how much latency this would add to the gating/ungating path? -asd -- The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, Linux Foundation Collaborative Project _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel