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[174.21.143.238]) by smtp.gmail.com with ESMTPSA id s23sm20102195pfs.157.2020.06.25.20.52.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 25 Jun 2020 20:52:15 -0700 (PDT) Subject: Re: [PATCH v3 4/8] target/ppc: add vmulld instruction To: Lijun Pan References: <20200625170018.64265-1-ljp@linux.ibm.com> <20200625170018.64265-5-ljp@linux.ibm.com> From: Richard Henderson Message-ID: Date: Thu, 25 Jun 2020 20:52:13 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.8.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::1042; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1042.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Laurent Vivier , Lijun Pan , qemu-devel@nongnu.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 6/25/20 2:13 PM, Lijun Pan wrote: >>>     case INDEX_op_mul_vec: >>> -        tcg_debug_assert(vece == MO_32 && have_isa_2_07); >>> -        insn = VMULUWM; >>> +        tcg_debug_assert((vece == MO_32 && have_isa_2_07) || >>> +                         (vece == MO_64 && have_isa_3_10)); >>> +        insn = mul_op[vece]; >> >> I think it would be ok to just index mul_op here, since the real isa check is >> to be done elsewhere. > > Just keep "insn = mul_op[vece];" > and remove"        tcg_debug_assert((vece == MO_32 && have_isa_2_07) || >                          (vece == MO_64 && have_isa_3_10));“? Yes. > @@ -3016,6 +3016,8 @@int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, > unsigned vece) >              return -1; >          case MO_32: >              return have_isa_2_07 ? 1 : -1; > +        case MO_64: > +            return have_isa_3_10 ? 1 : -1; >          } Actually, just "return have_isa_3_10". Returning 1 means that the opcode is supported directly. Returning -1 means that the opcode can be expanded by tcg_expand_vec_op. Returning 0 means that the tcg backend does not support the opcode at all. > something like below? > @@ -3712,6 +3712,11 @@static void tcg_target_init(TCGContext *s) >          have_isa = tcg_isa_3_00; >      } >  #endif > +#ifdef PPC_FEATURE2_ARCH_3_10 > +    if (hwcap2 & PPC_FEATURE2_ARCH_3_10) { > +        have_isa = tcg_isa_3_10; > +    } > +#endif Certainly this. > @@ -554,6 +554,7 @@typedef struct { >  #define PPC_FEATURE2_HTM_NOSC           0x01000000 >  #define PPC_FEATURE2_ARCH_3_00          0x00800000 >  #define PPC_FEATURE2_HAS_IEEE128        0x00400000 > +#define PPC_FEATURE2_ARCH_3_10          0x00200000 Of this I'm not sure. I didn't even realize these defines were here in include/elf.h. For other tcg backends we get the defines from . If we do want to update include/elf.h, it should be a separate patch. CC'ing Laurent for this. r~