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	for speck@linutronix.de; Tue, 01 May 2018 01:12:19 +0200
Subject: [MODERATED] Re: [patch V8 05/15] SSB 5
References: <20180430150423.180110059@linutronix.de>
 <20180430151232.202750431@linutronix.de>
 <aec37500-2266-41d1-696b-97d383acf432@linux.intel.com>
From: Tim Chen <tim.c.chen@linux.intel.com>
Message-ID: <a3b5fbfe-ffa9-0feb-d9d6-55ef3d48d8f2@linux.intel.com>
Date: Mon, 30 Apr 2018 16:12:15 -0700
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On 04/30/2018 01:57 PM, speck for Tim Chen wrote:
>=20
> The HW folks just gave me a few more CPUs not
> susceptible to SSB.
>=20
> Thanks.
>=20
> Tim
>=20
> diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.=
c
> index c3b53bc..9a205aa4 100644
> --- a/arch/x86/kernel/cpu/common.c
> +++ b/arch/x86/kernel/cpu/common.c
> @@ -930,6 +930,9 @@ static const __initconst struct x86_cpu_id cpu_no_s=
pec_store_bypass[] =3D {
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CLOVERVIEW },
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_CEDARVIEW },
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_SILVERMONT1 },
> +       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_SILVERMONT2 },
> +       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_YONAH },

Sorry, fix typo

+       { X86_VENDOR_INTEL,     6, INTEL_FAM6_CORE_YONAH },

> +       { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_MERRIFIELD },
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_ATOM_AIRMONT },
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_XEON_PHI_KNL },
>         { X86_VENDOR_INTEL,     6, INTEL_FAM6_XEON_PHI_KNM },
>=20


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