Re: [PATCH 2/3] drm/i915/ehl: Remove unsupported cd clocks

From: "Souza, Jose" <jose.souza@intel.com>
To: "ville.syrjala@linux.intel.com" <ville.syrjala@linux.intel.com>
Cc: "intel-gfx@lists.freedesktop.org" <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH 2/3] drm/i915/ehl: Remove unsupported cd clocks
Date: Thu, 20 Jun 2019 00:37:44 +0000	[thread overview]
Message-ID: <a3fb1a9c2095fc9b97f7fc046fcc0686e452551e.camel@intel.com> (raw)
In-Reply-To: <20190619114055.GV5942@intel.com>

On Wed, 2019-06-19 at 14:40 +0300, Ville Syrjälä wrote:
> On Tue, Jun 18, 2019 at 03:50:34PM -0700, José Roberto de Souza
> wrote:
> > EHL do not support 648 and 652.8 MHz.
> 
> You should modify the max_cdclk() function instead. I think that
> along
> should be sufficient.

Okay and it makes the patch smaller, thanks

> 
> > BSpec: 20598
> > Cc: Clint Taylor <Clinton.A.Taylor@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_cdclk.c | 17 +++++++++++++----
> >  1 file changed, 13 insertions(+), 4 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > index d560e25d3fb5..26c17ecf2083 100644
> > --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> > +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> > @@ -1754,7 +1754,8 @@ static void cnl_sanitize_cdclk(struct
> > drm_i915_private *dev_priv)
> >  	dev_priv->cdclk.hw.vco = -1;
> >  }
> >  
> > -static int icl_calc_cdclk(int min_cdclk, unsigned int ref)
> > +static int icl_calc_cdclk(struct drm_i915_private *dev_priv, int
> > min_cdclk,
> > +			  unsigned int ref)
> >  {
> >  	const int ranges_24[] = { 180000, 192000, 312000, 552000,
> > 648000 };
> >  	const int ranges_19_38[] = { 172800, 192000, 307200, 556800,
> > 652800 };
> > @@ -1776,6 +1777,12 @@ static int icl_calc_cdclk(int min_cdclk,
> > unsigned int ref)
> >  		break;
> >  	}
> >  
> > +	/*
> > +	 * EHL do not support 648 and 652.8 MHz, so just decrement the
> > len
> > +	 */
> > +	if (IS_ELKHARTLAKE(dev_priv))
> > +		len--;
> > +
> >  	for (i = 0; i < len; i++) {
> >  		if (min_cdclk <= ranges[i])
> >  			return ranges[i];
> > @@ -1954,7 +1961,8 @@ static void icl_init_cdclk(struct
> > drm_i915_private *dev_priv)
> >  	DRM_DEBUG_KMS("Sanitizing cdclk programmed by pre-os\n");
> >  
> >  	sanitized_state.ref = dev_priv->cdclk.hw.ref;
> > -	sanitized_state.cdclk = icl_calc_cdclk(0, sanitized_state.ref);
> > +	sanitized_state.cdclk = icl_calc_cdclk(dev_priv, 0,
> > +					       sanitized_state.ref);
> >  	sanitized_state.vco = icl_calc_cdclk_pll_vco(dev_priv,
> >  						     sanitized_state.cd
> > clk);
> >  	sanitized_state.voltage_level =
> > @@ -2554,7 +2562,7 @@ static int icl_modeset_calc_cdclk(struct
> > intel_atomic_state *state)
> >  	if (min_cdclk < 0)
> >  		return min_cdclk;
> >  
> > -	cdclk = icl_calc_cdclk(min_cdclk, ref);
> > +	cdclk = icl_calc_cdclk(dev_priv, min_cdclk, ref);
> >  	vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> >  
> >  	state->cdclk.logical.vco = vco;
> > @@ -2564,7 +2572,8 @@ static int icl_modeset_calc_cdclk(struct
> > intel_atomic_state *state)
> >  		    cnl_compute_min_voltage_level(state));
> >  
> >  	if (!state->active_crtcs) {
> > -		cdclk = icl_calc_cdclk(state->cdclk.force_min_cdclk,
> > ref);
> > +		cdclk = icl_calc_cdclk(dev_priv, state-
> > >cdclk.force_min_cdclk,
> > +				       ref);
> >  		vco = icl_calc_cdclk_pll_vco(dev_priv, cdclk);
> >  
> >  		state->cdclk.actual.vco = vco;
> > -- 
> > 2.22.0
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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